[gcc r17-3325] RISC-V: Add more test cases for vwmaccsu.vv

https://gcc.gnu.org/g:95dd5ea480d2b81e3075db75c0aedb5684b4f943

commit r17-3325-g95dd5ea480d2b81e3075db75c0aedb5684b4f943
Author: Pan Li <[email protected]>
Date:   Fri Aug 14 09:31:55 2026 +0800

    RISC-V: Add more test cases for vwmaccsu.vv
    
    For csrr not asm check when enable overlap enabled.
    
    gcc/testsuite/ChangeLog:
    
            * gcc.target/riscv/rvv/base/pr112431-51.c: New test.
    
    Signed-off-by: Pan Li <[email protected]>

Diff:
---
 .../gcc.target/riscv/rvv/base/pr112431-51.c        | 69 ++++++++++++++++++++++
 1 file changed, 69 insertions(+)

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-51.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-51.c
new file mode 100644
index 000000000000..98b10093185e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-51.c
@@ -0,0 +1,69 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3" } */
+
+#include "riscv_vector.h"
+
+void
+foo (void *in, void *out, int n)
+{
+  for (int i = 0; i < n; i++)
+    {
+      asm volatile("nop" ::: "memory");
+      vint16m4_t v0 = __riscv_vle16_v_i16m4 (in, 4);in+=100;
+      vint8m2_t v0_n = __riscv_vreinterpret_v_i16m2_i8m2 (__riscv_vget_v_i16m4_i16m2 (v0, 1));
+      vuint8m2_t v0_nu = __riscv_vreinterpret_v_i8m2_u8m2 (v0_n);
+      v0 = __riscv_vwmaccsu_vv_i16m4_tu (v0, v0_n, v0_nu, 4);
+      asm volatile("nop" ::: "memory");
+      vint16m4_t v1 = __riscv_vle16_v_i16m4 (in, 4);in+=100;
+      vint8m2_t v1_n = __riscv_vreinterpret_v_i16m2_i8m2 (__riscv_vget_v_i16m4_i16m2 (v1, 1));
+      vuint8m2_t v1_nu = __riscv_vreinterpret_v_i8m2_u8m2 (v1_n);
+      v1 = __riscv_vwmaccsu_vv_i16m4_tu (v1, v1_n, v1_nu, 4);
+      asm volatile("nop" ::: "memory");
+      vint16m4_t v2 = __riscv_vle16_v_i16m4 (in, 4);in+=100;
+      vint8m2_t v2_n = __riscv_vreinterpret_v_i16m2_i8m2 (__riscv_vget_v_i16m4_i16m2 (v2, 1));
+      vuint8m2_t v2_nu = __riscv_vreinterpret_v_i8m2_u8m2 (v2_n);
+      v2 = __riscv_vwmaccsu_vv_i16m4_tu (v2, v2_n, v2_nu, 4);
+      asm volatile("nop" ::: "memory");
+      vint16m4_t v3 = __riscv_vle16_v_i16m4 (in, 4);in+=100;
+      vint8m2_t v3_n = __riscv_vreinterpret_v_i16m2_i8m2 (__riscv_vget_v_i16m4_i16m2 (v3, 1));
+      vuint8m2_t v3_nu = __riscv_vreinterpret_v_i8m2_u8m2 (v3_n);
+      v3 = __riscv_vwmaccsu_vv_i16m4_tu (v3, v3_n, v3_nu, 4);
+      asm volatile("nop" ::: "memory");
+      vint16m4_t v4 = __riscv_vle16_v_i16m4 (in, 4);in+=100;
+      vint8m2_t v4_n = __riscv_vreinterpret_v_i16m2_i8m2 (__riscv_vget_v_i16m4_i16m2 (v4, 1));
+      vuint8m2_t v4_nu = __riscv_vreinterpret_v_i8m2_u8m2 (v4_n);
+      v4 = __riscv_vwmaccsu_vv_i16m4_tu (v4, v4_n, v4_nu, 4);
+      asm volatile("nop" ::: "memory");
+      vint16m4_t v5 = __riscv_vle16_v_i16m4 (in, 4);in+=100;
+      vint8m2_t v5_n = __riscv_vreinterpret_v_i16m2_i8m2 (__riscv_vget_v_i16m4_i16m2 (v5, 1));
+      vuint8m2_t v5_nu = __riscv_vreinterpret_v_i8m2_u8m2 (v5_n);
+      v5 = __riscv_vwmaccsu_vv_i16m4_tu (v5, v5_n, v5_nu, 4);
+      asm volatile("nop" ::: "memory");
+      vint16m4_t v6 = __riscv_vle16_v_i16m4 (in, 4);in+=100;
+      vint8m2_t v6_n = __riscv_vreinterpret_v_i16m2_i8m2 (__riscv_vget_v_i16m4_i16m2 (v6, 1));
+      vuint8m2_t v6_nu = __riscv_vreinterpret_v_i8m2_u8m2 (v6_n);
+      v6 = __riscv_vwmaccsu_vv_i16m4_tu (v6, v6_n, v6_nu, 4);
+      asm volatile("nop" ::: "memory");
+      vint8m2_t v7_n = __riscv_vle8_v_i8m2 (in, 4);in+=100;
+      vint16m4_t v7 = __riscv_vwcvt_x_x_v_i16m4 (v7_n, 4);
+
+      asm volatile("nop" ::: "memory");
+      __riscv_vsse16_v_i16m4 (out, 4, v0, 4);out+=100;
+      __riscv_vsse16_v_i16m4 (out, 4, v1, 4);out+=100;
+      __riscv_vsse16_v_i16m4 (out, 4, v2, 4);out+=100;
+      __riscv_vsse16_v_i16m4 (out, 4, v3, 4);out+=100;
+      __riscv_vsse16_v_i16m4 (out, 4, v4, 4);out+=100;
+      __riscv_vsse16_v_i16m4 (out, 4, v5, 4);out+=100;
+      __riscv_vsse16_v_i16m4 (out, 4, v6, 4);out+=100;
+      __riscv_vsse16_v_i16m4 (out, 4, v7, 4);out+=100;
+    }
+}
+
+/* Both narrowed sources are the highest-numbered half of the accumulator, thus
+   they overlap the destination register group.  */
+/* { dg-final { scan-assembler-times {vwmaccsu\.vv\s+v4,v6,v6([^0-9]|$)} 7 } } */
+/* { dg-final { scan-assembler-not {vmv1r} } } */
+/* { dg-final { scan-assembler-not {vmv2r} } } */
+/* { dg-final { scan-assembler-not {vmv4r} { xfail riscv*-*-* } } } */
+/* { dg-final { scan-assembler-not {vmv8r} } } */
+/* { dg-final { scan-assembler-not {csrr} } } */