[gcc r17-3366] AVR: invoke.texi (AVR Options): Sort alphabetically.

https://gcc.gnu.org/g:34852f3a769a5e2e6c2e7798d88fedf39c500614

commit r17-3366-g34852f3a769a5e2e6c2e7798d88fedf39c500614
Author: Georg-Johann Lay <[email protected]>
Date:   Tue Aug 18 14:01:28 2026 +0200

    AVR: invoke.texi (AVR Options): Sort alphabetically.
    
    gcc/
            * doc/invoke.texi (AVR Options): Sort alphabetically.

Diff:
---
 gcc/doc/invoke.texi | 78 ++++++++++++++++++++++++++---------------------------
 1 file changed, 39 insertions(+), 39 deletions(-)

diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi
index d6cfc4598531..85491759020b 100644
--- a/gcc/doc/invoke.texi
+++ b/gcc/doc/invoke.texi
@@ -24390,6 +24390,10 @@ the @code{--with-double=} and @code{--with-long-double=}
 @w{@uref{https://gcc.gnu.org/install/configure.html#avr,,configure options}},
 and the same applies for the default values of the options.
 
+@opindex mfract-convert-truncate
+@item -mfract-convert-truncate
+Allow to use truncation instead of rounding towards zero for fractional fixed-point types.
+
 @opindex mgas-isr-prologues
 @item -mgas-isr-prologues
 Interrupt service routines (ISRs) may use the @code{__gcc_isr} pseudo
@@ -24437,22 +24441,6 @@ With older versions, there will be no performance gain.
 Generated code is not compatible with hardware interrupts.
 Code size is smaller.
 
-@opindex mrelax
-@item -mrelax
-Try to replace @code{CALL} resp.@: @code{JMP} instruction by the shorter
-@code{RCALL} resp.@: @code{RJMP} instruction if applicable.
-Setting @option{-mrelax} just adds the @option{--mlink-relax} option to
-the assembler's command line and the @option{--relax} option to the
-linker's command line.
-
-Jump relaxing is performed by the linker because jump offsets are not
-known before code is located. Therefore, the assembler code generated by the
-compiler is the same, but the instructions in the executable may
-differ from instructions in the assembler code.
-
-Relaxing must be turned on if linker stubs are needed, see the
-section on @code{EIND} and linker stubs below.
-
 @opindex mpmem-wrap-around
 @opindex mno-pmem-wrap-around
 @item -mpmem-wrap-around
@@ -24472,14 +24460,43 @@ support (@w{@uref{https://sourceware.org/PR31124,,PR31124}}) is available.
 In that case, @option{-mrodata-in-ram} can be used to return to the old
 layout with @code{.rodata} in RAM.
 
+@opindex mrelax
+@item -mrelax
+Try to replace @code{CALL} resp.@: @code{JMP} instruction by the shorter
+@code{RCALL} resp.@: @code{RJMP} instruction if applicable.
+Setting @option{-mrelax} just adds the @option{--mlink-relax} option to
+the assembler's command line and the @option{--relax} option to the
+linker's command line.
+
+Jump relaxing is performed by the linker because jump offsets are not
+known before code is located. Therefore, the assembly code generated by the
+compiler is the same, but the instructions in the executable may
+differ from instructions in the assembly code.
+
+Relaxing must be turned on if linker stubs are needed, see the
+section on @code{EIND} and linker stubs below.
+
+@opindex mstrict-addr-space-subsets
+@item -mstrict-addr-space-subsets
+Impose strict named address space subset relations.  Without this option,
+every address space is considered to be a subset of all the other spaces,
+which allows to write code like
+@example
+char read_char (const char *addr, bool in_flash)
+@{
+   return in_flash
+     ? *(const __flash char*) addr  // Read from program memory.
+     : *addr;                       // Read from RAM.
+@}
+@end example
+When the option is on, such code is rejected since address space
+@code{__flash} is not a subset of the generic space, and hence the
+cast in the above code is prohibited.
+
 @opindex mtiny-stack
 @item -mtiny-stack
 Only change the lower 8@tie{}bits of the stack pointer.
 
-@opindex mfract-convert-truncate
-@item -mfract-convert-truncate
-Allow to use truncation instead of rounding towards zero for fractional fixed-point types.
-
 @opindex nodevicelib
 @item -nodevicelib
 Don't link against AVR-LibC's device specific library @code{lib@var{mcu}.a}.
@@ -24595,23 +24612,6 @@ aspect of the optimization.
 @item -mfuse-move2
 Run a post combine optimization pass that tries to fuse move instructions.
 
-@opindex mstrict-addr-space-subsets
-@item -mstrict-addr-space-subsets
-Impose strict named address space subset relations.  Without this option,
-every address space is considered to be a subset of all the other spaces,
-which allows to write code like
-@example
-char read_char (const char *addr, bool in_flash)
-@{
-   return in_flash
-     ? *(const __flash char*) addr  // Read from program memory.
-     : *addr;                       // Read from RAM.
-@}
-@end example
-When the option is on, such code is rejected since address space
-@code{__flash} is not a subset of the generic space, and hence the
-cast in the above code is prohibited.
-
 @opindex mstrict-X
 @item -mstrict-X
 Use address register @code{X} in a way proposed by the hardware.  This means
@@ -24827,7 +24827,7 @@ zero in case the ISR code might (implicitly) use it.
 
 @item
 RAM larger than 64@tie{}KiB is not supported by GCC for AVR targets.
-If you use inline assembler to read from locations outside the
+If you use inline assembly to read from locations outside the
 16-bit address range and change one of the @code{RAMP} registers,
 you must reset it to zero after the access.
 
@@ -25000,7 +25000,7 @@ This macro is defined provided the following conditions are met:
 @itemize @bullet
 @item The device has the @code{NVMCTRL_CTRLB.FLMAP} bitfield.
 This applies to the AVR64* and AVR128* devices.
-@item It's not known at assembler-time which emulation will be used.
+@item It's not known at assemble-time which emulation will be used.
 @end itemize
 This implies the compiler was configured with GNU Binutils that implement
 @w{@uref{https://sourceware.org/PR31124,,PR31124}}.