[gcc r17-3412] vec-narrow-1.C/vec-narrow-minmax-2.C: Compile with -msse4 and require int128

https://gcc.gnu.org/g:d8a26b20e474d15e1842321be0a7163e52e68442

commit r17-3412-gd8a26b20e474d15e1842321be0a7163e52e68442
Author: H.J. Lu <[email protected]>
Date:   Tue Aug 11 12:39:54 2026 +0800

    vec-narrow-1.C/vec-narrow-minmax-2.C: Compile with -msse4 and require int128
    
    128bit vector smaxmin and umaxmin are added to SSE4.  They don't require
    AVX512VL nor AVX512DQ.  Also mmx.md has
    
    (define_insn "<code><mode>3"
      [(set (match_operand:MMXMODE14 0 "register_operand" "=Yr,*x,Yv")
        (smaxmin:MMXMODE14
          (match_operand:MMXMODE14 1 "register_operand" "%0,0,Yv")
          (match_operand:MMXMODE14 2 "register_operand" "Yr,*x,Yv")))]
      "TARGET_SSE4_1 && TARGET_MMX_WITH_SSE"
      "@
       p<maxmin_int><mmxvecsize>\t{%2, %0|%0, %2}
       p<maxmin_int><mmxvecsize>\t{%2, %0|%0, %2}
       vp<maxmin_int><mmxvecsize>\t{%2, %1, %0|%0, %1, %2}"
      [(set_attr "isa" "noavx,noavx,avx")
       (set_attr "type" "sseiadd")
       (set_attr "prefix_extra" "1")
       (set_attr "prefix" "orig,orig,vex")
       (set_attr "mode" "TI")])
    
    (define_insn "<code><mode>3"
      [(set (match_operand:MMXMODE24 0 "register_operand" "=Yr,*x,Yv")
        (umaxmin:MMXMODE24
          (match_operand:MMXMODE24 1 "register_operand" "%0,0,Yv")
          (match_operand:MMXMODE24 2 "register_operand" "Yr,*x,Yv")))]
      "TARGET_SSE4_1 && TARGET_MMX_WITH_SSE"
      "@
       p<maxmin_int><mmxvecsize>\t{%2, %0|%0, %2}
       p<maxmin_int><mmxvecsize>\t{%2, %0|%0, %2}
       vp<maxmin_int><mmxvecsize>\t{%2, %1, %0|%0, %1, %2}"
      [(set_attr "isa" "noavx,noavx,avx")
       (set_attr "type" "sseiadd")
       (set_attr "prefix_extra" "1")
       (set_attr "prefix" "orig,orig,vex")
       (set_attr "mode" "TI")])
    
    These patterns require TARGET_MMX_WITH_SSE
    
     #define TARGET_MMX_WITH_SSE     (TARGET_64BIT && TARGET_SSE2)
    
    64-bit vector smaxmin and umaxmin aren't available for ia32 even with
    -mmmx.  Compile vec-narrow-1.C and vec-narrow-minmax-2.C with -msse4 and
    require int128 for x86.
    
            PR middle-end/126784
            * g++.dg/tree-ssa/vec-narrow-1.C: Remove -Wno-psabi.  Add -msse4
            and require int128 for x86.
            * g++.dg/tree-ssa/vec-narrow-minmax-2.C: Likewise.
    
    Signed-off-by: H.J. Lu <[email protected]>

Diff:
---
 gcc/testsuite/g++.dg/tree-ssa/vec-narrow-1.C        | 6 +++---
 gcc/testsuite/g++.dg/tree-ssa/vec-narrow-minmax-2.C | 4 +++-
 2 files changed, 6 insertions(+), 4 deletions(-)

diff --git a/gcc/testsuite/g++.dg/tree-ssa/vec-narrow-1.C b/gcc/testsuite/g++.dg/tree-ssa/vec-narrow-1.C
index 7af111875017..1f863b1d4a24 100644
--- a/gcc/testsuite/g++.dg/tree-ssa/vec-narrow-1.C
+++ b/gcc/testsuite/g++.dg/tree-ssa/vec-narrow-1.C
@@ -1,7 +1,7 @@
 // { dg-do compile }
-// { dg-options "-O2 -fdump-tree-optimized -Wno-psabi" }
-// { dg-additional-options "-mavx512vl -mavx512dq" { target { i?86-*-* x86_64-*-* } } }
-// { dg-additional-options "-mmmx" { target ia32 } }
+// { dg-options "-O2 -fdump-tree-optimized" }
+// { dg-additional-options "-msse4" { target { i?86-*-* x86_64-*-* } } }
+// { dg-require-effective-target int128 { target { i?86-*-* x86_64-*-* } } }
 // Extension is monotone, so it commutes with the comparison and the outer
 // truncation is exact.  The argument is lanewise, so a widened vector
 // MIN/MAX feeding a truncating conversion narrows.
diff --git a/gcc/testsuite/g++.dg/tree-ssa/vec-narrow-minmax-2.C b/gcc/testsuite/g++.dg/tree-ssa/vec-narrow-minmax-2.C
index 74177f7864e7..7df25de0942a 100644
--- a/gcc/testsuite/g++.dg/tree-ssa/vec-narrow-minmax-2.C
+++ b/gcc/testsuite/g++.dg/tree-ssa/vec-narrow-minmax-2.C
@@ -1,5 +1,7 @@
 // { dg-do compile }
-// { dg-options "-O2 -fdump-tree-optimized -Wno-psabi" }
+// { dg-options "-O2 -fdump-tree-optimized" }
+// { dg-additional-options "-msse4" { target { i?86-*-* x86_64-*-* } } }
+// { dg-require-effective-target int128 { target { i?86-*-* x86_64-*-* } } }
 
 typedef int v2si __attribute__((vector_size (8)));
 typedef long long v2di __attribute__((vector_size (16)));