[gcc r17-3432] aarch64: Update FEAT_TPS and FEAT_TPSP system registers
Alice Carlotti via Gcc-cvs <[email protected]>
| Newsgroups | gmane.comp.gcc.cvs |
|---|---|
| Message-ID | <[email protected]> |
https://gcc.gnu.org/g:3c22c9f398e4b2fd1abe48af408578c847f81d51 commit r17-3432-g3c22c9f398e4b2fd1abe48af408578c847f81d51 Author: Alice Carlotti <[email protected]> Date: Wed Aug 19 16:52:54 2026 +0100 aarch64: Update FEAT_TPS and FEAT_TPSP system registers The specification has been changed to use individual tpcr* registers, instead of the original tpmin*/tpmax* pairs. Copy the updated file from Binutils. gcc/ChangeLog: * config/aarch64/aarch64-sys-regs.def: Sync from Binutils. Diff: --- gcc/config/aarch64/aarch64-sys-regs.def | 24 ++++++++---------------- 1 file changed, 8 insertions(+), 16 deletions(-) diff --git a/gcc/config/aarch64/aarch64-sys-regs.def b/gcc/config/aarch64/aarch64-sys-regs.def index 1efbc3f3de5a..f6f2bc7eb925 100644 --- a/gcc/config/aarch64/aarch64-sys-regs.def +++ b/gcc/config/aarch64/aarch64-sys-regs.def @@ -1357,6 +1357,14 @@ SYSREG ("tindex_el2", CPENC (3,4,4,0,3), 0, AARCH64_FEATURE (POE2)) SYSREG ("tindex_el3", CPENC (3,6,4,0,3), 0, AARCH64_FEATURE (POE2)) SYSREG ("tlbididr_el1", CPENC (3,0,10,4,6), F_REG_READ, AARCH64_FEATURE (TLBID)) + SYSREG ("tpcr0_el0", CPENC (3,3,2,2,4), 0, AARCH64_NO_FEATURES) + SYSREG ("tpcr0_el1", CPENC (3,0,2,2,4), 0, AARCH64_NO_FEATURES) + SYSREG ("tpcr0_el12", CPENC (3,5,2,2,4), 0, AARCH64_NO_FEATURES) + SYSREG ("tpcr0_el2", CPENC (3,4,2,2,4), 0, AARCH64_NO_FEATURES) + SYSREG ("tpcr1_el0", CPENC (3,3,2,2,5), 0, AARCH64_NO_FEATURES) + SYSREG ("tpcr1_el1", CPENC (3,0,2,2,5), 0, AARCH64_NO_FEATURES) + SYSREG ("tpcr1_el12", CPENC (3,5,2,2,5), 0, AARCH64_NO_FEATURES) + SYSREG ("tpcr1_el2", CPENC (3,4,2,2,5), 0, AARCH64_NO_FEATURES) SYSREG ("tpidr2_el0", CPENC (3,3,13,0,5), 0, AARCH64_FEATURE (SME)) SYSREG ("tpidr3_el0", CPENC (3,3,13,0,0), 0, AARCH64_FEATURE (POE2)) SYSREG ("tpidr3_el1", CPENC (3,0,13,0,0), 0, AARCH64_FEATURE (POE2)) @@ -1368,22 +1376,6 @@ SYSREG ("tpidr_el2", CPENC (3,4,13,0,2), 0, AARCH64_NO_FEATURES) SYSREG ("tpidr_el3", CPENC (3,6,13,0,2), 0, AARCH64_NO_FEATURES) SYSREG ("tpidrro_el0", CPENC (3,3,13,0,3), 0, AARCH64_NO_FEATURES) - SYSREG ("tpmax0_el0", CPENC (3,3,2,2,5), 0, AARCH64_NO_FEATURES) - SYSREG ("tpmax0_el1", CPENC (3,0,2,2,5), 0, AARCH64_NO_FEATURES) - SYSREG ("tpmax0_el12", CPENC (3,5,2,2,5), 0, AARCH64_NO_FEATURES) - SYSREG ("tpmax0_el2", CPENC (3,4,2,2,5), 0, AARCH64_NO_FEATURES) - SYSREG ("tpmax1_el0", CPENC (3,3,2,2,7), 0, AARCH64_NO_FEATURES) - SYSREG ("tpmax1_el1", CPENC (3,0,2,2,7), 0, AARCH64_NO_FEATURES) - SYSREG ("tpmax1_el12", CPENC (3,5,2,2,7), 0, AARCH64_NO_FEATURES) - SYSREG ("tpmax1_el2", CPENC (3,4,2,2,7), 0, AARCH64_NO_FEATURES) - SYSREG ("tpmin0_el0", CPENC (3,3,2,2,4), 0, AARCH64_NO_FEATURES) - SYSREG ("tpmin0_el1", CPENC (3,0,2,2,4), 0, AARCH64_NO_FEATURES) - SYSREG ("tpmin0_el12", CPENC (3,5,2,2,4), 0, AARCH64_NO_FEATURES) - SYSREG ("tpmin0_el2", CPENC (3,4,2,2,4), 0, AARCH64_NO_FEATURES) - SYSREG ("tpmin1_el0", CPENC (3,3,2,2,6), 0, AARCH64_NO_FEATURES) - SYSREG ("tpmin1_el1", CPENC (3,0,2,2,6), 0, AARCH64_NO_FEATURES) - SYSREG ("tpmin1_el12", CPENC (3,5,2,2,6), 0, AARCH64_NO_FEATURES) - SYSREG ("tpmin1_el2", CPENC (3,4,2,2,6), 0, AARCH64_NO_FEATURES) SYSREG ("trbbaser_el1", CPENC (3,0,9,11,2), 0, AARCH64_FEATURE (V9A)) /* TRBE */ SYSREG ("trbidr_el1", CPENC (3,0,9,11,7), F_REG_READ, AARCH64_FEATURE (V9A)) /* TRBE */ SYSREG ("trblimitr_el1", CPENC (3,0,9,11,0), 0, AARCH64_FEATURE (V9A)) /* TRBE */