[gcc r15-11495] i386: Disallow APX EGPR in FMA4/XOP insns [PR target/126787]
Hongyu Wang via Gcc-cvs <[email protected]>
| Newsgroups | gmane.comp.gcc.cvs |
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https://gcc.gnu.org/g:68c97e6444b8478a45645348fcda43792448f4c2 commit r15-11495-g68c97e6444b8478a45645348fcda43792448f4c2 Author: Hongyu Wang <[email protected]> Date: Tue Aug 11 16:57:48 2026 +0800 i386: Disallow APX EGPR in FMA4/XOP insns [PR target/126787] FMA4 and XOP instructions are VEX-only, so cannot be promoted to EVEX form. When enforcing -mapxf on such target clone, which is at --with-arch=native plus libgfortran bootstrap on Diamond Rapids or Nova Lake, the fma4 clone may generate unencodable vfmaddps with egpr in mem. Restrict all the FMA4/XOP patterns with replacing 'm' to 'jm' and add gpr16 to the addr attribute to avoid egpr usage under high register pressure. gcc/ChangeLog: PR target/126787 * config/i386/sse.md (*fma_fmadd_<mode>): Use the "jm" to replace "m" constraint and set addr attribute to "gpr16" for vex only alternatives. (*fma_fmsub_<mode>): Likewise. (*fma_fnmadd_<mode>): Likewise. (*fma_fnmsub_<mode>): Likewise. (*fma_fmaddsub_<mode>): Likewise. (*fma_fmsubadd_<mode>): Likewise. (xop_p<macs><ssemodesuffix><ssemodesuffix>): Likewise. (xop_p<macs>dql): Likewise. (xop_p<macs>dqh): Likewise. (xop_p<macs>wd): Likewise. (xop_p<madcs>wd): Likewise. (xop_pcmov_<mode><avxsizesuffix>): Likewise. (xop_phadd<u>bw): Likewise. (xop_phadd<u>bd): Likewise. (xop_phadd<u>bq): Likewise. (xop_phadd<u>wd): Likewise. (xop_phadd<u>wq): Likewise. (xop_phadd<u>dq): Likewise. (xop_phsubbw): Likewise. (xop_phsubwd): Likewise. (xop_phsubdq): Likewise. (xop_pperm): Likewise. (xop_pperm_pack_v2di_v4si): Likewise. (xop_pperm_pack_v4si_v8hi): Likewise. (xop_pperm_pack_v8hi_v16qi): Likewise. (xop_rotl<mode>3): Likewise. (xop_rotr<mode>3): Likewise. (xop_vrotl<mode>3): Likewise. (xop_sha<mode>3): Likewise. (xop_shl<mode>3): Likewise. (xop_frcz<mode>2): Likewise. (*xop_vmfrcz<mode>2): Likewise. (xop_maskcmp<mode>3): Likewise. (xop_maskcmp_uns<mode>3): Likewise. (xop_maskcmp_uns2<mode>3): Likewise. (xop_pcom_tf<mode>3): Likewise. (xop_vpermil2<mode>3): Likewise. gcc/testsuite/ChangeLog: PR target/126787 * gcc.target/i386/pr126787.c: New test. (cherry picked from commit 475e9efffaf8de781d7e17b687faf1807e104b01) Diff: --- gcc/config/i386/sse.md | 141 +++++++++++++++++++------------ gcc/testsuite/gcc.target/i386/pr126787.c | 15 ++++ 2 files changed, 104 insertions(+), 52 deletions(-) diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md index 1aa3b49067f3..060b3dfdc97f 100644 --- a/gcc/config/i386/sse.md +++ b/gcc/config/i386/sse.md @@ -5947,8 +5947,8 @@ [(set (match_operand:FMAMODE 0 "register_operand" "=v,v,v,x,x") (fma:FMAMODE (match_operand:FMAMODE 1 "nonimmediate_operand" "%0,0,v,x,x") - (match_operand:FMAMODE 2 "nonimmediate_operand" "vm,v,vm,x,m") - (match_operand:FMAMODE 3 "nonimmediate_operand" "v,vm,0,xm,x")))] + (match_operand:FMAMODE 2 "nonimmediate_operand" "vm,v,vm,x,jm") + (match_operand:FMAMODE 3 "nonimmediate_operand" "v,vm,0,xjm,x")))] "TARGET_FMA || TARGET_FMA4" "@ vfmadd132<ssemodesuffix>\t{%2, %3, %0|%0, %3, %2} @@ -5958,6 +5958,7 @@ vfmadd<ssemodesuffix>\t{%3, %2, %1, %0|%0, %1, %2, %3}" [(set_attr "isa" "fma,fma,fma,fma4,fma4") (set_attr "type" "ssemuladd") + (set_attr "addr" "*,*,*,gpr16,gpr16") (set_attr "mode" "<MODE>")]) ;; Suppose AVX-512F as baseline @@ -6045,9 +6046,9 @@ [(set (match_operand:FMAMODE 0 "register_operand" "=v,v,v,x,x") (fma:FMAMODE (match_operand:FMAMODE 1 "nonimmediate_operand" "%0,0,v,x,x") - (match_operand:FMAMODE 2 "nonimmediate_operand" "vm,v,vm,x,m") + (match_operand:FMAMODE 2 "nonimmediate_operand" "vm,v,vm,x,jm") (neg:FMAMODE - (match_operand:FMAMODE 3 "nonimmediate_operand" "v,vm,0,xm,x"))))] + (match_operand:FMAMODE 3 "nonimmediate_operand" "v,vm,0,xjm,x"))))] "TARGET_FMA || TARGET_FMA4" "@ vfmsub132<ssemodesuffix>\t{%2, %3, %0|%0, %3, %2} @@ -6057,6 +6058,7 @@ vfmsub<ssemodesuffix>\t{%3, %2, %1, %0|%0, %1, %2, %3}" [(set_attr "isa" "fma,fma,fma,fma4,fma4") (set_attr "type" "ssemuladd") + (set_attr "addr" "*,*,*,gpr16,gpr16") (set_attr "mode" "<MODE>")]) (define_expand "<avx512>_fmsub_<mode>_maskz<round_expand_name>" @@ -6152,8 +6154,8 @@ (fma:FMAMODE (neg:FMAMODE (match_operand:FMAMODE 1 "nonimmediate_operand" "%0,0,v,x,x")) - (match_operand:FMAMODE 2 "nonimmediate_operand" "vm,v,vm,x,m") - (match_operand:FMAMODE 3 "nonimmediate_operand" "v,vm,0,xm,x")))] + (match_operand:FMAMODE 2 "nonimmediate_operand" "vm,v,vm,x,jm") + (match_operand:FMAMODE 3 "nonimmediate_operand" "v,vm,0,xjm,x")))] "TARGET_FMA || TARGET_FMA4" "@ vfnmadd132<ssemodesuffix>\t{%2, %3, %0|%0, %3, %2} @@ -6163,6 +6165,7 @@ vfnmadd<ssemodesuffix>\t{%3, %2, %1, %0|%0, %1, %2, %3}" [(set_attr "isa" "fma,fma,fma,fma4,fma4") (set_attr "type" "ssemuladd") + (set_attr "addr" "*,*,*,gpr16,gpr16") (set_attr "mode" "<MODE>")]) (define_expand "<avx512>_fnmadd_<mode>_maskz<round_expand_name>" @@ -6258,9 +6261,9 @@ (fma:FMAMODE (neg:FMAMODE (match_operand:FMAMODE 1 "nonimmediate_operand" "%0,0,v,x,x")) - (match_operand:FMAMODE 2 "nonimmediate_operand" "vm,v,vm,x,m") + (match_operand:FMAMODE 2 "nonimmediate_operand" "vm,v,vm,x,jm") (neg:FMAMODE - (match_operand:FMAMODE 3 "nonimmediate_operand" "v,vm,0,xm,x"))))] + (match_operand:FMAMODE 3 "nonimmediate_operand" "v,vm,0,xjm,x"))))] "TARGET_FMA || TARGET_FMA4" "@ vfnmsub132<ssemodesuffix>\t{<round_sd_mask_op4>%2, %3, %0<sd_mask_op4>|%0<sd_mask_op4>, %3, %2<round_sd_mask_op4>} @@ -6270,6 +6273,7 @@ vfnmsub<ssemodesuffix>\t{%3, %2, %1, %0|%0, %1, %2, %3}" [(set_attr "isa" "fma,fma,fma,fma4,fma4") (set_attr "type" "ssemuladd") + (set_attr "addr" "*,*,*,gpr16,gpr16") (set_attr "mode" "<MODE>")]) (define_expand "<avx512>_fnmsub_<mode>_maskz<round_expand_name>" @@ -6435,8 +6439,8 @@ [(set (match_operand:VF_128_256 0 "register_operand" "=v,v,v,x,x") (unspec:VF_128_256 [(match_operand:VF_128_256 1 "nonimmediate_operand" "%0,0,v,x,x") - (match_operand:VF_128_256 2 "nonimmediate_operand" "vm,v,vm,x,m") - (match_operand:VF_128_256 3 "nonimmediate_operand" "v,vm,0,xm,x")] + (match_operand:VF_128_256 2 "nonimmediate_operand" "vm,v,vm,x,jm") + (match_operand:VF_128_256 3 "nonimmediate_operand" "v,vm,0,xjm,x")] UNSPEC_FMADDSUB))] "TARGET_FMA || TARGET_FMA4" "@ @@ -6447,6 +6451,7 @@ vfmaddsub<ssemodesuffix>\t{%3, %2, %1, %0|%0, %1, %2, %3}" [(set_attr "isa" "fma,fma,fma,fma4,fma4") (set_attr "type" "ssemuladd") + (set_attr "addr" "*,*,*,gpr16,gpr16") (set_attr "mode" "<MODE>")]) (define_insn "<sd_mask_codefor>fma_fmaddsub_<mode><sd_maskz_name><round_name>" @@ -6503,9 +6508,9 @@ [(set (match_operand:VF_128_256 0 "register_operand" "=v,v,v,x,x") (unspec:VF_128_256 [(match_operand:VF_128_256 1 "nonimmediate_operand" "%0,0,v,x,x") - (match_operand:VF_128_256 2 "nonimmediate_operand" "vm,v,vm,x,m") + (match_operand:VF_128_256 2 "nonimmediate_operand" "vm,v,vm,x,jm") (neg:VF_128_256 - (match_operand:VF_128_256 3 "nonimmediate_operand" "v,vm,0,xm,x"))] + (match_operand:VF_128_256 3 "nonimmediate_operand" "v,vm,0,xjm,x"))] UNSPEC_FMADDSUB))] "TARGET_FMA || TARGET_FMA4" "@ @@ -6516,6 +6521,7 @@ vfmsubadd<ssemodesuffix>\t{%3, %2, %1, %0|%0, %1, %2, %3}" [(set_attr "isa" "fma,fma,fma,fma4,fma4") (set_attr "type" "ssemuladd") + (set_attr "addr" "*,*,*,gpr16,gpr16") (set_attr "mode" "<MODE>")]) (define_insn "<sd_mask_codefor>fma_fmsubadd_<mode><sd_maskz_name><round_name>" @@ -26509,12 +26515,13 @@ (xop_plus:VI24_128 (mult:VI24_128 (match_operand:VI24_128 1 "nonimmediate_operand" "%x") - (match_operand:VI24_128 2 "nonimmediate_operand" "xm")) + (match_operand:VI24_128 2 "nonimmediate_operand" "xjm")) (match_operand:VI24_128 3 "register_operand" "x")))] "TARGET_XOP" "vp<macs><ssemodesuffix><ssemodesuffix>\t{%3, %2, %1, %0|%0, %1, %2, %3}" [(set_attr "type" "ssemuladd") (set_attr "prefix" "vex") + (set_attr "addr" "gpr16") (set_attr "mode" "TI")]) (define_insn "xop_p<macs>dql" @@ -26527,13 +26534,14 @@ (parallel [(const_int 0) (const_int 2)]))) (sign_extend:V2DI (vec_select:V2SI - (match_operand:V4SI 2 "nonimmediate_operand" "xm") + (match_operand:V4SI 2 "nonimmediate_operand" "xjm") (parallel [(const_int 0) (const_int 2)])))) (match_operand:V2DI 3 "register_operand" "x")))] "TARGET_XOP" "vp<macs>dql\t{%3, %2, %1, %0|%0, %1, %2, %3}" [(set_attr "type" "ssemuladd") (set_attr "prefix" "vex") + (set_attr "addr" "gpr16") (set_attr "mode" "TI")]) (define_insn "xop_p<macs>dqh" @@ -26546,13 +26554,14 @@ (parallel [(const_int 1) (const_int 3)]))) (sign_extend:V2DI (vec_select:V2SI - (match_operand:V4SI 2 "nonimmediate_operand" "xm") + (match_operand:V4SI 2 "nonimmediate_operand" "xjm") (parallel [(const_int 1) (const_int 3)])))) (match_operand:V2DI 3 "register_operand" "x")))] "TARGET_XOP" "vp<macs>dqh\t{%3, %2, %1, %0|%0, %1, %2, %3}" [(set_attr "type" "ssemuladd") (set_attr "prefix" "vex") + (set_attr "addr" "gpr16") (set_attr "mode" "TI")]) ;; XOP parallel integer multiply/add instructions for the intrinisics @@ -26567,7 +26576,7 @@ (const_int 5) (const_int 7)]))) (sign_extend:V4SI (vec_select:V4HI - (match_operand:V8HI 2 "nonimmediate_operand" "xm") + (match_operand:V8HI 2 "nonimmediate_operand" "xjm") (parallel [(const_int 1) (const_int 3) (const_int 5) (const_int 7)])))) (match_operand:V4SI 3 "register_operand" "x")))] @@ -26575,6 +26584,7 @@ "vp<macs>wd\t{%3, %2, %1, %0|%0, %1, %2, %3}" [(set_attr "type" "ssemuladd") (set_attr "prefix" "vex") + (set_attr "addr" "gpr16") (set_attr "mode" "TI")]) (define_insn "xop_p<madcs>wd" @@ -26589,7 +26599,7 @@ (const_int 4) (const_int 6)]))) (sign_extend:V4SI (vec_select:V4HI - (match_operand:V8HI 2 "nonimmediate_operand" "xm") + (match_operand:V8HI 2 "nonimmediate_operand" "xjm") (parallel [(const_int 0) (const_int 2) (const_int 4) (const_int 6)])))) (mult:V4SI @@ -26608,18 +26618,20 @@ "vp<madcs>wd\t{%3, %2, %1, %0|%0, %1, %2, %3}" [(set_attr "type" "ssemuladd") (set_attr "prefix" "vex") + (set_attr "addr" "gpr16") (set_attr "mode" "TI")]) ;; XOP parallel XMM conditional moves (define_insn "xop_pcmov_<mode><avxsizesuffix>" [(set (match_operand:V_128_256 0 "register_operand" "=x,x") (if_then_else:V_128_256 - (match_operand:V_128_256 3 "nonimmediate_operand" "x,m") + (match_operand:V_128_256 3 "nonimmediate_operand" "x,jm") (match_operand:V_128_256 1 "register_operand" "x,x") - (match_operand:V_128_256 2 "nonimmediate_operand" "xm,x")))] + (match_operand:V_128_256 2 "nonimmediate_operand" "xjm,x")))] "TARGET_XOP" "vpcmov\t{%3, %2, %1, %0|%0, %1, %2, %3}" [(set_attr "type" "sse4arg") + (set_attr "addr" "gpr16") (set_attr "mode" "<sseinsnmode>")]) ;; Recognize XOP's vpcmov from canonical (xor (and (xor t f) c) f) @@ -26654,7 +26666,7 @@ (plus:V8HI (any_extend:V8HI (vec_select:V8QI - (match_operand:V16QI 1 "nonimmediate_operand" "xm") + (match_operand:V16QI 1 "nonimmediate_operand" "xjm") (parallel [(const_int 0) (const_int 2) (const_int 4) (const_int 6) (const_int 8) (const_int 10) @@ -26672,6 +26684,7 @@ (set_attr "c86_attr" "hplus") (set_attr "prefix" "vex") (set_attr "prefix_extra" "1") + (set_attr "addr" "gpr16") (set_attr "mode" "TI")]) (define_insn "xop_phadd<u>bd" @@ -26680,7 +26693,7 @@ (plus:V4SI (any_extend:V4SI (vec_select:V4QI - (match_operand:V16QI 1 "nonimmediate_operand" "xm") + (match_operand:V16QI 1 "nonimmediate_operand" "xjm") (parallel [(const_int 0) (const_int 4) (const_int 8) (const_int 12)]))) (any_extend:V4SI @@ -26705,6 +26718,7 @@ (set_attr "c86_attr" "hplus") (set_attr "prefix" "vex") (set_attr "prefix_extra" "1") + (set_attr "addr" "gpr16") (set_attr "mode" "TI")]) (define_insn "xop_phadd<u>bq" @@ -26714,7 +26728,7 @@ (plus:V2DI (any_extend:V2DI (vec_select:V2QI - (match_operand:V16QI 1 "nonimmediate_operand" "xm") + (match_operand:V16QI 1 "nonimmediate_operand" "xjm") (parallel [(const_int 0) (const_int 8)]))) (any_extend:V2DI (vec_select:V2QI @@ -26754,6 +26768,7 @@ (set_attr "c86_attr" "hplus") (set_attr "prefix" "vex") (set_attr "prefix_extra" "1") + (set_attr "addr" "gpr16") (set_attr "mode" "TI")]) (define_insn "xop_phadd<u>wd" @@ -26761,7 +26776,7 @@ (plus:V4SI (any_extend:V4SI (vec_select:V4HI - (match_operand:V8HI 1 "nonimmediate_operand" "xm") + (match_operand:V8HI 1 "nonimmediate_operand" "xjm") (parallel [(const_int 0) (const_int 2) (const_int 4) (const_int 6)]))) (any_extend:V4SI @@ -26775,6 +26790,7 @@ (set_attr "c86_attr" "hplus") (set_attr "prefix" "vex") (set_attr "prefix_extra" "1") + (set_attr "addr" "gpr16") (set_attr "mode" "TI")]) (define_insn "xop_phadd<u>wq" @@ -26783,7 +26799,7 @@ (plus:V2DI (any_extend:V2DI (vec_select:V2HI - (match_operand:V8HI 1 "nonimmediate_operand" "xm") + (match_operand:V8HI 1 "nonimmediate_operand" "xjm") (parallel [(const_int 0) (const_int 4)]))) (any_extend:V2DI (vec_select:V2HI @@ -26804,6 +26820,7 @@ (set_attr "c86_attr" "hplus") (set_attr "prefix" "vex") (set_attr "prefix_extra" "1") + (set_attr "addr" "gpr16") (set_attr "mode" "TI")]) (define_insn "xop_phadd<u>dq" @@ -26811,7 +26828,7 @@ (plus:V2DI (any_extend:V2DI (vec_select:V2SI - (match_operand:V4SI 1 "nonimmediate_operand" "xm") + (match_operand:V4SI 1 "nonimmediate_operand" "xjm") (parallel [(const_int 0) (const_int 2)]))) (any_extend:V2DI (vec_select:V2SI @@ -26823,6 +26840,7 @@ (set_attr "c86_attr" "hplus") (set_attr "prefix" "vex") (set_attr "prefix_extra" "1") + (set_attr "addr" "gpr16") (set_attr "mode" "TI")]) (define_insn "xop_phsubbw" @@ -26830,7 +26848,7 @@ (minus:V8HI (sign_extend:V8HI (vec_select:V8QI - (match_operand:V16QI 1 "nonimmediate_operand" "xm") + (match_operand:V16QI 1 "nonimmediate_operand" "xjm") (parallel [(const_int 0) (const_int 2) (const_int 4) (const_int 6) (const_int 8) (const_int 10) @@ -26848,6 +26866,7 @@ (set_attr "c86_attr" "hplus") (set_attr "prefix" "vex") (set_attr "prefix_extra" "1") + (set_attr "addr" "gpr16") (set_attr "mode" "TI")]) (define_insn "xop_phsubwd" @@ -26855,7 +26874,7 @@ (minus:V4SI (sign_extend:V4SI (vec_select:V4HI - (match_operand:V8HI 1 "nonimmediate_operand" "xm") + (match_operand:V8HI 1 "nonimmediate_operand" "xjm") (parallel [(const_int 0) (const_int 2) (const_int 4) (const_int 6)]))) (sign_extend:V4SI @@ -26869,6 +26888,7 @@ (set_attr "c86_attr" "hplus") (set_attr "prefix" "vex") (set_attr "prefix_extra" "1") + (set_attr "addr" "gpr16") (set_attr "mode" "TI")]) (define_insn "xop_phsubdq" @@ -26876,7 +26896,7 @@ (minus:V2DI (sign_extend:V2DI (vec_select:V2SI - (match_operand:V4SI 1 "nonimmediate_operand" "xm") + (match_operand:V4SI 1 "nonimmediate_operand" "xjm") (parallel [(const_int 0) (const_int 2)]))) (sign_extend:V2DI (vec_select:V2SI @@ -26888,6 +26908,7 @@ (set_attr "c86_attr" "hplus") (set_attr "prefix" "vex") (set_attr "prefix_extra" "1") + (set_attr "addr" "gpr16") (set_attr "mode" "TI")]) ;; XOP permute instructions @@ -26895,12 +26916,13 @@ [(set (match_operand:V16QI 0 "register_operand" "=x,x") (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "x,x") - (match_operand:V16QI 2 "nonimmediate_operand" "x,m") - (match_operand:V16QI 3 "nonimmediate_operand" "xm,x")] + (match_operand:V16QI 2 "nonimmediate_operand" "x,jm") + (match_operand:V16QI 3 "nonimmediate_operand" "xjm,x")] UNSPEC_XOP_PERMUTE))] "TARGET_XOP && !(MEM_P (operands[2]) && MEM_P (operands[3]))" "vpperm\t{%3, %2, %1, %0|%0, %1, %2, %3}" [(set_attr "type" "sse4arg") + (set_attr "addr" "gpr16") (set_attr "mode" "TI")]) ;; XOP pack instructions that combine two vectors into a smaller vector @@ -26910,11 +26932,12 @@ (truncate:V2SI (match_operand:V2DI 1 "register_operand" "x,x")) (truncate:V2SI - (match_operand:V2DI 2 "nonimmediate_operand" "x,m")))) - (use (match_operand:V16QI 3 "nonimmediate_operand" "xm,x"))] + (match_operand:V2DI 2 "nonimmediate_operand" "x,jm")))) + (use (match_operand:V16QI 3 "nonimmediate_operand" "xjm,x"))] "TARGET_XOP && !(MEM_P (operands[2]) && MEM_P (operands[3]))" "vpperm\t{%3, %2, %1, %0|%0, %1, %2, %3}" [(set_attr "type" "sse4arg") + (set_attr "addr" "gpr16") (set_attr "mode" "TI")]) (define_insn "xop_pperm_pack_v4si_v8hi" @@ -26923,11 +26946,12 @@ (truncate:V4HI (match_operand:V4SI 1 "register_operand" "x,x")) (truncate:V4HI - (match_operand:V4SI 2 "nonimmediate_operand" "x,m")))) - (use (match_operand:V16QI 3 "nonimmediate_operand" "xm,x"))] + (match_operand:V4SI 2 "nonimmediate_operand" "x,jm")))) + (use (match_operand:V16QI 3 "nonimmediate_operand" "xjm,x"))] "TARGET_XOP && !(MEM_P (operands[2]) && MEM_P (operands[3]))" "vpperm\t{%3, %2, %1, %0|%0, %1, %2, %3}" [(set_attr "type" "sse4arg") + (set_attr "addr" "gpr16") (set_attr "mode" "TI")]) (define_insn "xop_pperm_pack_v8hi_v16qi" @@ -26936,11 +26960,12 @@ (truncate:V8QI (match_operand:V8HI 1 "register_operand" "x,x")) (truncate:V8QI - (match_operand:V8HI 2 "nonimmediate_operand" "x,m")))) - (use (match_operand:V16QI 3 "nonimmediate_operand" "xm,x"))] + (match_operand:V8HI 2 "nonimmediate_operand" "x,jm")))) + (use (match_operand:V16QI 3 "nonimmediate_operand" "xjm,x"))] "TARGET_XOP && !(MEM_P (operands[2]) && MEM_P (operands[3]))" "vpperm\t{%3, %2, %1, %0|%0, %1, %2, %3}" [(set_attr "type" "sse4arg") + (set_attr "addr" "gpr16") (set_attr "mode" "TI")]) ;; XOP packed rotate instructions @@ -27011,7 +27036,7 @@ (define_insn "xop_rotl<mode>3" [(set (match_operand:VI_128 0 "register_operand" "=x") (rotate:VI_128 - (match_operand:VI_128 1 "nonimmediate_operand" "xm") + (match_operand:VI_128 1 "nonimmediate_operand" "xjm") (match_operand:SI 2 "const_0_to_<sserotatemax>_operand")))] "TARGET_XOP" "vprot<ssemodesuffix>\t{%2, %1, %0|%0, %1, %2}" @@ -27019,12 +27044,13 @@ (set_attr "prefix" "vex") (set_attr "prefix_extra" "1") (set_attr "length_immediate" "1") + (set_attr "addr" "gpr16") (set_attr "mode" "TI")]) (define_insn "xop_rotr<mode>3" [(set (match_operand:VI_128 0 "register_operand" "=x") (rotatert:VI_128 - (match_operand:VI_128 1 "nonimmediate_operand" "xm") + (match_operand:VI_128 1 "nonimmediate_operand" "xjm") (match_operand:SI 2 "const_0_to_<sserotatemax>_operand")))] "TARGET_XOP" { @@ -27036,6 +27062,7 @@ (set_attr "prefix" "vex") (set_attr "prefix_extra" "1") (set_attr "length_immediate" "1") + (set_attr "addr" "gpr16") (set_attr "mode" "TI")]) (define_expand "vrotr<mode>3" @@ -27064,10 +27091,10 @@ [(set (match_operand:VI_128 0 "register_operand" "=x,x") (if_then_else:VI_128 (ge:VI_128 - (match_operand:VI_128 2 "nonimmediate_operand" "x,m") + (match_operand:VI_128 2 "nonimmediate_operand" "x,jm") (const_int 0)) (rotate:VI_128 - (match_operand:VI_128 1 "nonimmediate_operand" "xm,x") + (match_operand:VI_128 1 "nonimmediate_operand" "xjm,x") (match_dup 2)) (rotatert:VI_128 (match_dup 1) @@ -27077,6 +27104,7 @@ [(set_attr "type" "sseishft") (set_attr "prefix" "vex") (set_attr "prefix_extra" "1") + (set_attr "addr" "gpr16") (set_attr "mode" "TI")]) ;; XOP packed shift instructions. @@ -27301,10 +27329,10 @@ [(set (match_operand:VI_128 0 "register_operand" "=x,x") (if_then_else:VI_128 (ge:VI_128 - (match_operand:VI_128 2 "nonimmediate_operand" "x,m") + (match_operand:VI_128 2 "nonimmediate_operand" "x,jm") (const_int 0)) (ashift:VI_128 - (match_operand:VI_128 1 "nonimmediate_operand" "xm,x") + (match_operand:VI_128 1 "nonimmediate_operand" "xjm,x") (match_dup 2)) (ashiftrt:VI_128 (match_dup 1) @@ -27314,16 +27342,17 @@ [(set_attr "type" "sseishft") (set_attr "prefix" "vex") (set_attr "prefix_extra" "1") + (set_attr "addr" "gpr16") (set_attr "mode" "TI")]) (define_insn "xop_shl<mode>3" [(set (match_operand:VI_128 0 "register_operand" "=x,x") (if_then_else:VI_128 (ge:VI_128 - (match_operand:VI_128 2 "nonimmediate_operand" "x,m") + (match_operand:VI_128 2 "nonimmediate_operand" "x,jm") (const_int 0)) (ashift:VI_128 - (match_operand:VI_128 1 "nonimmediate_operand" "xm,x") + (match_operand:VI_128 1 "nonimmediate_operand" "xjm,x") (match_dup 2)) (lshiftrt:VI_128 (match_dup 1) @@ -27333,6 +27362,7 @@ [(set_attr "type" "sseishft") (set_attr "prefix" "vex") (set_attr "prefix_extra" "1") + (set_attr "addr" "gpr16") (set_attr "mode" "TI")]) (define_expand "<insn><mode>3" @@ -27404,13 +27434,14 @@ (define_insn "xop_frcz<mode>2" [(set (match_operand:FMAMODE 0 "register_operand" "=x") (unspec:FMAMODE - [(match_operand:FMAMODE 1 "nonimmediate_operand" "xm")] + [(match_operand:FMAMODE 1 "nonimmediate_operand" "xjm")] UNSPEC_FRCZ))] "TARGET_XOP" "vfrcz<ssemodesuffix>\t{%1, %0|%0, %1}" [(set_attr "type" "ssecvt1") (set_attr "prefix" "vex") (set_attr "prefix_extra" "1") + (set_attr "addr" "gpr16") (set_attr "mode" "<MODE>")]) (define_expand "xop_vmfrcz<mode>2" @@ -27428,7 +27459,7 @@ [(set (match_operand:VF_128 0 "register_operand" "=x") (vec_merge:VF_128 (unspec:VF_128 - [(match_operand:VF_128 1 "nonimmediate_operand" "xm")] + [(match_operand:VF_128 1 "nonimmediate_operand" "xjm")] UNSPEC_FRCZ) (match_operand:VF_128 2 "const0_operand") (const_int 1)))] @@ -27437,26 +27468,29 @@ [(set_attr "type" "ssecvt1") (set_attr "prefix" "vex") (set_attr "prefix_extra" "1") + (set_attr "addr" "gpr16") (set_attr "mode" "<MODE>")]) (define_insn "xop_maskcmp<mode>3" [(set (match_operand:VI_128 0 "register_operand" "=x") (match_operator:VI_128 1 "ix86_comparison_int_operator" [(match_operand:VI_128 2 "register_operand" "x") - (match_operand:VI_128 3 "nonimmediate_operand" "xm")]))] + (match_operand:VI_128 3 "nonimmediate_operand" "xjm")]))] "TARGET_XOP" "vpcom%Y1<ssemodesuffix>\t{%3, %2, %0|%0, %2, %3}" [(set_attr "type" "sse4arg") + (set_attr "addr" "gpr16") (set_attr "mode" "TI")]) (define_insn "xop_maskcmp_uns<mode>3" [(set (match_operand:VI_128 0 "register_operand" "=x") (match_operator:VI_128 1 "ix86_comparison_uns_operator" [(match_operand:VI_128 2 "register_operand" "x") - (match_operand:VI_128 3 "nonimmediate_operand" "xm")]))] + (match_operand:VI_128 3 "nonimmediate_operand" "xjm")]))] "TARGET_XOP" "vpcom%Y1u<ssemodesuffix>\t{%3, %2, %0|%0, %2, %3}" [(set_attr "type" "sse4arg") + (set_attr "addr" "gpr16") (set_attr "mode" "TI")]) ;; Version of pcom*u* that is called from the intrinsics that allows pcomequ* @@ -27467,11 +27501,12 @@ (unspec:VI_128 [(match_operator:VI_128 1 "ix86_comparison_uns_operator" [(match_operand:VI_128 2 "register_operand" "x") - (match_operand:VI_128 3 "nonimmediate_operand" "xm")])] + (match_operand:VI_128 3 "nonimmediate_operand" "xjm")])] UNSPEC_XOP_UNSIGNED_CMP))] "TARGET_XOP" "vpcom%Y1u<ssemodesuffix>\t{%3, %2, %0|%0, %2, %3}" [(set_attr "type" "sse4arg") + (set_attr "addr" "gpr16") (set_attr "mode" "TI")]) ;; Pcomtrue and pcomfalse support. These are useless instructions, but are @@ -27480,7 +27515,7 @@ [(set (match_operand:VI_128 0 "register_operand" "=x") (unspec:VI_128 [(match_operand:VI_128 1 "register_operand" "x") - (match_operand:VI_128 2 "nonimmediate_operand" "xm") + (match_operand:VI_128 2 "nonimmediate_operand" "xjm") (match_operand:SI 3 "const_int_operand")] UNSPEC_XOP_TRUEFALSE))] "TARGET_XOP" @@ -27490,19 +27525,21 @@ : "vpcomfalse<ssemodesuffix>\t{%2, %1, %0|%0, %1, %2}"); } [(set_attr "type" "sse4arg") + (set_attr "addr" "gpr16") (set_attr "mode" "TI")]) (define_insn "xop_vpermil2<mode>3" [(set (match_operand:VF_128_256 0 "register_operand" "=x,x") (unspec:VF_128_256 [(match_operand:VF_128_256 1 "register_operand" "x,x") - (match_operand:VF_128_256 2 "nonimmediate_operand" "x,m") - (match_operand:<sseintvecmode> 3 "nonimmediate_operand" "xm,x") + (match_operand:VF_128_256 2 "nonimmediate_operand" "x,jm") + (match_operand:<sseintvecmode> 3 "nonimmediate_operand" "xjm,x") (match_operand:SI 4 "const_0_to_3_operand")] UNSPEC_VPERMIL2))] "TARGET_XOP" "vpermil2<ssemodesuffix>\t{%4, %3, %2, %1, %0|%0, %1, %2, %3, %4}" [(set_attr "type" "sse4arg") + (set_attr "addr" "gpr16") (set_attr "mode" "<MODE>")]) ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; diff --git a/gcc/testsuite/gcc.target/i386/pr126787.c b/gcc/testsuite/gcc.target/i386/pr126787.c new file mode 100644 index 000000000000..a15928c139f7 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr126787.c @@ -0,0 +1,15 @@ +/* { dg-do assemble { target { apxf && { ! ia32 } } } } */ +/* { dg-options "-O2 -mapxf -mprefer-avx128 -funroll-loops --param max-unroll-times=4 -ffast-math -ftree-vectorize" } */ + +typedef float f4; +__attribute__((__target__("avx,fma4"))) +void smm_avx128_fma4(f4 * restrict c, const f4 * restrict a, + const f4 * restrict b, int m, int n, int k) +{ + for (int j = 0; j < n; j++) + for (int l = 0; l < k; l++) { + f4 bl = b[l + j*k]; + for (int i = 0; i < m; i++) + c[i + j*m] += a[i + l*m] * bl; + } +}