[gcc r17-3494] RISC-V: Add missing platform VLEN check for pr113429.c and pr114734.c

https://gcc.gnu.org/g:7112f88833018f2c5f1e07948c9c8fd4634363ed

commit r17-3494-g7112f88833018f2c5f1e07948c9c8fd4634363ed
Author: Kito Cheng <[email protected]>
Date:   Fri Aug 21 15:02:13 2026 +0800

    RISC-V: Add missing platform VLEN check for pr113429.c and pr114734.c
    
    Both tests run code built for -march=rv64gcv_zvl256b but only require
    riscv_v, so they fail on a platform with a smaller VLEN.  pr114734.c
    also passes -mrvv-vector-bits=zvl, which fixes the vector length at 256
    bits, so it needs exactly 256 rather than at least 256.
    
    gcc/testsuite/ChangeLog:
    
            * gcc.target/riscv/rvv/autovec/pr114734.c: Require rvv_zvl256b_ok.
            * gcc.target/riscv/rvv/vsetvl/pr113429.c: Require rvv_zvl_ge_256b_ok.

Diff:
---
 gcc/testsuite/gcc.target/riscv/rvv/autovec/pr114734.c | 1 +
 gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr113429.c  | 1 +
 2 files changed, 2 insertions(+)

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr114734.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr114734.c
index b605d992aa15..f7357f04730a 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr114734.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr114734.c
@@ -1,6 +1,7 @@
 /* { dg-do run } */
 /* { dg-require-effective-target riscv_v } */
 /* { dg-options { -march=rv64gcv_zvl256b -mabi=lp64d -fwhole-program -O3 -mrvv-vector-bits=zvl  } } */
+/* { dg-require-effective-target rvv_zvl256b_ok } */
 
 int f[18];
 int g[18];
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr113429.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr113429.c
index a7f5db616d8b..bc123bb9cef0 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr113429.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr113429.c
@@ -2,6 +2,7 @@
 /* { dg-options "-march=rv64gcv_zvl256b -mabi=lp64d -O3" } */
 /* { dg-require-effective-target rv64 } */
 /* { dg-require-effective-target riscv_v } */
+/* { dg-require-effective-target rvv_zvl_ge_256b_ok } */
 
 long a;
 int b, c, d, e, f, g;