[gcc r17-3541] [PATCH] RISC-V: Improve slliw shifted bitfield split constraints

https://gcc.gnu.org/g:b2a19796811717cc8639408b384501a4dc840dc1

commit r17-3541-gb2a19796811717cc8639408b384501a4dc840dc1
Author: Luke Zhuang <[email protected]>
Date:   Sat Aug 22 16:15:27 2026 -0600

    [PATCH] RISC-V: Improve slliw shifted bitfield split constraints
    
    Improve the constraints in the split pattern introduced by
    <046bc3484c9>:
    1. The split ought to only match bitfields starting at bit 0, as
       described in its commit message.
    2. Need to make sure the hi-32bits of operands[5] is completely
       equivalent to signed extened slliw result after removing the
       outer AND
    
    Though the issues theoretically exist, I cannot find a C-level
    counterexample to demonstrate the issue.  May add one if it's
    possible to make one in the future.
    
    gcc/ChangeLog:
    
            * config/riscv/riscv.md: Restrict slliw shifted bitfield split
            to extractions starting at bit 0, and require the outer mask to
            match slliw sign-extension.

Diff:
---
 gcc/config/riscv/riscv.md | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md
index b9014b28b611..a56d6cbc592f 100644
--- a/gcc/config/riscv/riscv.md
+++ b/gcc/config/riscv/riscv.md
@@ -5375,7 +5375,9 @@
 	 (match_operand:DI 5 "const_int_operand")))
    (clobber (match_operand:DI 6 "register_operand"))]
   "(TARGET_64BIT
+    && INTVAL (operands[3]) == 0
     && INTVAL (operands[2]) + INTVAL (operands[4]) == 32
+    && sext_hwi (INTVAL (operands[5]), 32) == INTVAL (operands[5])
     && SMALL_OPERAND (INTVAL (operands[5]) >> INTVAL (operands[4])))"
   [(set (match_dup 6) (and:DI (match_dup 1) (match_dup 5)))
    (set (match_dup 0) (sign_extend:DI (ashift:SI (match_dup 7) (match_dup 4))))]