[PATCH v3 0/1] AArch64: Relax regexps in tests to let them pass with -fweb

Hi gcc-patches mailing list,
Christopher Bazley via Sourceware Forge <[email protected]> has requested that the following forgejo pull request
be published on the mailing list.

Created on: 2026-07-30 16:16:38+00:00
Latest update: 2026-07-30 17:17:13+00:00
Changes: 3 changed files, 13 additions, 13 deletions
Head revision: chris.bazley/gcc ref relax-aarch64-tests commit 5157c9d5221c06796fe8213aa16c43dee5376bd9
Base revision: gcc/gcc ref trunk commit ece564fdaa15a0da008cedd881afcd3f0f4dbd5a r17-2824-gece564fdaa15a0
Merge base: ece564fdaa15a0da008cedd881afcd3f0f4dbd5a
Full diff url: https://forge.sourceware.org/gcc/gcc/pulls/209.diff
Discussion:  https://forge.sourceware.org/gcc/gcc/pulls/209
Requested Reviewers: pinskia

The -fweb option changes the way that GCC allocates
registers.  -fweb is not enabled by default, so we
have never previously noticed that some AArch64 tests
have unreasonably strict expectations about register
allocation.  This patch relaxes those expectations.

gcc/testsuite/ChangeLog:

        * gcc.target/aarch64/ffs.c: Relax test expectations.
        * gcc.target/aarch64/frecpe_1.c: As above.
        * gcc.target/aarch64/frecpe_2.c: As above.


Changed files:
- M: gcc/testsuite/gcc.target/aarch64/ffs.c
- M: gcc/testsuite/gcc.target/aarch64/frecpe_1.c
- M: gcc/testsuite/gcc.target/aarch64/frecpe_2.c


Christopher Bazley (1):
  AArch64: Relax regexps in tests to let them pass with -fweb

 gcc/testsuite/gcc.target/aarch64/ffs.c      | 20 ++++++++++----------
 gcc/testsuite/gcc.target/aarch64/frecpe_1.c |  2 +-
 gcc/testsuite/gcc.target/aarch64/frecpe_2.c |  4 ++--
 3 files changed, 13 insertions(+), 13 deletions(-)

Range-diff against v2:
1:  bec1ae564653 ! 1:  5157c9d5221c AArch64: Relax regexps in tests to let them pass with -fweb
    @@ gcc/testsuite/gcc.target/aarch64/frecpe_1.c: f2 (double x)
     +/* { dg-final { scan-assembler {\tfrecpe\t(d[0-9]+), d0\n\tfrecps\t(d[0-9]+), \1, d0\n\tfmul\t(d[0-9]+), \1, \2\n\tfrecps\t(d[0-9]+), \1, d0\n\tfmul\td0, \3, \4\n} } } */
     
      ## gcc/testsuite/gcc.target/aarch64/frecpe_2.c ##
    +@@ gcc/testsuite/gcc.target/aarch64/frecpe_2.c: f1 (float x, float y)
    +   return y / x;
    + }
    + 
    +-/* { dg-final { scan-assembler {\tfrecpe\t(s[0-9]+), s0\n\tfrecps\t(s[0-9]+), \1, s0\n\tfmul\t\1, \1, s1\n\tfmul\ts0, \1, \2\n} } } */
    ++/* { dg-final { scan-assembler {\tfrecpe\t(s[0-9]+), s0\n\tfrecps\t(s[0-9]+), \1, s0\n\tfmul\t(s[0-9]+), \1, s1\n\tfmul\ts0, \3, \2\n} } } */
    + 
    + double
    + f2 (double x, double y)
     @@ gcc/testsuite/gcc.target/aarch64/frecpe_2.c: f2 (double x, double y)
        return y / x;
      }
      
     -/* { dg-final { scan-assembler {\tfrecpe\t(d[0-9]+), d0\n\tfrecps\t(d[0-9]+), \1, d0\n\tfmul\t\1, \1, \2\n\tfrecps\t\2, \1, d0\n\tfmul\t\1, \1, d1\n\tfmul\td0, \1, \2\n} } } */
    -+/* { dg-final { scan-assembler {\tfrecpe\t(d[0-9]+), d0\n\tfrecps\t(d[0-9]+), \1, d0\n\tfmul\t\1, \1, \2\n\tfrecps\t(d[0-9]+), \1, d0\n\tfmul\t\1, \1, d1\n\tfmul\td0, \1, \3\n} } } */
    ++/* { dg-final { scan-assembler {\tfrecpe\t(d[0-9]+), d0\n\tfrecps\t(d[0-9]+), \1, d0\n\tfmul\t(d[0-9]+), \1, \2\n\tfrecps\t(d[0-9]+), \3, d0\n\tfmul\t(d[0-9]+), \3, d1\n\tfmul\td0, \5, \4\n} } } */
-- 
2.54.0