[PATCH v3 7/7] [X86]: Add Sub-byte element extration and Symmetric-signed saturation narrow support.
Dipesh Sharma <[email protected]>
| Newsgroups | gmane.comp.gcc.patches |
|---|---|
| Message-ID | <[email protected]> |
Resolved comments from Haochen Jiang. gcc/ChangeLog: * config/i386/avx10v2auxintrin.h (_mm_cvtss_epi32_epi8): New intrin. (_mm_mask_cvtss_epi32_epi8): Ditto. (_mm_maskz_cvtss_epi32_epi8): Ditto. (_mm_mask_cvtss_epi32_storeu_epi8): Ditto. (_mm256_cvtss_epi32_epi8): Ditto. (_mm256_mask_cvtss_epi32_epi8): Ditto. (_mm256_maskz_cvtss_epi32_epi8): Ditto. (_mm256_mask_cvtss_epi32_storeu_epi8): Ditto. (_mm512_cvtss_epi32_epi8): Ditto. (_mm512_mask_cvtss_epi32_epi8): Ditto. (_mm512_maskz_cvtss_epi32_epi8): Ditto. (_mm512_mask_cvtss_epi32_storeu_epi8): Ditto. (_mm_unpack_epi8): Ditto. (_mm_mask_unpack_epi8): Ditto. (_mm_maskz_unpack_epi8): Ditto. (_mm256_unpack_epi8): Ditto. (_mm256_mask_unpack_epi8): Ditto. (_mm256_maskz_unpack_epi8): Ditto. (_mm512_unpack_epi8): Ditto. (_mm512_mask_unpack_epi8): Ditto. (_mm512_maskz_unpack_epi8): Ditto. * config/i386/i386-builtin-types.def: New function types. * config/i386/i386-builtin.def (BDESC): New builtins. * config/i386/i386-expand.cc (ix86_expand_args_builtin): Handle new builtin and reserved immediate check. * config/i386/sse.md (vunpackb<mode><mask_name>): New. (avx10v2aux_sym_truncatev4siv4qi2): Ditto. (*avx10v2aux_sym_truncatev4siv4qi2): Ditto. (avx10v2aux_sym_truncatev8siv8qi2): Ditto. (*avx10v2aux_sym_truncatev8siv8qi2): Ditto. (avx10v2aux_sym_truncatev4siv4qi2_mask): Ditto. (*avx10v2aux_sym_truncatev4siv4qi2_mask): Ditto. (avx10v2aux_sym_truncatev8siv8qi2_mask): Ditto. (*avx10v2aux_sym_truncatev8siv8qi2_mask): Ditto. (*avx10v2aux_sym_truncatev16siv16qi2): Ditto. (avx10v2aux_sym_truncatev16siv16qi2_mask): Ditto. (avx10v2aux_sym_truncatev16siv16qi2_mask_store): Ditto. (*avx10v2aux_sym_truncate<mode>v<ssescalarnum>qi2_store_1): Ditto. (*avx10v2aux_sym_truncate<mode>v<ssescalarnum>qi2_store_2): Ditto. (avx10v2aux_sym_truncate<mode>v<ssescalarnum>qi2_mask_store_1): Ditto. (avx10v2aux_sym_truncate<mode>v<ssescalarnum>qi2_mask_store_2): Ditto. gcc/testsuite/ChangeLog: * lib/target-supports.exp: Add more checks for avx10v2aux. * gcc.target/i386/avx10v2aux-convert-1i.c: New test. * gcc.target/i386/avx10v2aux-convert-1j.c: New test. * gcc.target/i386/avx10v2aux-convert-1k.c: New test. * gcc.target/i386/avx10v2aux-convert-1l.c: New test. Co-authored-by: Venkataramanan Kumar <[email protected]> Co-authored-by: Haochen Jiang <[email protected]> --- gcc/config/i386/avx10v2auxintrin.h | 287 ++++++++++++++++++ gcc/config/i386/i386-builtin-types.def | 3 + gcc/config/i386/i386-builtin.def | 13 + gcc/config/i386/i386-expand.cc | 26 ++ gcc/config/i386/sse.md | 231 ++++++++++++++ .../gcc.target/i386/avx10v2aux-convert-1i.c | 36 +++ .../gcc.target/i386/avx10v2aux-convert-1j.c | 43 +++ .../gcc.target/i386/avx10v2aux-convert-1k.c | 29 ++ .../gcc.target/i386/avx10v2aux-convert-1l.c | 27 ++ gcc/testsuite/lib/target-supports.exp | 3 + 10 files changed, 698 insertions(+) create mode 100644 gcc/testsuite/gcc.target/i386/avx10v2aux-convert-1i.c create mode 100644 gcc/testsuite/gcc.target/i386/avx10v2aux-convert-1j.c create mode 100644 gcc/testsuite/gcc.target/i386/avx10v2aux-convert-1k.c create mode 100644 gcc/testsuite/gcc.target/i386/avx10v2aux-convert-1l.c diff --git a/gcc/config/i386/avx10v2auxintrin.h b/gcc/config/i386/avx10v2auxintrin.h index bab9cb1475b..f15343f2389 100644 --- a/gcc/config/i386/avx10v2auxintrin.h +++ b/gcc/config/i386/avx10v2auxintrin.h @@ -1566,6 +1566,293 @@ _mm512_maskz_cvthf6_hf8 (__mmask64 __U, __m512i __A) (__mmask64) __U); } +// VPMOVSSDB - 128-bit + +extern __inline __m128i +__attribute__ ((__gnu_inline__, __always_inline__, __artificial__)) +_mm_cvtss_epi32_epi8 (__m128i __A) +{ + return (__m128i) __builtin_ia32_vpmovssdb128_mask ((__v4si) __A, + (__v16qi) + _mm_undefined_si128 (), + (__mmask8) -1); +} + +extern __inline __m128i +__attribute__ ((__gnu_inline__, __always_inline__, __artificial__)) +_mm_mask_cvtss_epi32_epi8 (__m128i __W, __mmask8 __U, __m128i __A) +{ + return (__m128i) __builtin_ia32_vpmovssdb128_mask ((__v4si) __A, + (__v16qi) __W, + (__mmask8) __U); +} + +extern __inline __m128i +__attribute__ ((__gnu_inline__, __always_inline__, __artificial__)) +_mm_maskz_cvtss_epi32_epi8 (__mmask8 __U, __m128i __A) +{ + return (__m128i) __builtin_ia32_vpmovssdb128_mask ((__v4si) __A, + (__v16qi) + _mm_setzero_si128 (), + (__mmask8) __U); +} + +extern __inline void +__attribute__ ((__gnu_inline__, __always_inline__, __artificial__)) +_mm_mask_cvtss_epi32_storeu_epi8 (void * __P, __mmask8 __U, __m128i __A) +{ + __builtin_ia32_vpmovssdb128mem_mask ((unsigned int *) __P, + (__v4si) __A, + (__mmask8) __U); +} + +// VPMOVSSDB - 256-bit + +extern __inline __m128i +__attribute__ ((__gnu_inline__, __always_inline__, __artificial__)) +_mm256_cvtss_epi32_epi8 (__m256i __A) +{ + return (__m128i) __builtin_ia32_vpmovssdb256_mask ((__v8si) __A, + (__v16qi) + _mm_undefined_si128 (), + (__mmask8) -1); +} + +extern __inline __m128i +__attribute__ ((__gnu_inline__, __always_inline__, __artificial__)) +_mm256_mask_cvtss_epi32_epi8 (__m128i __W, __mmask8 __U, __m256i __A) +{ + return (__m128i) __builtin_ia32_vpmovssdb256_mask ((__v8si) __A, + (__v16qi) __W, + (__mmask8) __U); +} + +extern __inline __m128i +__attribute__ ((__gnu_inline__, __always_inline__, __artificial__)) +_mm256_maskz_cvtss_epi32_epi8 (__mmask8 __U, __m256i __A) +{ + return (__m128i) __builtin_ia32_vpmovssdb256_mask ((__v8si) __A, + (__v16qi) + _mm_setzero_si128 (), + (__mmask8) __U); +} + +extern __inline void +__attribute__ ((__gnu_inline__, __always_inline__, __artificial__)) +_mm256_mask_cvtss_epi32_storeu_epi8 (void * __P, __mmask8 __U, __m256i __A) +{ + __builtin_ia32_vpmovssdb256mem_mask ((unsigned long long *) __P, + (__v8si) __A, + (__mmask8) __U); +} + +// VPMOVSSDB - 512-bit + +extern __inline __m128i +__attribute__ ((__gnu_inline__, __always_inline__, __artificial__)) +_mm512_cvtss_epi32_epi8 (__m512i __A) +{ + return (__m128i) __builtin_ia32_vpmovssdb512_mask ((__v16si) __A, + (__v16qi) + _mm_undefined_si128 (), + (__mmask16) -1); +} + +extern __inline __m128i +__attribute__ ((__gnu_inline__, __always_inline__, __artificial__)) +_mm512_mask_cvtss_epi32_epi8 (__m128i __W, __mmask16 __U, __m512i __A) +{ + return (__m128i) __builtin_ia32_vpmovssdb512_mask ((__v16si) __A, + (__v16qi) __W, + (__mmask16) __U); +} + +extern __inline __m128i +__attribute__ ((__gnu_inline__, __always_inline__, __artificial__)) +_mm512_maskz_cvtss_epi32_epi8 (__mmask16 __U, __m512i __A) +{ + return (__m128i) __builtin_ia32_vpmovssdb512_mask ((__v16si) __A, + (__v16qi) + _mm_setzero_si128 (), + (__mmask16) __U); +} + +extern __inline void +__attribute__ ((__gnu_inline__, __always_inline__, __artificial__)) +_mm512_mask_cvtss_epi32_storeu_epi8 (void * __P, __mmask16 __U, __m512i __A) +{ + __builtin_ia32_vpmovssdb512mem_mask ((__v16qi *) __P, + (__v16si) __A, + (__mmask16) __U); +} + +// VUNPACKB - 128-bit +#ifdef __OPTIMIZE__ +extern __inline __m128i +__attribute__ ((__gnu_inline__, __always_inline__, __artificial__)) +_mm_unpack_epi8 (__m128i __A, const int __B) +{ + return (__m128i) __builtin_ia32_vunpackb128_mask ((__v16qi) __A, + (const int) __B, + (__v16qi) + _mm_undefined_si128 (), + (__mmask16) -1); +} + +extern __inline __m128i +__attribute__ ((__gnu_inline__, __always_inline__, __artificial__)) +_mm_mask_unpack_epi8 (__m128i __W, __mmask16 __U, + __m128i __A, const int __B) +{ + return (__m128i) __builtin_ia32_vunpackb128_mask ((__v16qi) __A, + (const int) __B, + (__v16qi) __W, + (__mmask16) __U); +} + +extern __inline __m128i +__attribute__ ((__gnu_inline__, __always_inline__, __artificial__)) +_mm_maskz_unpack_epi8 (__mmask16 __U, __m128i __A, const int __B) +{ + return (__m128i) __builtin_ia32_vunpackb128_mask ((__v16qi) __A, + (const int) __B, + (__v16qi) + _mm_setzero_si128 (), + (__mmask16) __U); +} + +// VUNPACKB - 256-bit + +extern __inline __m256i +__attribute__ ((__gnu_inline__, __always_inline__, __artificial__)) +_mm256_unpack_epi8 (__m256i __A, const int __B) +{ + return (__m256i) __builtin_ia32_vunpackb256_mask ((__v32qi) __A, + (const int) __B, + (__v32qi) + _mm256_undefined_si256 (), + (__mmask32) -1); +} + +extern __inline __m256i +__attribute__ ((__gnu_inline__, __always_inline__, __artificial__)) +_mm256_mask_unpack_epi8 (__m256i __W, __mmask32 __U, + __m256i __A, const int __B) +{ + return (__m256i) __builtin_ia32_vunpackb256_mask ((__v32qi) __A, + (const int) __B, + (__v32qi) __W, + (__mmask32) __U); +} + +extern __inline __m256i +__attribute__ ((__gnu_inline__, __always_inline__, __artificial__)) +_mm256_maskz_unpack_epi8 (__mmask32 __U, __m256i __A, const int __B) +{ + return (__m256i) __builtin_ia32_vunpackb256_mask ((__v32qi) __A, + (const int) __B, + (__v32qi) + _mm256_setzero_si256 (), + (__mmask32) __U); +} + +// VUNPACKB - 512-bit + +extern __inline __m512i +__attribute__ ((__gnu_inline__, __always_inline__, __artificial__)) +_mm512_unpack_epi8 (__m512i __A, const int __B) +{ + return (__m512i) __builtin_ia32_vunpackb512_mask ((__v64qi) __A, + (const int) __B, + (__v64qi) + _mm512_undefined_si512 (), + (__mmask64) -1); +} + +extern __inline __m512i +__attribute__ ((__gnu_inline__, __always_inline__, __artificial__)) +_mm512_mask_unpack_epi8 (__m512i __W, __mmask64 __U, __m512i __A, + const int __B) +{ + return (__m512i) __builtin_ia32_vunpackb512_mask ((__v64qi) __A, + (const int) __B, + (__v64qi) __W, + (__mmask64) __U); +} + +extern __inline __m512i +__attribute__ ((__gnu_inline__, __always_inline__, __artificial__)) +_mm512_maskz_unpack_epi8 (__mmask64 __U, __m512i __A, const int __B) +{ + return (__m512i) __builtin_ia32_vunpackb512_mask ((__v64qi) __A, + (const int) __B, + (__v64qi) + _mm512_setzero_si512 (), + (__mmask64) __U); +} + +#else +#define _mm_unpack_epi8(A, imm) \ + ((__m128i) __builtin_ia32_vunpackb128_mask ((__v16qi)(__m128i)(A), \ + (int)(imm), \ + (__v16qi)(__m128i) \ + (_mm_undefined_si128 ()), \ + (__mmask16)(-1))) + +#define _mm_mask_unpack_epi8(W, U, A, imm) \ + ((__m128i) __builtin_ia32_vunpackb128_mask ((__v16qi)(__m128i)(A), \ + (int)(imm), \ + (__v16qi)(__m128i)(W), \ + (__mmask16)(U))) + +#define _mm_maskz_unpack_epi8(U, A, imm) \ + ((__m128i) __builtin_ia32_vunpackb128_mask ((__v16qi)(__m128i)(A), \ + (int)(imm), \ + (__v16qi)(__m128i) \ + (_mm_undefined_si128 ()), \ + (__mmask16)(U))) + +#define _mm256_unpack_epi8(A, imm) \ + ((__m256i) __builtin_ia32_vunpackb256_mask ((__v32qi)(__m256i)(A), \ + (int)(imm), \ + (__v32qi)(__m256i) \ + (_mm256_undefined_si256 ()), \ + (__mmask32)(-1))) + +#define _mm256_mask_unpack_epi8(W, U, A, imm) \ + ((__m256i) __builtin_ia32_vunpackb256_mask ((__v32qi)(__m256i)(A), \ + (int)(imm), \ + (__v32qi)(__m256i)(W), \ + (__mmask32)(U))) + +#define _mm256_maskz_unpack_epi8(U, A, imm) \ + ((__m256i) __builtin_ia32_vunpackb256_mask ((__v32qi)(__m256i)(A), \ + (int)(imm), \ + (__v32qi)(__m256i) \ + (_mm256_undefined_si256 ()), \ + (__mmask32)(U))) + +#define _mm512_unpack_epi8(A, imm) \ + ((__m512i) __builtin_ia32_vunpackb512_mask ((__v64qi)(__m512i)(A), \ + (int)(imm), \ + (__v64qi)(__m512i) \ + (_mm512_undefined_si512 ()), \ + (__mmask64)(-1))) + +#define _mm512_mask_unpack_epi8(W, U, A, imm) \ + ((__m512i) __builtin_ia32_vunpackb512_mask ((__v64qi)(__m512i)(A), \ + (int)(imm), \ + (__v64qi)(__m512i)(W), \ + (__mmask64)(U))) + +#define _mm512_maskz_unpack_epi8(U, A, imm) \ + ((__m512i) __builtin_ia32_vunpackb512_mask ((__v64qi)(__m512i)(A), \ + (int)(imm), \ + (__v64qi)(__m512i) \ + (_mm512_undefined_si512 ()), \ + (__mmask64)(U))) +#endif + #ifdef __DISABLE_AVX10V2AUX__ #undef __DISABLE_AVX10V2AUX__ #pragma GCC pop_options diff --git a/gcc/config/i386/i386-builtin-types.def b/gcc/config/i386/i386-builtin-types.def index ade9b3a67e2..4083453ce3e 100644 --- a/gcc/config/i386/i386-builtin-types.def +++ b/gcc/config/i386/i386-builtin-types.def @@ -1487,6 +1487,9 @@ DEF_FUNCTION_TYPE (V16SF, V16QI, V16SF, UHI) DEF_FUNCTION_TYPE (V16QI, V32QI) DEF_FUNCTION_TYPE (V32QI, V64QI) DEF_FUNCTION_TYPE (V64QI, V32QI, V64QI, UDI) +DEF_FUNCTION_TYPE (V16QI, V16QI, INT, V16QI, UHI) +DEF_FUNCTION_TYPE (V32QI, V32QI, INT, V32QI, USI) +DEF_FUNCTION_TYPE (V64QI, V64QI, INT, V64QI, UDI) # SM4 builtins diff --git a/gcc/config/i386/i386-builtin.def b/gcc/config/i386/i386-builtin.def index ad963e9011b..84f23239326 100644 --- a/gcc/config/i386/i386-builtin.def +++ b/gcc/config/i386/i386-builtin.def @@ -523,6 +523,12 @@ BDESC (OPTION_MASK_ISA_64BIT, OPTION_MASK_ISA2_MOVRS | OPTION_MASK_ISA2_AVX10_2, BDESC (OPTION_MASK_ISA_64BIT, OPTION_MASK_ISA2_MOVRS | OPTION_MASK_ISA2_AVX10_2, CODE_FOR_avx10_2_vmovrsqv2di_mask, "__builtin_ia32_vmovrsq128_mask", IX86_BUILTIN_VMOVRSQ_128, UNKNOWN, (int) V2DI_FTYPE_PCV2DI_V2DI_UQI) BDESC (OPTION_MASK_ISA_64BIT, OPTION_MASK_ISA2_MOVRS | OPTION_MASK_ISA2_AVX10_2, CODE_FOR_avx10_2_vmovrswv8hi_mask, "__builtin_ia32_vmovrsw128_mask", IX86_BUILTIN_VMOVRSW_128, UNKNOWN, (int) V8HI_FTYPE_PCV8HI_V8HI_UQI) +/* AVX10V2AUX. */ +BDESC (0, OPTION_MASK_ISA2_AVX10V2AUX, CODE_FOR_avx10v2aux_sym_truncatev4siv4qi2_mask_store_2, "__builtin_ia32_vpmovssdb128mem_mask", IX86_BUILTIN_VPMOVSSDB128_MEM, UNKNOWN, (int) VOID_FTYPE_PUSI_V4SI_UQI) +BDESC (0, OPTION_MASK_ISA2_AVX10V2AUX, CODE_FOR_avx10v2aux_sym_truncatev8siv8qi2_mask_store_2, "__builtin_ia32_vpmovssdb256mem_mask", IX86_BUILTIN_VPMOVSSDB256_MEM, UNKNOWN, (int) VOID_FTYPE_PUDI_V8SI_UQI) +BDESC (0, OPTION_MASK_ISA2_AVX10V2AUX, CODE_FOR_avx10v2aux_sym_truncatev16siv16qi2_mask_store, "__builtin_ia32_vpmovssdb512mem_mask", IX86_BUILTIN_VPMOVSSDB512_MEM, UNKNOWN, (int) VOID_FTYPE_PV16QI_V16SI_UHI) + + BDESC_END (SPECIAL_ARGS, PURE_ARGS) /* AVX */ @@ -3427,6 +3433,13 @@ BDESC (0, OPTION_MASK_ISA2_AVX10V2AUX, CODE_FOR_vcvtbf62hf8v64qi_mask, "__builti BDESC (0, OPTION_MASK_ISA2_AVX10V2AUX, CODE_FOR_vcvthf62hf8v16qi_mask, "__builtin_ia32_vcvthf62hf8128_mask", IX86_BUILTIN_VCVTHF62HF8128_MASK, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_UHI) BDESC (0, OPTION_MASK_ISA2_AVX10V2AUX, CODE_FOR_vcvthf62hf8v32qi_mask, "__builtin_ia32_vcvthf62hf8256_mask", IX86_BUILTIN_VCVTHF62HF8256_MASK, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_USI) BDESC (0, OPTION_MASK_ISA2_AVX10V2AUX, CODE_FOR_vcvthf62hf8v64qi_mask, "__builtin_ia32_vcvthf62hf8512_mask", IX86_BUILTIN_VCVTHF62HF8512_MASK, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI_UDI) +BDESC (0, OPTION_MASK_ISA2_AVX10V2AUX, CODE_FOR_vunpackbv16qi_mask, "__builtin_ia32_vunpackb128_mask", IX86_BUILTIN_VUNPACKB128_MASK, UNKNOWN, (int) V16QI_FTYPE_V16QI_INT_V16QI_UHI) +BDESC (0, OPTION_MASK_ISA2_AVX10V2AUX, CODE_FOR_vunpackbv32qi_mask, "__builtin_ia32_vunpackb256_mask", IX86_BUILTIN_VUNPACKB256_MASK, UNKNOWN, (int) V32QI_FTYPE_V32QI_INT_V32QI_USI) +BDESC (0, OPTION_MASK_ISA2_AVX10V2AUX, CODE_FOR_vunpackbv64qi_mask, "__builtin_ia32_vunpackb512_mask", IX86_BUILTIN_VUNPACKB512_MASK, UNKNOWN, (int) V64QI_FTYPE_V64QI_INT_V64QI_UDI) +BDESC (0, OPTION_MASK_ISA2_AVX10V2AUX, CODE_FOR_avx10v2aux_sym_truncatev4siv4qi2_mask, "__builtin_ia32_vpmovssdb128_mask", IX86_BUILTIN_VPMOVSSDB128_MASK, UNKNOWN, (int) V16QI_FTYPE_V4SI_V16QI_UQI) +BDESC (0, OPTION_MASK_ISA2_AVX10V2AUX, CODE_FOR_avx10v2aux_sym_truncatev8siv8qi2_mask, "__builtin_ia32_vpmovssdb256_mask", IX86_BUILTIN_VPMOVSSDB256_MASK, UNKNOWN, (int) V16QI_FTYPE_V8SI_V16QI_UQI) +BDESC (0, OPTION_MASK_ISA2_AVX10V2AUX, CODE_FOR_avx10v2aux_sym_truncatev16siv16qi2_mask, "__builtin_ia32_vpmovssdb512_mask", IX86_BUILTIN_VPMOVSSDB512_MASK, UNKNOWN, (int) V16QI_FTYPE_V16SI_V16QI_UHI) + /* Builtins with rounding support. */ BDESC_END (ARGS, ROUND_ARGS) diff --git a/gcc/config/i386/i386-expand.cc b/gcc/config/i386/i386-expand.cc index b82a4913b4e..98aab429062 100644 --- a/gcc/config/i386/i386-expand.cc +++ b/gcc/config/i386/i386-expand.cc @@ -13321,6 +13321,9 @@ ix86_expand_args_builtin (const struct builtin_description *d, case V4DF_FTYPE_V8DF_INT_V4DF_UQI: case V4SF_FTYPE_V16SF_INT_V4SF_UQI: case V8DI_FTYPE_V8DI_INT_V8DI_UQI: + case V16QI_FTYPE_V16QI_INT_V16QI_UHI: + case V32QI_FTYPE_V32QI_INT_V32QI_USI: + case V64QI_FTYPE_V64QI_INT_V64QI_UDI: nargs = 4; mask_pos = 2; nargs_constant = 1; @@ -13452,6 +13455,29 @@ ix86_expand_args_builtin (const struct builtin_description *d, else if ((mask_pos && (nargs - i - mask_pos) == nargs_constant) || (!mask_pos && (nargs - i) <= nargs_constant)) { + switch (icode) + { + case CODE_FOR_vunpackbv16qi_mask: + case CODE_FOR_vunpackbv32qi_mask: + case CODE_FOR_vunpackbv64qi_mask: + if (CONST_INT_P (op)) + { + char val = INTVAL (op); + if ((val & 0xc0) + || (!(val & 0x18)) + || ((val & 0x02) && ((val & 0x1c) != 0x08)) + || ((val & 0x01) && (((val & 0x1c) >> 2) > 0x4))) + { + error ("the last argument must not use reserved value " + "immediate"); + return const0_rtx; + } + } + break; + default: + break; + } + if (!match) switch (icode) { diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md index 1625b8b18ca..cf07d7d2d37 100644 --- a/gcc/config/i386/sse.md +++ b/gcc/config/i386/sse.md @@ -279,6 +279,8 @@ UNSPEC_VCVTHF82HF6S UNSPEC_VCVTBF62HF8 UNSPEC_VCVTHF62HF8 + UNSPEC_VUNPACKB + UNSPEC_VPMOVSSDB ]) (define_c_enum "unspecv" [ @@ -34642,3 +34644,232 @@ "vcvt<convertfp62hf8>\t{%1, %0<mask_operand2>|%0<mask_operand2>, %1}" [(set_attr "prefix" "evex") (set_attr "mode" "<sseinsnmode>")]) + +;; VUNPACKB - Sub-byte element extraction + +(define_insn "vunpackb<mode><mask_name>" + [(set (match_operand:VI1_AVX512VL 0 "register_operand" "=v") + (unspec:VI1_AVX512VL + [(match_operand:VI1_AVX512VL 1 "nonimmediate_operand" "vm") + (match_operand:QI 2 "const_0_to_63_operand")] + UNSPEC_VUNPACKB))] + "TARGET_AVX10V2AUX" + "vunpackb\t{%2, %1, %0<mask_operand3>|%0<mask_operand3>, %1, %2}" + [(set_attr "prefix" "evex") + (set_attr "mode" "<sseinsnmode>")]) + +;; VPMOVSSDB - Symmetric signed saturation narrow (32-bit to 8-bit) + +(define_mode_attr pmovss_mem_dest + [(V4SI "SI") (V8SI "DI")]) + +(define_expand "avx10v2aux_sym_truncatev4siv4qi2" + [(set (match_operand:V16QI 0 "nonimmediate_operand") + (vec_concat:V16QI + (unspec:V4QI + [(match_operand:V4SI 1 "register_operand")] + UNSPEC_VPMOVSSDB) + (match_dup 2)))] + "TARGET_AVX10V2AUX" + "operands[2] = CONST0_RTX (V12QImode);") + +(define_insn "*avx10v2aux_sym_truncatev4siv4qi2" + [(set (match_operand:V16QI 0 "register_operand" "=v") + (vec_concat:V16QI + (unspec:V4QI + [(match_operand:V4SI 1 "register_operand" "v")] + UNSPEC_VPMOVSSDB) + (match_operand:V12QI 2 "const0_operand")))] + "TARGET_AVX10V2AUX" + "vpmovssdb\t{%1, %0|%0, %1}" + [(set_attr "type" "ssemov") + (set_attr "prefix" "evex") + (set_attr "mode" "TI")]) + +(define_expand "avx10v2aux_sym_truncatev8siv8qi2" + [(set (match_operand:V16QI 0 "nonimmediate_operand") + (vec_concat:V16QI + (unspec:V8QI + [(match_operand:V8SI 1 "register_operand")] + UNSPEC_VPMOVSSDB) + (match_dup 2)))] + "TARGET_AVX10V2AUX" + "operands[2] = CONST0_RTX (V8QImode);") + +(define_insn "*avx10v2aux_sym_truncatev8siv8qi2" + [(set (match_operand:V16QI 0 "register_operand" "=v") + (vec_concat:V16QI + (unspec:V8QI + [(match_operand:V8SI 1 "register_operand" "v")] + UNSPEC_VPMOVSSDB) + (match_operand:V8QI 2 "const0_operand")))] + "TARGET_AVX10V2AUX" + "vpmovssdb\t{%1, %0|%0, %1}" + [(set_attr "type" "ssemov") + (set_attr "prefix" "evex") + (set_attr "mode" "OI")]) + +(define_expand "avx10v2aux_sym_truncatev4siv4qi2_mask" + [(set (match_operand:V16QI 0 "nonimmediate_operand") + (vec_concat:V16QI + (vec_merge:V4QI + (unspec:V4QI + [(match_operand:V4SI 1 "register_operand")] + UNSPEC_VPMOVSSDB) + (vec_select:V4QI + (match_operand:V16QI 2 "nonimm_or_0_operand") + (parallel [(const_int 0) (const_int 1) + (const_int 2) (const_int 3)])) + (match_operand:QI 3 "register_operand")) + (match_dup 4)))] + "TARGET_AVX10V2AUX" + "operands[4] = CONST0_RTX (V12QImode);") + +(define_insn "*avx10v2aux_sym_truncatev4siv4qi2_mask" + [(set (match_operand:V16QI 0 "register_operand" "=v") + (vec_concat:V16QI + (vec_merge:V4QI + (unspec:V4QI + [(match_operand:V4SI 1 "register_operand" "v")] + UNSPEC_VPMOVSSDB) + (vec_select:V4QI + (match_operand:V16QI 2 "nonimm_or_0_operand" "0C") + (parallel [(const_int 0) (const_int 1) + (const_int 2) (const_int 3)])) + (match_operand:QI 3 "register_operand" "Yk")) + (match_operand:V12QI 4 "const0_operand")))] + "TARGET_AVX10V2AUX" + "vpmovssdb\t{%1, %0%{%3%}%N2|%0%{%3%}%N2, %1}" + [(set_attr "type" "ssemov") + (set_attr "prefix" "evex") + (set_attr "mode" "TI")]) + +(define_expand "avx10v2aux_sym_truncatev8siv8qi2_mask" + [(set (match_operand:V16QI 0 "nonimmediate_operand") + (vec_concat:V16QI + (vec_merge:V8QI + (unspec:V8QI + [(match_operand:V8SI 1 "register_operand")] + UNSPEC_VPMOVSSDB) + (vec_select:V8QI + (match_operand:V16QI 2 "nonimm_or_0_operand") + (parallel [(const_int 0) (const_int 1) + (const_int 2) (const_int 3) + (const_int 4) (const_int 5) + (const_int 6) (const_int 7)])) + (match_operand:QI 3 "register_operand")) + (match_dup 4)))] + "TARGET_AVX10V2AUX" + "operands[4] = CONST0_RTX (V8QImode);") + +(define_insn "*avx10v2aux_sym_truncatev8siv8qi2_mask" + [(set (match_operand:V16QI 0 "register_operand" "=v") + (vec_concat:V16QI + (vec_merge:V8QI + (unspec:V8QI + [(match_operand:V8SI 1 "register_operand" "v")] + UNSPEC_VPMOVSSDB) + (vec_select:V8QI + (match_operand:V16QI 2 "nonimm_or_0_operand" "0C") + (parallel [(const_int 0) (const_int 1) + (const_int 2) (const_int 3) + (const_int 4) (const_int 5) + (const_int 6) (const_int 7)])) + (match_operand:QI 3 "register_operand" "Yk")) + (match_operand:V8QI 4 "const0_operand")))] + "TARGET_AVX10V2AUX" + "vpmovssdb\t{%1, %0%{%3%}%N2|%0%{%3%}%N2, %1}" + [(set_attr "type" "ssemov") + (set_attr "prefix" "evex") + (set_attr "mode" "OI")]) + +(define_insn "*avx10v2aux_sym_truncatev16siv16qi2" + [(set (match_operand:V16QI 0 "nonimmediate_operand" "=v,m") + (unspec:V16QI + [(match_operand:V16SI 1 "register_operand" "v,v")] + UNSPEC_VPMOVSSDB))] + "TARGET_AVX10V2AUX" + "vpmovssdb\t{%1, %0|%0, %1}" + [(set_attr "type" "ssemov") + (set_attr "memory" "none,store") + (set_attr "prefix" "evex") + (set_attr "mode" "XI")]) + +(define_insn "avx10v2aux_sym_truncatev16siv16qi2_mask" + [(set (match_operand:V16QI 0 "nonimmediate_operand" "=v,m") + (vec_merge:V16QI + (unspec:V16QI + [(match_operand:V16SI 1 "register_operand" "v,v")] + UNSPEC_VPMOVSSDB) + (match_operand:V16QI 2 "nonimm_or_0_operand" "0C,0") + (match_operand:HI 3 "register_operand" "Yk,Yk")))] + "TARGET_AVX10V2AUX" + "vpmovssdb\t{%1, %0%{%3%}%N2|%0%{%3%}%N2, %1}" + [(set_attr "type" "ssemov") + (set_attr "memory" "none,store") + (set_attr "prefix" "evex") + (set_attr "mode" "XI")]) + +(define_expand "avx10v2aux_sym_truncatev16siv16qi2_mask_store" + [(set (match_operand:V16QI 0 "memory_operand") + (vec_merge:V16QI + (unspec:V16QI + [(match_operand:V16SI 1 "register_operand")] + UNSPEC_VPMOVSSDB) + (match_dup 0) + (match_operand:HI 2 "register_operand")))] + "TARGET_AVX10V2AUX") + +(define_insn "*avx10v2aux_sym_truncate<mode>v<ssescalarnum>qi2_store_1" + [(set (match_operand:<pmov_dst_3> 0 "memory_operand" "=m") + (unspec:<pmov_dst_3> + [(match_operand:VI4_AVX2 1 "register_operand" "v")] + UNSPEC_VPMOVSSDB))] + "TARGET_AVX10V2AUX" + "vpmovssdb\t{%1, %0|%0, %1}" + [(set_attr "type" "ssemov") + (set_attr "memory" "store") + (set_attr "prefix" "evex") + (set_attr "mode" "<sseinsnmode>")]) + +(define_insn_and_split "*avx10v2aux_sym_truncate<mode>v<ssescalarnum>qi2_store_2" + [(set (match_operand:<pmovss_mem_dest> 0 "memory_operand") + (subreg:<pmovss_mem_dest> + (unspec:<pmov_dst_3> + [(match_operand:VI4_AVX2 1 "register_operand")] + UNSPEC_VPMOVSSDB) 0))] + "TARGET_AVX10V2AUX && ix86_pre_reload_split ()" + "#" + "&& 1" + [(set (match_dup 0) + (unspec:<pmov_dst_3> [(match_dup 1)] UNSPEC_VPMOVSSDB))] + "operands[0] = adjust_address_nv (operands[0], <pmov_dst_3>mode, 0);") + +(define_insn "avx10v2aux_sym_truncate<mode>v<ssescalarnum>qi2_mask_store_1" + [(set (match_operand:<pmov_dst_3> 0 "memory_operand" "=m") + (vec_merge:<pmov_dst_3> + (unspec:<pmov_dst_3> + [(match_operand:VI4_AVX2 1 "register_operand" "v")] + UNSPEC_VPMOVSSDB) + (match_dup 0) + (match_operand:<avx512fmaskmode> 2 "register_operand" "Yk")))] + "TARGET_AVX10V2AUX" + "vpmovssdb\t{%1, %0%{%2%}|%0%{%2%}, %1}" + [(set_attr "type" "ssemov") + (set_attr "memory" "store") + (set_attr "prefix" "evex") + (set_attr "mode" "<sseinsnmode>")]) + +(define_expand "avx10v2aux_sym_truncate<mode>v<ssescalarnum>qi2_mask_store_2" + [(match_operand:<pmov_dst_3> 0 "memory_operand") + (unspec:<pmov_dst_3> + [(match_operand:VI4_AVX2 1 "register_operand")] + UNSPEC_VPMOVSSDB) + (match_operand:<avx512fmaskmode> 2 "register_operand")] + "TARGET_AVX10V2AUX" +{ + operands[0] = adjust_address_nv (operands[0], <pmov_dst_3>mode, 0); + emit_insn (gen_avx10v2aux_sym_truncate<mode>v<ssescalarnum>qi2_mask_store_1 + (operands[0], operands[1], operands[2])); + DONE; +}) diff --git a/gcc/testsuite/gcc.target/i386/avx10v2aux-convert-1i.c b/gcc/testsuite/gcc.target/i386/avx10v2aux-convert-1i.c new file mode 100644 index 00000000000..9fe7a163dda --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx10v2aux-convert-1i.c @@ -0,0 +1,36 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx10v2aux -O2 -fno-fuse-ops-with-volatile-access" } */ +/* { dg-final { scan-assembler-times "vunpackb\[ \\t\]+\[^\{\n\]*%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vunpackb\[ \\t\]+\[^\{\n\]*%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+\{%k\[1-7\]\}(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vunpackb\[ \\t\]+\[^\{\n\]*%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+\{%k\[1-7\]\}\{z\}(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vunpackb\[ \\t\]+\[^\{\n\]*%ymm\[0-9\]+\[^\n\r]*%ymm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vunpackb\[ \\t\]+\[^\{\n\]*%ymm\[0-9\]+\[^\n\r]*%ymm\[0-9\]+\{%k\[1-7\]\}(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vunpackb\[ \\t\]+\[^\{\n\]*%ymm\[0-9\]+\[^\n\r]*%ymm\[0-9\]+\{%k\[1-7\]\}\{z\}(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vunpackb\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vunpackb\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\{%k\[1-7\]\}(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vunpackb\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\{%k\[1-7\]\}\{z\}(?:\n|\[ \\t\]+#)" 1 } } */ + +#include <immintrin.h> + +volatile __m128i x128i; +volatile __m256i x256i; +volatile __m512i x512i; +volatile __mmask16 m16; +volatile __mmask32 m32; +volatile __mmask64 m64; + +void extern +avx10v2aux_vunpack_test (void) +{ + x128i = _mm_unpack_epi8 (x128i, 8); + x128i = _mm_mask_unpack_epi8 (x128i, m16, x128i, 8); + x128i = _mm_maskz_unpack_epi8 (m16, x128i, 8); + + x256i = _mm256_unpack_epi8 (x256i, 16); + x256i = _mm256_mask_unpack_epi8 (x256i, m32, x256i, 16); + x256i = _mm256_maskz_unpack_epi8 (m32, x256i, 16); + + x512i = _mm512_unpack_epi8 (x512i, 16); + x512i = _mm512_mask_unpack_epi8 (x512i, m64, x512i, 16); + x512i = _mm512_maskz_unpack_epi8 (m64, x512i, 16); +} diff --git a/gcc/testsuite/gcc.target/i386/avx10v2aux-convert-1j.c b/gcc/testsuite/gcc.target/i386/avx10v2aux-convert-1j.c new file mode 100644 index 00000000000..630968a7803 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx10v2aux-convert-1j.c @@ -0,0 +1,43 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx10v2aux -O2 -fno-fuse-ops-with-volatile-access" } */ +/* { dg-final { scan-assembler-times "vpmovssdb\[ \\t\]+\[^\{\n\]*%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vpmovssdb\[ \\t\]+\[^\{\n\]*%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+\{%k\[1-7\]\}(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vpmovssdb\[ \\t\]+\[^\{\n\]*%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+\{%k\[1-7\]\}\{z\}(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vpmovssdb\[ \\t\]+\[^\{\n\]*%ymm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vpmovssdb\[ \\t\]+\[^\{\n\]*%ymm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+\{%k\[1-7\]\}(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vpmovssdb\[ \\t\]+\[^\{\n\]*%ymm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+\{%k\[1-7\]\}\{z\}(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vpmovssdb\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vpmovssdb\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+\{%k\[1-7\]\}(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vpmovssdb\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+\{%k\[1-7\]\}\{z\}(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vpmovssdb\[ \\t\]+%xmm\[0-9\]+, \\(\[^\{\n\]*\\)\{%k\[1-7\]\}(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vpmovssdb\[ \\t\]+%ymm\[0-9\]+, \\(\[^\{\n\]*\\)\{%k\[1-7\]\}(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vpmovssdb\[ \\t\]+%zmm\[0-9\]+, \\(\[^\{\n\]*\\)\{%k\[1-7\]\}(?:\n|\[ \\t\]+#)" 1 } } */ + +#include <immintrin.h> + +volatile __m128i x128i; +volatile __m256i x256i; +volatile __m512i x512i; +volatile __m128i res128i; +volatile __mmask8 m8; +volatile __mmask16 m16; +char *p; + +void extern +avx10v2aux_vpmovssdb_test (void) +{ + res128i = _mm_cvtss_epi32_epi8 (x128i); + res128i = _mm_mask_cvtss_epi32_epi8 (res128i, m8, x128i); + res128i = _mm_maskz_cvtss_epi32_epi8 (m8, x128i); + _mm_mask_cvtss_epi32_storeu_epi8 ((void *) p, m8, x128i); + + res128i = _mm256_cvtss_epi32_epi8 (x256i); + res128i = _mm256_mask_cvtss_epi32_epi8 (res128i, m8, x256i); + res128i = _mm256_maskz_cvtss_epi32_epi8 (m8, x256i); + _mm256_mask_cvtss_epi32_storeu_epi8 ((void *) p, m8, x256i); + + res128i = _mm512_cvtss_epi32_epi8 (x512i); + res128i = _mm512_mask_cvtss_epi32_epi8 (res128i, m16, x512i); + res128i = _mm512_maskz_cvtss_epi32_epi8 (m16, x512i); + _mm512_mask_cvtss_epi32_storeu_epi8 ((void *) p, m16, x512i); +} diff --git a/gcc/testsuite/gcc.target/i386/avx10v2aux-convert-1k.c b/gcc/testsuite/gcc.target/i386/avx10v2aux-convert-1k.c new file mode 100644 index 00000000000..a38cafe4980 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx10v2aux-convert-1k.c @@ -0,0 +1,29 @@ +/* Exercise the non-__OPTIMIZE__ (macro) path of the vunpackb intrinsics. */ +/* { dg-do compile } */ +/* { dg-options "-mavx10v2aux -O0" } */ +/* { dg-final { scan-assembler-times "vunpackb\[ \\t\]" 9 } } */ + +#include <immintrin.h> + +volatile __m128i x128i; +volatile __m256i x256i; +volatile __m512i x512i; +volatile __mmask16 m16; +volatile __mmask32 m32; +volatile __mmask64 m64; + +void extern +avx10v2aux_vunpack_noopt_test (void) +{ + x128i = _mm_unpack_epi8 (x128i, 8); + x128i = _mm_mask_unpack_epi8 (x128i, m16, x128i, 8); + x128i = _mm_maskz_unpack_epi8 (m16, x128i, 8); + + x256i = _mm256_unpack_epi8 (x256i, 16); + x256i = _mm256_mask_unpack_epi8 (x256i, m32, x256i, 16); + x256i = _mm256_maskz_unpack_epi8 (m32, x256i, 16); + + x512i = _mm512_unpack_epi8 (x512i, 16); + x512i = _mm512_mask_unpack_epi8 (x512i, m64, x512i, 16); + x512i = _mm512_maskz_unpack_epi8 (m64, x512i, 16); +} diff --git a/gcc/testsuite/gcc.target/i386/avx10v2aux-convert-1l.c b/gcc/testsuite/gcc.target/i386/avx10v2aux-convert-1l.c new file mode 100644 index 00000000000..3a734acc594 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx10v2aux-convert-1l.c @@ -0,0 +1,27 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx10v2aux -O0" } */ + +#include <immintrin.h> + +volatile __m128i x128i; +volatile __m256i x256i; +volatile __m512i x512i; +volatile __mmask16 m16; +volatile __mmask32 m32; +volatile __mmask64 m64; + +void extern +avx10v2aux_vunpack_imm_range_test (void) +{ + x128i = _mm_unpack_epi8 (x128i, 70); /* { dg-error "the last argument must not use reserved value immediate" } */ + x128i = _mm_mask_unpack_epi8 (x128i, m16, x128i, 64); /* { dg-error "the last argument must not use reserved value immediate" } */ + x128i = _mm_maskz_unpack_epi8 (m16, x128i, 0); /* { dg-error "the last argument must not use reserved value immediate" } */ + + x256i = _mm256_unpack_epi8 (x256i, 70); /* { dg-error "the last argument must not use reserved value immediate" } */ + x256i = _mm256_mask_unpack_epi8 (x256i, m32, x256i, 64); /* { dg-error "the last argument must not use reserved value immediate" } */ + x256i = _mm256_maskz_unpack_epi8 (m32, x256i, 64); /* { dg-error "the last argument must not use reserved value immediate" } */ + + x512i = _mm512_unpack_epi8 (x512i, 70); /* { dg-error "the last argument must not use reserved value immediate" } */ + x512i = _mm512_mask_unpack_epi8 (x512i, m64, x512i, 64); /* { dg-error "the last argument must not use reserved value immediate" } */ + x512i = _mm512_maskz_unpack_epi8 (m64, x512i, 64); /* { dg-error "the last argument must not use reserved value immediate" } */ +} diff --git a/gcc/testsuite/lib/target-supports.exp b/gcc/testsuite/lib/target-supports.exp index 07ba9c62efa..c5823a03cb5 100644 --- a/gcc/testsuite/lib/target-supports.exp +++ b/gcc/testsuite/lib/target-supports.exp @@ -11606,6 +11606,9 @@ proc check_effective_target_avx10v2aux { } { foo () { __asm__ volatile ("vcvtps2bf8\t{%%xmm1, %%xmm0|%%xmm0, %%xmm1}"); + __asm__ volatile ("vcvtbf82ps\t{%%xmm1, %%xmm0|%%xmm0, %%xmm1}"); + __asm__ volatile ("vunpackb\t$1, %%ymm1, %%ymm0"); + __asm__ volatile ("vpmovssdb\t{%%zmm1, %%xmm0|%%xmm0, %%zmm1}"); } } "-mavx10v2aux" ] } -- 2.34.1