[PATCH v1 0/5] Add test cases for v[sub|mul][u].vv register overlap

From: Pan Li <[email protected]>

The widen_op of register overlap is allowed in previous, add more test
case to make sure it works well as expected.

The below test suites are passed for this patch:
1. The rv64gcv fully regression tests.

Pan Li (5):
  RISC-V: Add test cases for vwsub.vv reg overlap
  RISC-V: Add test cases for vwsubu.vv reg overlap
  RISC-V: Add test cases for vwmul.vv reg overlap
  RISC-V: Add test cases for vwmulu.vv reg overlap
  RISC-V: Add more test cases for vwsub/vwsubu/vwmul/vwmulu.vv

 .../autovec/group_overlap/vwmul_vv-i16-m1.c   | 17 ++++++
 .../autovec/group_overlap/vwmul_vv-i16-m2.c   | 17 ++++++
 .../autovec/group_overlap/vwmul_vv-i16-m4.c   | 17 ++++++
 .../autovec/group_overlap/vwmul_vv-i16-mf2.c  | 19 ++++++
 .../autovec/group_overlap/vwmul_vv-i16-mf4.c  | 19 ++++++
 .../autovec/group_overlap/vwmul_vv-i32-m1.c   | 17 ++++++
 .../autovec/group_overlap/vwmul_vv-i32-m2.c   | 17 ++++++
 .../autovec/group_overlap/vwmul_vv-i32-m4.c   | 17 ++++++
 .../autovec/group_overlap/vwmul_vv-i32-mf2.c  | 19 ++++++
 .../autovec/group_overlap/vwmul_vv-i8-m1.c    | 17 ++++++
 .../autovec/group_overlap/vwmul_vv-i8-m2.c    | 17 ++++++
 .../autovec/group_overlap/vwmul_vv-i8-m4.c    | 17 ++++++
 .../autovec/group_overlap/vwmul_vv-i8-mf2.c   | 19 ++++++
 .../autovec/group_overlap/vwmul_vv-i8-mf4.c   | 19 ++++++
 .../autovec/group_overlap/vwmul_vv-i8-mf8.c   | 19 ++++++
 .../autovec/group_overlap/vwmulu_vv-u16-m1.c  | 17 ++++++
 .../autovec/group_overlap/vwmulu_vv-u16-m2.c  | 17 ++++++
 .../autovec/group_overlap/vwmulu_vv-u16-m4.c  | 17 ++++++
 .../autovec/group_overlap/vwmulu_vv-u16-mf2.c | 19 ++++++
 .../autovec/group_overlap/vwmulu_vv-u16-mf4.c | 19 ++++++
 .../autovec/group_overlap/vwmulu_vv-u32-m1.c  | 17 ++++++
 .../autovec/group_overlap/vwmulu_vv-u32-m2.c  | 17 ++++++
 .../autovec/group_overlap/vwmulu_vv-u32-m4.c  | 17 ++++++
 .../autovec/group_overlap/vwmulu_vv-u32-mf2.c | 19 ++++++
 .../autovec/group_overlap/vwmulu_vv-u8-m1.c   | 17 ++++++
 .../autovec/group_overlap/vwmulu_vv-u8-m2.c   | 17 ++++++
 .../autovec/group_overlap/vwmulu_vv-u8-m4.c   | 17 ++++++
 .../autovec/group_overlap/vwmulu_vv-u8-mf2.c  | 19 ++++++
 .../autovec/group_overlap/vwmulu_vv-u8-mf4.c  | 19 ++++++
 .../autovec/group_overlap/vwmulu_vv-u8-mf8.c  | 19 ++++++
 .../autovec/group_overlap/vwsub_vv-i16-m1.c   | 17 ++++++
 .../autovec/group_overlap/vwsub_vv-i16-m2.c   | 17 ++++++
 .../autovec/group_overlap/vwsub_vv-i16-m4.c   | 17 ++++++
 .../autovec/group_overlap/vwsub_vv-i16-mf2.c  | 19 ++++++
 .../autovec/group_overlap/vwsub_vv-i16-mf4.c  | 19 ++++++
 .../autovec/group_overlap/vwsub_vv-i32-m1.c   | 17 ++++++
 .../autovec/group_overlap/vwsub_vv-i32-m2.c   | 17 ++++++
 .../autovec/group_overlap/vwsub_vv-i32-m4.c   | 17 ++++++
 .../autovec/group_overlap/vwsub_vv-i32-mf2.c  | 19 ++++++
 .../autovec/group_overlap/vwsub_vv-i8-m1.c    | 17 ++++++
 .../autovec/group_overlap/vwsub_vv-i8-m2.c    | 17 ++++++
 .../autovec/group_overlap/vwsub_vv-i8-m4.c    | 17 ++++++
 .../autovec/group_overlap/vwsub_vv-i8-mf2.c   | 19 ++++++
 .../autovec/group_overlap/vwsub_vv-i8-mf4.c   | 19 ++++++
 .../autovec/group_overlap/vwsub_vv-i8-mf8.c   | 19 ++++++
 .../autovec/group_overlap/vwsubu_vv-u16-m1.c  | 17 ++++++
 .../autovec/group_overlap/vwsubu_vv-u16-m2.c  | 17 ++++++
 .../autovec/group_overlap/vwsubu_vv-u16-m4.c  | 17 ++++++
 .../autovec/group_overlap/vwsubu_vv-u16-mf2.c | 19 ++++++
 .../autovec/group_overlap/vwsubu_vv-u16-mf4.c | 19 ++++++
 .../autovec/group_overlap/vwsubu_vv-u32-m1.c  | 17 ++++++
 .../autovec/group_overlap/vwsubu_vv-u32-m2.c  | 17 ++++++
 .../autovec/group_overlap/vwsubu_vv-u32-m4.c  | 17 ++++++
 .../autovec/group_overlap/vwsubu_vv-u32-mf2.c | 19 ++++++
 .../autovec/group_overlap/vwsubu_vv-u8-m1.c   | 17 ++++++
 .../autovec/group_overlap/vwsubu_vv-u8-m2.c   | 17 ++++++
 .../autovec/group_overlap/vwsubu_vv-u8-m4.c   | 17 ++++++
 .../autovec/group_overlap/vwsubu_vv-u8-mf2.c  | 19 ++++++
 .../autovec/group_overlap/vwsubu_vv-u8-mf4.c  | 19 ++++++
 .../autovec/group_overlap/vwsubu_vv-u8-mf8.c  | 19 ++++++
 .../gcc.target/riscv/rvv/base/pr112431-44.c   | 56 ++++++++++++++++++
 .../gcc.target/riscv/rvv/base/pr112431-45.c   | 56 ++++++++++++++++++
 .../gcc.target/riscv/rvv/base/pr112431-46.c   | 59 +++++++++++++++++++
 .../gcc.target/riscv/rvv/base/pr112431-47.c   | 59 +++++++++++++++++++
 64 files changed, 1298 insertions(+)
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmul_vv-i16-m1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmul_vv-i16-m2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmul_vv-i16-m4.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmul_vv-i16-mf2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmul_vv-i16-mf4.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmul_vv-i32-m1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmul_vv-i32-m2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmul_vv-i32-m4.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmul_vv-i32-mf2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmul_vv-i8-m1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmul_vv-i8-m2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmul_vv-i8-m4.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmul_vv-i8-mf2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmul_vv-i8-mf4.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmul_vv-i8-mf8.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmulu_vv-u16-m1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmulu_vv-u16-m2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmulu_vv-u16-m4.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmulu_vv-u16-mf2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmulu_vv-u16-mf4.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmulu_vv-u32-m1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmulu_vv-u32-m2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmulu_vv-u32-m4.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmulu_vv-u32-mf2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmulu_vv-u8-m1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmulu_vv-u8-m2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmulu_vv-u8-m4.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmulu_vv-u8-mf2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmulu_vv-u8-mf4.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmulu_vv-u8-mf8.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwsub_vv-i16-m1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwsub_vv-i16-m2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwsub_vv-i16-m4.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwsub_vv-i16-mf2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwsub_vv-i16-mf4.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwsub_vv-i32-m1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwsub_vv-i32-m2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwsub_vv-i32-m4.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwsub_vv-i32-mf2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwsub_vv-i8-m1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwsub_vv-i8-m2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwsub_vv-i8-m4.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwsub_vv-i8-mf2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwsub_vv-i8-mf4.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwsub_vv-i8-mf8.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwsubu_vv-u16-m1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwsubu_vv-u16-m2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwsubu_vv-u16-m4.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwsubu_vv-u16-mf2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwsubu_vv-u16-mf4.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwsubu_vv-u32-m1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwsubu_vv-u32-m2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwsubu_vv-u32-m4.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwsubu_vv-u32-mf2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwsubu_vv-u8-m1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwsubu_vv-u8-m2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwsubu_vv-u8-m4.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwsubu_vv-u8-mf2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwsubu_vv-u8-mf4.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwsubu_vv-u8-mf8.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-44.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-45.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-46.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-47.c

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2.43.0