[PATCH v1 4/5] RISC-V: Add test cases for vwmulu.vv reg overlap

From: Pan Li <[email protected]>

Add test cases for register group overlap, please
note it is not overlap as much as possible.

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/rvv/autovec/group_overlap/vwmulu_vv-u16-m1.c: New test.
	* gcc.target/riscv/rvv/autovec/group_overlap/vwmulu_vv-u16-m2.c: New test.
	* gcc.target/riscv/rvv/autovec/group_overlap/vwmulu_vv-u16-m4.c: New test.
	* gcc.target/riscv/rvv/autovec/group_overlap/vwmulu_vv-u16-mf2.c: New test.
	* gcc.target/riscv/rvv/autovec/group_overlap/vwmulu_vv-u16-mf4.c: New test.
	* gcc.target/riscv/rvv/autovec/group_overlap/vwmulu_vv-u32-m1.c: New test.
	* gcc.target/riscv/rvv/autovec/group_overlap/vwmulu_vv-u32-m2.c: New test.
	* gcc.target/riscv/rvv/autovec/group_overlap/vwmulu_vv-u32-m4.c: New test.
	* gcc.target/riscv/rvv/autovec/group_overlap/vwmulu_vv-u32-mf2.c: New test.
	* gcc.target/riscv/rvv/autovec/group_overlap/vwmulu_vv-u8-m1.c: New test.
	* gcc.target/riscv/rvv/autovec/group_overlap/vwmulu_vv-u8-m2.c: New test.
	* gcc.target/riscv/rvv/autovec/group_overlap/vwmulu_vv-u8-m4.c: New test.
	* gcc.target/riscv/rvv/autovec/group_overlap/vwmulu_vv-u8-mf2.c: New test.
	* gcc.target/riscv/rvv/autovec/group_overlap/vwmulu_vv-u8-mf4.c: New test.
	* gcc.target/riscv/rvv/autovec/group_overlap/vwmulu_vv-u8-mf8.c: New test.

Signed-off-by: Pan Li <[email protected]>
Co-Authored-By: Claude Opus 5 (1M context) <[email protected]>
---
 .../autovec/group_overlap/vwmulu_vv-u16-m1.c  | 17 +++++++++++++++++
 .../autovec/group_overlap/vwmulu_vv-u16-m2.c  | 17 +++++++++++++++++
 .../autovec/group_overlap/vwmulu_vv-u16-m4.c  | 17 +++++++++++++++++
 .../autovec/group_overlap/vwmulu_vv-u16-mf2.c | 19 +++++++++++++++++++
 .../autovec/group_overlap/vwmulu_vv-u16-mf4.c | 19 +++++++++++++++++++
 .../autovec/group_overlap/vwmulu_vv-u32-m1.c  | 17 +++++++++++++++++
 .../autovec/group_overlap/vwmulu_vv-u32-m2.c  | 17 +++++++++++++++++
 .../autovec/group_overlap/vwmulu_vv-u32-m4.c  | 17 +++++++++++++++++
 .../autovec/group_overlap/vwmulu_vv-u32-mf2.c | 19 +++++++++++++++++++
 .../autovec/group_overlap/vwmulu_vv-u8-m1.c   | 17 +++++++++++++++++
 .../autovec/group_overlap/vwmulu_vv-u8-m2.c   | 17 +++++++++++++++++
 .../autovec/group_overlap/vwmulu_vv-u8-m4.c   | 17 +++++++++++++++++
 .../autovec/group_overlap/vwmulu_vv-u8-mf2.c  | 19 +++++++++++++++++++
 .../autovec/group_overlap/vwmulu_vv-u8-mf4.c  | 19 +++++++++++++++++++
 .../autovec/group_overlap/vwmulu_vv-u8-mf8.c  | 19 +++++++++++++++++++
 15 files changed, 267 insertions(+)
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmulu_vv-u16-m1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmulu_vv-u16-m2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmulu_vv-u16-m4.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmulu_vv-u16-mf2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmulu_vv-u16-mf4.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmulu_vv-u32-m1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmulu_vv-u32-m2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmulu_vv-u32-m4.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmulu_vv-u32-mf2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmulu_vv-u8-m1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmulu_vv-u8-m2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmulu_vv-u8-m4.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmulu_vv-u8-mf2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmulu_vv-u8-mf4.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmulu_vv-u8-mf8.c

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmulu_vv-u16-m1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmulu_vv-u16-m1.c
new file mode 100644
index 00000000000..0ec66f1eecd
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmulu_vv-u16-m1.c
@@ -0,0 +1,17 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d" } */
+
+#include "group_overlap.h"
+
+DEF_GROUP_OVERLAP_BINARY_1(
+  __riscv_vsetvlmax_e16m1,
+  vuint16m1_t,
+  vuint32m2_t,
+  __riscv_vle16_v_u16m1,
+  __riscv_vwmulu_vv_u32m2,
+  __riscv_vse32_v_u32m2,
+  vwmulu_vv,
+  LOOP_DUAL_WIDEN_BINARY_BODY_X16)
+
+/* { dg-final { scan-assembler-times {vwmulu\.vv\s+v2,v1,v3([^0-9]|$)} 1 } } */
+/* { dg-final { scan-assembler-times {vwmulu\.vv\s+v10,v11,v3([^0-9]|$)} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmulu_vv-u16-m2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmulu_vv-u16-m2.c
new file mode 100644
index 00000000000..ec2a0eafdc8
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmulu_vv-u16-m2.c
@@ -0,0 +1,17 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d" } */
+
+#include "group_overlap.h"
+
+DEF_GROUP_OVERLAP_BINARY_1(
+  __riscv_vsetvlmax_e16m2,
+  vuint16m2_t,
+  vuint32m4_t,
+  __riscv_vle16_v_u16m2,
+  __riscv_vwmulu_vv_u32m4,
+  __riscv_vse32_v_u32m4,
+  vwmulu_vv,
+  LOOP_DUAL_WIDEN_BINARY_BODY_X8)
+
+/* { dg-final { scan-assembler-times {vwmulu\.vv\s+v8,v10,v6([^0-9]|$)} 1 } } */
+/* { dg-final { scan-assembler-times {vwmulu\.vv\s+v28,v30,v24([^0-9]|$)} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmulu_vv-u16-m4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmulu_vv-u16-m4.c
new file mode 100644
index 00000000000..2ceeae060d5
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmulu_vv-u16-m4.c
@@ -0,0 +1,17 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d" } */
+
+#include "group_overlap.h"
+
+DEF_GROUP_OVERLAP_BINARY_1(
+  __riscv_vsetvlmax_e16m4,
+  vuint16m4_t,
+  vuint32m8_t,
+  __riscv_vle16_v_u16m4,
+  __riscv_vwmulu_vv_u32m8,
+  __riscv_vse32_v_u32m8,
+  vwmulu_vv,
+  LOOP_DUAL_WIDEN_BINARY_BODY_X4)
+
+/* { dg-final { scan-assembler-times {vwmulu\.vv\s+v8,v4,v12([^0-9]|$)} 1 } } */
+/* { dg-final { scan-assembler-times {vwmulu\.vv\s+v24,v28,v16([^0-9]|$)} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmulu_vv-u16-mf2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmulu_vv-u16-mf2.c
new file mode 100644
index 00000000000..de3e2af21f7
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmulu_vv-u16-mf2.c
@@ -0,0 +1,19 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d" } */
+
+#include "group_overlap.h"
+
+DEF_GROUP_OVERLAP_BINARY_1(
+  __riscv_vsetvlmax_e16m1,
+  vuint16mf2_t,
+  vuint32m1_t,
+  __riscv_vle16_v_u16mf2,
+  __riscv_vwmulu_vv_u32m1,
+  __riscv_vse32_v_u32m1,
+  vwmulu_vv,
+  LOOP_DUAL_WIDEN_BINARY_BODY_X16)
+
+/* The fractional LMUL source has EMUL < 1, thus the widened destination
+   register group must not overlap either source at all.  */
+/* { dg-final { scan-assembler-not {vwmulu\.vv\s+(v[0-9]+),\1,} } } */
+/* { dg-final { scan-assembler-not {vwmulu\.vv\s+(v[0-9]+),v[0-9]+,\1([^0-9]|$)} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmulu_vv-u16-mf4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmulu_vv-u16-mf4.c
new file mode 100644
index 00000000000..ff31f22c111
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmulu_vv-u16-mf4.c
@@ -0,0 +1,19 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d" } */
+
+#include "group_overlap.h"
+
+DEF_GROUP_OVERLAP_BINARY_1(
+  __riscv_vsetvlmax_e16m1,
+  vuint16mf4_t,
+  vuint32mf2_t,
+  __riscv_vle16_v_u16mf4,
+  __riscv_vwmulu_vv_u32mf2,
+  __riscv_vse32_v_u32mf2,
+  vwmulu_vv,
+  LOOP_DUAL_WIDEN_BINARY_BODY_X16)
+
+/* The fractional LMUL source has EMUL < 1, thus the widened destination
+   register group must not overlap either source at all.  */
+/* { dg-final { scan-assembler-not {vwmulu\.vv\s+(v[0-9]+),\1,} } } */
+/* { dg-final { scan-assembler-not {vwmulu\.vv\s+(v[0-9]+),v[0-9]+,\1([^0-9]|$)} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmulu_vv-u32-m1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmulu_vv-u32-m1.c
new file mode 100644
index 00000000000..7676b1eceb7
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmulu_vv-u32-m1.c
@@ -0,0 +1,17 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d" } */
+
+#include "group_overlap.h"
+
+DEF_GROUP_OVERLAP_BINARY_1(
+  __riscv_vsetvlmax_e32m1,
+  vuint32m1_t,
+  vuint64m2_t,
+  __riscv_vle32_v_u32m1,
+  __riscv_vwmulu_vv_u64m2,
+  __riscv_vse64_v_u64m2,
+  vwmulu_vv,
+  LOOP_DUAL_WIDEN_BINARY_BODY_X16)
+
+/* { dg-final { scan-assembler-times {vwmulu\.vv\s+v2,v1,v3([^0-9]|$)} 1 } } */
+/* { dg-final { scan-assembler-times {vwmulu\.vv\s+v10,v11,v3([^0-9]|$)} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmulu_vv-u32-m2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmulu_vv-u32-m2.c
new file mode 100644
index 00000000000..52d53a59cee
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmulu_vv-u32-m2.c
@@ -0,0 +1,17 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d" } */
+
+#include "group_overlap.h"
+
+DEF_GROUP_OVERLAP_BINARY_1(
+  __riscv_vsetvlmax_e32m2,
+  vuint32m2_t,
+  vuint64m4_t,
+  __riscv_vle32_v_u32m2,
+  __riscv_vwmulu_vv_u64m4,
+  __riscv_vse64_v_u64m4,
+  vwmulu_vv,
+  LOOP_DUAL_WIDEN_BINARY_BODY_X8)
+
+/* { dg-final { scan-assembler-times {vwmulu\.vv\s+v8,v10,v6([^0-9]|$)} 1 } } */
+/* { dg-final { scan-assembler-times {vwmulu\.vv\s+v28,v30,v24([^0-9]|$)} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmulu_vv-u32-m4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmulu_vv-u32-m4.c
new file mode 100644
index 00000000000..b74a421bf65
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmulu_vv-u32-m4.c
@@ -0,0 +1,17 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d" } */
+
+#include "group_overlap.h"
+
+DEF_GROUP_OVERLAP_BINARY_1(
+  __riscv_vsetvlmax_e32m4,
+  vuint32m4_t,
+  vuint64m8_t,
+  __riscv_vle32_v_u32m4,
+  __riscv_vwmulu_vv_u64m8,
+  __riscv_vse64_v_u64m8,
+  vwmulu_vv,
+  LOOP_DUAL_WIDEN_BINARY_BODY_X4)
+
+/* { dg-final { scan-assembler-times {vwmulu\.vv\s+v8,v4,v12([^0-9]|$)} 1 } } */
+/* { dg-final { scan-assembler-times {vwmulu\.vv\s+v24,v28,v16([^0-9]|$)} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmulu_vv-u32-mf2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmulu_vv-u32-mf2.c
new file mode 100644
index 00000000000..f8ce7fb01c2
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmulu_vv-u32-mf2.c
@@ -0,0 +1,19 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d" } */
+
+#include "group_overlap.h"
+
+DEF_GROUP_OVERLAP_BINARY_1(
+  __riscv_vsetvlmax_e32m1,
+  vuint32mf2_t,
+  vuint64m1_t,
+  __riscv_vle32_v_u32mf2,
+  __riscv_vwmulu_vv_u64m1,
+  __riscv_vse64_v_u64m1,
+  vwmulu_vv,
+  LOOP_DUAL_WIDEN_BINARY_BODY_X16)
+
+/* The fractional LMUL source has EMUL < 1, thus the widened destination
+   register group must not overlap either source at all.  */
+/* { dg-final { scan-assembler-not {vwmulu\.vv\s+(v[0-9]+),\1,} } } */
+/* { dg-final { scan-assembler-not {vwmulu\.vv\s+(v[0-9]+),v[0-9]+,\1([^0-9]|$)} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmulu_vv-u8-m1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmulu_vv-u8-m1.c
new file mode 100644
index 00000000000..73b5583397d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmulu_vv-u8-m1.c
@@ -0,0 +1,17 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d" } */
+
+#include "group_overlap.h"
+
+DEF_GROUP_OVERLAP_BINARY_1(
+  __riscv_vsetvlmax_e8m1,
+  vuint8m1_t,
+  vuint16m2_t,
+  __riscv_vle8_v_u8m1,
+  __riscv_vwmulu_vv_u16m2,
+  __riscv_vse16_v_u16m2,
+  vwmulu_vv,
+  LOOP_DUAL_WIDEN_BINARY_BODY_X16)
+
+/* { dg-final { scan-assembler-times {vwmulu\.vv\s+v2,v1,v3([^0-9]|$)} 1 } } */
+/* { dg-final { scan-assembler-times {vwmulu\.vv\s+v10,v11,v3([^0-9]|$)} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmulu_vv-u8-m2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmulu_vv-u8-m2.c
new file mode 100644
index 00000000000..518700d9b6f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmulu_vv-u8-m2.c
@@ -0,0 +1,17 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d" } */
+
+#include "group_overlap.h"
+
+DEF_GROUP_OVERLAP_BINARY_1(
+  __riscv_vsetvlmax_e8m2,
+  vuint8m2_t,
+  vuint16m4_t,
+  __riscv_vle8_v_u8m2,
+  __riscv_vwmulu_vv_u16m4,
+  __riscv_vse16_v_u16m4,
+  vwmulu_vv,
+  LOOP_DUAL_WIDEN_BINARY_BODY_X8)
+
+/* { dg-final { scan-assembler-times {vwmulu\.vv\s+v8,v10,v6([^0-9]|$)} 1 } } */
+/* { dg-final { scan-assembler-times {vwmulu\.vv\s+v28,v30,v24([^0-9]|$)} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmulu_vv-u8-m4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmulu_vv-u8-m4.c
new file mode 100644
index 00000000000..4105e4d2e19
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmulu_vv-u8-m4.c
@@ -0,0 +1,17 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d" } */
+
+#include "group_overlap.h"
+
+DEF_GROUP_OVERLAP_BINARY_1(
+  __riscv_vsetvlmax_e8m4,
+  vuint8m4_t,
+  vuint16m8_t,
+  __riscv_vle8_v_u8m4,
+  __riscv_vwmulu_vv_u16m8,
+  __riscv_vse16_v_u16m8,
+  vwmulu_vv,
+  LOOP_DUAL_WIDEN_BINARY_BODY_X4)
+
+/* { dg-final { scan-assembler-times {vwmulu\.vv\s+v8,v4,v12([^0-9]|$)} 1 } } */
+/* { dg-final { scan-assembler-times {vwmulu\.vv\s+v24,v28,v16([^0-9]|$)} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmulu_vv-u8-mf2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmulu_vv-u8-mf2.c
new file mode 100644
index 00000000000..0fdadb503ad
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmulu_vv-u8-mf2.c
@@ -0,0 +1,19 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d" } */
+
+#include "group_overlap.h"
+
+DEF_GROUP_OVERLAP_BINARY_1(
+  __riscv_vsetvlmax_e8m1,
+  vuint8mf2_t,
+  vuint16m1_t,
+  __riscv_vle8_v_u8mf2,
+  __riscv_vwmulu_vv_u16m1,
+  __riscv_vse16_v_u16m1,
+  vwmulu_vv,
+  LOOP_DUAL_WIDEN_BINARY_BODY_X16)
+
+/* The fractional LMUL source has EMUL < 1, thus the widened destination
+   register group must not overlap either source at all.  */
+/* { dg-final { scan-assembler-not {vwmulu\.vv\s+(v[0-9]+),\1,} } } */
+/* { dg-final { scan-assembler-not {vwmulu\.vv\s+(v[0-9]+),v[0-9]+,\1([^0-9]|$)} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmulu_vv-u8-mf4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmulu_vv-u8-mf4.c
new file mode 100644
index 00000000000..9df0d2b9874
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmulu_vv-u8-mf4.c
@@ -0,0 +1,19 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d" } */
+
+#include "group_overlap.h"
+
+DEF_GROUP_OVERLAP_BINARY_1(
+  __riscv_vsetvlmax_e8m1,
+  vuint8mf4_t,
+  vuint16mf2_t,
+  __riscv_vle8_v_u8mf4,
+  __riscv_vwmulu_vv_u16mf2,
+  __riscv_vse16_v_u16mf2,
+  vwmulu_vv,
+  LOOP_DUAL_WIDEN_BINARY_BODY_X16)
+
+/* The fractional LMUL source has EMUL < 1, thus the widened destination
+   register group must not overlap either source at all.  */
+/* { dg-final { scan-assembler-not {vwmulu\.vv\s+(v[0-9]+),\1,} } } */
+/* { dg-final { scan-assembler-not {vwmulu\.vv\s+(v[0-9]+),v[0-9]+,\1([^0-9]|$)} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmulu_vv-u8-mf8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmulu_vv-u8-mf8.c
new file mode 100644
index 00000000000..c45dc9e5987
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmulu_vv-u8-mf8.c
@@ -0,0 +1,19 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d" } */
+
+#include "group_overlap.h"
+
+DEF_GROUP_OVERLAP_BINARY_1(
+  __riscv_vsetvlmax_e8m1,
+  vuint8mf8_t,
+  vuint16mf4_t,
+  __riscv_vle8_v_u8mf8,
+  __riscv_vwmulu_vv_u16mf4,
+  __riscv_vse16_v_u16mf4,
+  vwmulu_vv,
+  LOOP_DUAL_WIDEN_BINARY_BODY_X16)
+
+/* The fractional LMUL source has EMUL < 1, thus the widened destination
+   register group must not overlap either source at all.  */
+/* { dg-final { scan-assembler-not {vwmulu\.vv\s+(v[0-9]+),\1,} } } */
+/* { dg-final { scan-assembler-not {vwmulu\.vv\s+(v[0-9]+),v[0-9]+,\1([^0-9]|$)} } } */
-- 
2.43.0