RE: [PATCH v3 7/7] [X86]: Add Sub-byte element extration and Symmetric-signed saturation narrow support.
"Jiang, Haochen" <[email protected]> Mon, 3 Aug 2026 08:41:53 +0000
| Newsgroups | gmane.comp.gcc.patches |
|---|---|
| Message-ID | <SJ5PPF77D28E3C260A3B38D48378BAB0BC8ECD52@SJ5PPF77D28E3C2.namprd11.prod.outlook.com> |
> From: Dipesh Sharma <[email protected]> > Sent: Friday, July 31, 2026 6:08 PM > diff --git a/gcc/config/i386/i386-expand.cc b/gcc/config/i386/i386-expand.cc > index b82a4913b4e..98aab429062 100644 > --- a/gcc/config/i386/i386-expand.cc > +++ b/gcc/config/i386/i386-expand.cc > @@ -13452,6 +13455,29 @@ ix86_expand_args_builtin (const struct > builtin_description *d, > else if ((mask_pos && (nargs - i - mask_pos) == nargs_constant) || > (!mask_pos && (nargs - i) <= nargs_constant)) > { > + switch (icode) An if putting after "if(!match)" is well enough. No need for a switch. But the current code is also ok. > + { > + case CODE_FOR_vunpackbv16qi_mask: > + case CODE_FOR_vunpackbv32qi_mask: > + case CODE_FOR_vunpackbv64qi_mask: > + if (CONST_INT_P (op)) > + { > + char val = INTVAL (op); > + if ((val & 0xc0) > + || (!(val & 0x18)) > + || ((val & 0x02) && ((val & 0x1c) != 0x08)) > + || ((val & 0x01) && (((val & 0x1c) >> 2) > 0x4))) > + { > + error ("the last argument must not use reserved value " > + "immediate"); > + return const0_rtx; > + } > + } > + break; > + default: > + break; > + } > + > if (!match) > switch (icode) > { > diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md > index 1625b8b18ca..cf07d7d2d37 100644 > --- a/gcc/config/i386/sse.md > +++ b/gcc/config/i386/sse.md > +(define_insn "*avx10v2aux_sym_truncatev4siv4qi2" > + [(set (match_operand:V16QI 0 "register_operand" "=v") Do you meet any issues for changing this and similar patterns to nonimmediate_operand? Thx, Haochen > + (vec_concat:V16QI > + (unspec:V4QI > + [(match_operand:V4SI 1 "register_operand" "v")] > + UNSPEC_VPMOVSSDB) > + (match_operand:V12QI 2 "const0_operand")))] > + "TARGET_AVX10V2AUX" > + "vpmovssdb\t{%1, %0|%0, %1}" > + [(set_attr "type" "ssemov") > + (set_attr "prefix" "evex") > + (set_attr "mode" "TI")])