[PATCH v4 1/2] arm: handle neon vec_dup from select of 128-bit vector
Richard Earnshaw via Sourceware Forge <[email protected]> Mon, 03 Aug 2026 13:59:42 +0000
| Newsgroups | gmane.comp.gcc.patches |
|---|---|
| Message-ID | <bmm.hl01du4maw.gcc.gcc.rearnsha.208.4.1@forge-stage.sourceware.org> |
From: Richard Earnshaw <[email protected]> The Neon instruction set lacks a direct vdup from a lane in a 128-bit vector; but one isn't needed because the lane is a constant and we can handle the appropriate half of a 128-bit register simply by selecting that during output. Additionally, we can also handle core registers as the source operand for both 64-bit and 128-bit sources without needing to copy the entire vector to VFP/SIMD regs; at most a simple shift is needed to extract the appropriate lane to the lower bits of a scratch core reg, but in some cases we can use the core reg directly (when no shift is needed) since the upper bits are ignored. I've also disambiguated the two paterns named neon_vdup_lane<mode>_internal by inserting the iterator name into the pattern. This doesn't change anything in terms of generated code, but makes the pattern names in the MD file unique. gcc/ChangeLog: * config/arm/neon.md (neon_vdup_lane<VDQW:mode>_internal): Handle core registers as the input vector operand by splitting. (neon_vdup_lane<VHFBF:mode>_internal): Likewise. (neon_vdupq_lane<VQ2BF:mode>_internal): New pattern. gcc/testsuite/ChangeLog: * gcc.target/arm/crypto-vsha1cq_u32.c: Don't expect a vmov.32 in the generated code. * gcc.target/arm/crypto-vsha1h_u32.c: Likewise. * gcc.target/arm/crypto-vsha1mq_u32.c: Likewise. * gcc.target/arm/crypto-vsha1pq_u32.c: Likewise. * gcc.target/arm/armv8_2-fp16-neon-1.c: Update expected output. * gcc.target/arm/armv8_2-fp16-neon-2.c: Likewise. --- gcc/config/arm/neon.md | 164 ++++++++++++++---- .../gcc.target/arm/armv8_2-fp16-neon-1.c | 114 +++++++++--- .../gcc.target/arm/armv8_2-fp16-neon-2.c | 90 +++++++++- .../gcc.target/arm/crypto-vsha1cq_u32.c | 1 - .../gcc.target/arm/crypto-vsha1h_u32.c | 1 - .../gcc.target/arm/crypto-vsha1mq_u32.c | 1 - .../gcc.target/arm/crypto-vsha1pq_u32.c | 1 - 7 files changed, 306 insertions(+), 66 deletions(-) diff --git a/gcc/config/arm/neon.md b/gcc/config/arm/neon.md index 603bdc1ab828f..4b5f023162b07 100644 --- a/gcc/config/arm/neon.md +++ b/gcc/config/arm/neon.md @@ -3526,48 +3526,138 @@ if (BYTES_BIG_ENDIAN) (set_attr "type" "multiple")] ) -(define_insn "neon_vdup_lane<mode>_internal" - [(set (match_operand:VDQW 0 "s_register_operand" "=w") - (vec_duplicate:VDQW - (vec_select:<V_elem> - (match_operand:<V_double_vector_mode> 1 "s_register_operand" "w") - (parallel [(match_operand:SI 2 "immediate_operand" "i")]))))] +(define_insn_and_split "neon_vdup_lane<VDQW:mode>_internal" + [(set (match_operand:VDQW 0 "s_register_operand" "=w,w") + (vec_duplicate:VDQW + (vec_select:<V_elem> + (match_operand:<V_double_vector_mode> 1 "s_register_operand" "w,r") + (parallel [(match_operand:SI 2 "immediate_operand" "i,i")])))) + (clobber (match_scratch:<V_elem> 3 "=X,r"))] "TARGET_NEON" -{ - if (BYTES_BIG_ENDIAN) - { - int elt = INTVAL (operands[2]); + { + if (REGNO (operands[1]) <= LAST_ARM_REGNUM) + return "#"; + if (BYTES_BIG_ENDIAN) + { + int elt = INTVAL (operands[2]); + elt = GET_MODE_NUNITS (<V_double_vector_mode>mode) - 1 - elt; + operands[2] = GEN_INT (elt); + } + if (<Is_d_reg>) + return "vdup.<V_sz_elem>\t%P0, %P1[%c2]"; + else + return "vdup.<V_sz_elem>\t%q0, %P1[%c2]"; + } + "&& REGNO (operands[1]) <= LAST_ARM_REGNUM" + [(set (match_dup 0) + (vec_duplicate:VDQW (match_dup 3)))] + { + unsigned HOST_WIDE_INT elt = UINTVAL (operands[2]); + if (BYTES_BIG_ENDIAN) elt = GET_MODE_NUNITS (<V_double_vector_mode>mode) - 1 - elt; - operands[2] = GEN_INT (elt); - } - if (<Is_d_reg>) - return "vdup.<V_sz_elem>\t%P0, %P1[%c2]"; - else - return "vdup.<V_sz_elem>\t%q0, %P1[%c2]"; -} - [(set_attr "type" "neon_dup<q>")] + unsigned HOST_WIDE_INT size = GET_MODE_SIZE (<V_elem>mode); + int base_regno = REGNO (operands[1]); + int regno = (base_regno + + subreg_regno_offset (base_regno, <V_double_vector_mode>mode, + elt * size, SImode)); + unsigned HOST_WIDE_INT offset = (elt * size) % GET_MODE_SIZE (SImode); + if (offset != 0) + { + gcc_assert (offset < 4); + rtx reg = gen_rtx_REG (SImode, regno); + rtx shift = gen_rtx_LSHIFTRT (SImode, reg, + GEN_INT (offset * BITS_PER_UNIT)); + emit_move_insn (gen_rtx_SUBREG (SImode, operands[3], 0), + shift); + } + else + operands[3] = gen_rtx_REG (<V_elem>mode, regno); + } + [(set_attr "length" "4,8") + (set_attr "type" "neon_dup<q>")] ) -(define_insn "neon_vdup_lane<mode>_internal" - [(set (match_operand:VHFBF 0 "s_register_operand" "=w") - (vec_duplicate:VHFBF - (vec_select:<V_elem> - (match_operand:<V_double_vector_mode> 1 "s_register_operand" "w") - (parallel [(match_operand:SI 2 "immediate_operand" "i")]))))] - "TARGET_NEON && (TARGET_FP16 || TARGET_BF16_SIMD)" -{ - if (BYTES_BIG_ENDIAN) - { - int elt = INTVAL (operands[2]); +; There isn't an intrinsic for this, but the compiler can generate it +; idomatically from other operations. +(define_insn_and_split "neon_vdupq_lane<VQ2BF:mode>_internal" + [(set (match_operand:VQ2BF 0 "s_register_operand" "=w,w") + (vec_duplicate:VQ2BF + (vec_select:<V_elem> + (match_operand:VQ2BF 1 "s_register_operand" "w,r") + (parallel [(match_operand:SI 2 "immediate_operand" "i,i")])))) + (clobber (match_scratch:<V_elem> 3 "=X,r"))] + "TARGET_NEON" + "#" + "" + [(parallel + [(set (match_dup 0) + (vec_duplicate:VQ2BF + (vec_select:<V_elem> (match_dup 1) (parallel [(match_dup 2)])))) + (clobber (match_dup 3))])] + { + HOST_WIDE_INT elt = INTVAL (operands[2]); + if (elt >= GET_MODE_NUNITS (<MODE>mode) / 2) + { + elt -= GET_MODE_NUNITS (<MODE>mode) / 2; + operands[1] = simplify_gen_subreg (<V_HALF>mode, operands[1], + <MODE>mode, + GET_MODE_SIZE (<V_HALF>mode)); + operands[2] = GEN_INT (elt); + } + else + operands[1] = gen_lowpart (<V_HALF>mode, operands[1]); + } + [(set_attr "type" "neon_dup<q>") + (set_attr "length" "4,8")] +) + +(define_insn_and_split "neon_vdup_lane<VHFBF:mode>_internal" + [(set (match_operand:VHFBF 0 "s_register_operand" "=w,w") + (vec_duplicate:VHFBF + (vec_select:<V_elem> + (match_operand:<V_double_vector_mode> 1 "s_register_operand" "w,r") + (parallel [(match_operand:SI 2 "immediate_operand" "i,i")])))) + (clobber (match_scratch:<V_elem> 3 "=X,r"))] + "TARGET_NEON && (TARGET_FP16 || TARGET_BF16_SIMD)" + { + if (BYTES_BIG_ENDIAN) + { + int elt = INTVAL (operands[2]); + elt = GET_MODE_NUNITS (<V_double_vector_mode>mode) - 1 - elt; + operands[2] = GEN_INT (elt); + } + if (<Is_d_reg>) + return "vdup.<V_sz_elem>\t%P0, %P1[%c2]"; + else + return "vdup.<V_sz_elem>\t%q0, %P1[%c2]"; + } + "&& REGNO (operands[1]) <= LAST_ARM_REGNUM" + [(set (match_dup 0) + (vec_duplicate:VHFBF (match_dup 3)))] + { + unsigned HOST_WIDE_INT elt = UINTVAL (operands[2]); + if (BYTES_BIG_ENDIAN) elt = GET_MODE_NUNITS (<V_double_vector_mode>mode) - 1 - elt; - operands[2] = GEN_INT (elt); - } - if (<Is_d_reg>) - return "vdup.<V_sz_elem>\t%P0, %P1[%c2]"; - else - return "vdup.<V_sz_elem>\t%q0, %P1[%c2]"; -} - [(set_attr "type" "neon_dup<q>")] + unsigned HOST_WIDE_INT size = GET_MODE_SIZE (<V_elem>mode); + int base_regno = REGNO (operands[1]); + int regno = (base_regno + + subreg_regno_offset (base_regno, <V_double_vector_mode>mode, + elt * size, SImode)); + unsigned HOST_WIDE_INT offset = (elt * size) % GET_MODE_SIZE (SImode); + if (offset != 0) + { + gcc_assert (offset < 4); + rtx reg = gen_rtx_REG (SImode, regno); + rtx shift = gen_rtx_LSHIFTRT (SImode, reg, + GEN_INT (offset * BITS_PER_UNIT)); + emit_move_insn (gen_rtx_SUBREG (SImode, operands[3], 0), + shift); + } + else + operands[3] = gen_rtx_REG (<V_elem>mode, regno); + } + [(set_attr "length" "4,8") + (set_attr "type" "neon_dup<q>")] ) (define_expand "neon_vdup_lane<mode>" diff --git a/gcc/testsuite/gcc.target/arm/armv8_2-fp16-neon-1.c b/gcc/testsuite/gcc.target/arm/armv8_2-fp16-neon-1.c index d32c723e5e3e4..2292be5bcccdf 100644 --- a/gcc/testsuite/gcc.target/arm/armv8_2-fp16-neon-1.c +++ b/gcc/testsuite/gcc.target/arm/armv8_2-fp16-neon-1.c @@ -2,6 +2,7 @@ /* { dg-require-effective-target arm_v8_2a_fp16_neon_ok } */ /* { dg-options "-O2" } */ /* { dg-add-options arm_v8_2a_fp16_neon } */ +/* { dg-final { check-function-bodies "**" "" "" } } */ /* Test instructions generated for the FP16 vector intrinsics. */ @@ -186,43 +187,35 @@ VCVT_N_TEST (vcvt, _u16_f16, uint, float) VCVT_TEST (vcvta, _s16_f16, int, float) /* { dg-final { scan-assembler-times {vcvta\.s16\.f16\td[0-9]+, d[0-9]+} 1 } } - { dg-final { scan-assembler-times {vcvta\.s16\.f16\tq[0-9]+, q[0-9]+} 1 } } -*/ + { dg-final { scan-assembler-times {vcvta\.s16\.f16\tq[0-9]+, q[0-9]+} 1 } } */ VCVT_TEST (vcvta, _u16_f16, uint, float) /* { dg-final { scan-assembler-times {vcvta\.u16\.f16\td[0-9]+, d[0-9]+} 1 } } - { dg-final { scan-assembler-times {vcvta\.u16\.f16\tq[0-9]+, q[0-9]+} 1 } } -*/ + { dg-final { scan-assembler-times {vcvta\.u16\.f16\tq[0-9]+, q[0-9]+} 1 } } */ VCVT_TEST (vcvtm, _s16_f16, int, float) /* { dg-final { scan-assembler-times {vcvtm\.s16\.f16\td[0-9]+, d[0-9]+} 1 } } - { dg-final { scan-assembler-times {vcvtm\.s16\.f16\tq[0-9]+, q[0-9]+} 1 } } -*/ + { dg-final { scan-assembler-times {vcvtm\.s16\.f16\tq[0-9]+, q[0-9]+} 1 } } */ VCVT_TEST (vcvtm, _u16_f16, uint, float) /* { dg-final { scan-assembler-times {vcvtm\.u16\.f16\td[0-9]+, d[0-9]+} 1 } } - { dg-final { scan-assembler-times {vcvtm\.u16\.f16\tq[0-9]+, q[0-9]+} 1 } } -*/ + { dg-final { scan-assembler-times {vcvtm\.u16\.f16\tq[0-9]+, q[0-9]+} 1 } } */ VCVT_TEST (vcvtn, _s16_f16, int, float) /* { dg-final { scan-assembler-times {vcvtn\.s16\.f16\td[0-9]+, d[0-9]+} 1 } } - { dg-final { scan-assembler-times {vcvtn\.s16\.f16\tq[0-9]+, q[0-9]+} 1 } } -*/ + { dg-final { scan-assembler-times {vcvtn\.s16\.f16\tq[0-9]+, q[0-9]+} 1 } } */ VCVT_TEST (vcvtn, _u16_f16, uint, float) /* { dg-final { scan-assembler-times {vcvtn\.u16\.f16\td[0-9]+, d[0-9]+} 1 } } - { dg-final { scan-assembler-times {vcvtn\.u16\.f16\tq[0-9]+, q[0-9]+} 1 } } -*/ + { dg-final { scan-assembler-times {vcvtn\.u16\.f16\tq[0-9]+, q[0-9]+} 1 } } */ VCVT_TEST (vcvtp, _s16_f16, int, float) /* { dg-final { scan-assembler-times {vcvtp\.s16\.f16\td[0-9]+, d[0-9]+} 1 } } - { dg-final { scan-assembler-times {vcvtp\.s16\.f16\tq[0-9]+, q[0-9]+} 1 } } -*/ + { dg-final { scan-assembler-times {vcvtp\.s16\.f16\tq[0-9]+, q[0-9]+} 1 } } */ VCVT_TEST (vcvtp, _u16_f16, uint, float) /* { dg-final { scan-assembler-times {vcvtp\.u16\.f16\td[0-9]+, d[0-9]+} 1 } } - { dg-final { scan-assembler-times {vcvtp\.u16\.f16\tq[0-9]+, q[0-9]+} 1 } } -*/ + { dg-final { scan-assembler-times {vcvtp\.u16\.f16\tq[0-9]+, q[0-9]+} 1 } } */ UNOP_TEST (vabs) /* { dg-final { scan-assembler-times {vabs\.f16\td[0-9]+, d[0-9]+} 1 } } @@ -380,40 +373,121 @@ test_vmov_n_f16 (float16_t a) { return vmov_n_f16 (a); } +/* +** test_vmov_n_f16: +** ( + softfp +** vdup.16 (d[0-9]+), r0 +** vmov r0, r1, \1 @ v4hf +** | + hardfp + Note: We should be able to do this with 'vdup.16 d0, d[0]' +** vmov.f16 (r[0-9]+), s0 @ __fp16 +** vdup.16 d0, \2 +** ) +** bx lr +*/ float16x4_t test_vdup_n_f16 (float16_t a) { return vdup_n_f16 (a); } -/* { dg-final { scan-assembler-times {vdup\.16\td[0-9]+, r[0-9]+} 2 } } */ +/* +** test_vdup_n_f16: +** ( + softfp +** vdup.16 (d[0-9]+), r0 +** vmov r0, r1, \1 @ v4hf +** | + hardfp + Note: We should be able to do this with 'vdup.16 d0, d[0]' +** vmov.f16 (r[0-9]+), s0 @ __fp16 +** vdup.16 d0, \2 +** ) +** bx lr +*/ float16x8_t test_vmovq_n_f16 (float16_t a) { return vmovq_n_f16 (a); } +/* +** test_vmovq_n_f16: +** ( + softfp +** vdup.16 q[0-9]+, r0 +** vmov r0, r1, d[0-9]+ @ v8hf +** vmov r2, r3, d[0-9]+ +** | + hardfp + Note: We should be able to do this with 'vdup.16 d0, d[0]' +** vmov.f16 (r[0-9]+), s0 @ __fp16 +** vdup.16 q0, \1 +** ) +** bx lr +*/ float16x8_t test_vdupq_n_f16 (float16_t a) { return vdupq_n_f16 (a); } -/* { dg-final { scan-assembler-times {vdup\.16\tq[0-9]+, r[0-9]+} 2 } } */ +/* +** test_vdupq_n_f16: +** ( + softfp +** vdup.16 q[0-9]+, r0 +** vmov r0, r1, d[0-9]+ @ v8hf +** vmov r2, r3, d[0-9]+ +** | + hardfp + Note: We should be able to do this with 'vdup.16 d0, d[0]' +** vmov.f16 (r[0-9]+), s0 @ __fp16 +** vdup.16 q0, \1 +** ) +** bx lr +*/ float16x4_t test_vdup_lane_f16 (float16x4_t a) { return vdup_lane_f16 (a, 1); } -/* { dg-final { scan-assembler-times {vdup\.16\td[0-9]+, d[0-9]+\[1\]} 1 } } */ +/* +** test_vdup_lane_f16: +** ( + softfp +** lsrs? (r[0-9]+), r0, #16 +** vdup.16 (d[0-9]+), \1 +** vmov r0, r1, \2 @ v4hf +** | + hard +** vdup.16 d0, d0\[1\] +** ) +** bx lr +*/ float16x8_t test_vdupq_lane_f16 (float16x4_t a) { return vdupq_lane_f16 (a, 1); } -/* { dg-final { scan-assembler-times {vdup\.16\tq[0-9]+, d[0-9]+\[1\]} 1 } } */ +/* +** test_vdupq_lane_f16: +** ( + softfp +** lsrs? (r[0-9]+), r0, #16 +** vdup.16 q[0-9], \1 +** vmov r0, r1, d[0-9]+ @ v8hf +** vmov r2, r3, d[0-9]+ +** | + hard +** vdup.16 q0, d0\[1\] +** ) +** bx lr +*/ float16x4_t test_vext_f16 (float16x4_t a, float16x4_t b) diff --git a/gcc/testsuite/gcc.target/arm/armv8_2-fp16-neon-2.c b/gcc/testsuite/gcc.target/arm/armv8_2-fp16-neon-2.c index 9e783046d2b4b..a07dca3228fc4 100644 --- a/gcc/testsuite/gcc.target/arm/armv8_2-fp16-neon-2.c +++ b/gcc/testsuite/gcc.target/arm/armv8_2-fp16-neon-2.c @@ -402,41 +402,121 @@ test_vmov_n_f16 (float16_t a) { return vmov_n_f16 (a); } +/* +** test_vmov_n_f16: +** ( + softfp +** vdup.16 (d[0-9]+), r0 +** vmov r0, r1, \1 @ v4hf +** | + hardfp + Note: We should be able to do this with 'vdup.16 d0, d[0]' +** vmov.f16 (r[0-9]+), s0 @ __fp16 +** vdup.16 d0, \2 +** ) +** bx lr +*/ float16x4_t test_vdup_n_f16 (float16_t a) { return vdup_n_f16 (a); } -/* { dg-final { scan-assembler-times {vdup\.16\td[0-9]+, r[0-9]+} 3 } } */ +/* +** test_vdup_n_f16: +** ( + softfp +** vdup.16 (d[0-9]+), r0 +** vmov r0, r1, \1 @ v4hf +** | + hardfp + Note: We should be able to do this with 'vdup.16 d0, d[0]' +** vmov.f16 (r[0-9]+), s0 @ __fp16 +** vdup.16 d0, \2 +** ) +** bx lr +*/ float16x8_t test_vmovq_n_f16 (float16_t a) { return vmovq_n_f16 (a); } +/* +** test_vmovq_n_f16: +** ( + softfp +** vdup.16 q[0-9]+, r0 +** vmov r0, r1, d[0-9]+ @ v8hf +** vmov r2, r3, d[0-9]+ +** | + hardfp + Note: We should be able to do this with 'vdup.16 d0, d[0]' +** vmov.f16 (r[0-9]+), s0 @ __fp16 +** vdup.16 q0, \1 +** ) +** bx lr +*/ float16x8_t test_vdupq_n_f16 (float16_t a) { return vdupq_n_f16 (a); } -/* { dg-final { scan-assembler-times {vdup\.16\tq[0-9]+, r[0-9]+} 3 { target arm_hf_eabi } } } */ -/* { dg-final { scan-assembler-times {vdup\.16\tq[0-9]+, r[0-9]+} 2 { target { ! arm_hf_eabi } } } } */ +/* +** test_vdupq_n_f16: +** ( + softfp +** vdup.16 q[0-9]+, r0 +** vmov r0, r1, d[0-9]+ @ v8hf +** vmov r2, r3, d[0-9]+ +** | + hardfp + Note: We should be able to do this with 'vdup.16 d0, d[0]' +** vmov.f16 (r[0-9]+), s0 @ __fp16 +** vdup.16 q0, \1 +** ) +** bx lr +*/ float16x4_t test_vdup_lane_f16 (float16x4_t a) { return vdup_lane_f16 (a, 1); } -/* { dg-final { scan-assembler-times {vdup\.16\td[0-9]+, d[0-9]+\[1\]} 1 } } */ +/* +** test_vdup_lane_f16: +** ( + softfp +** lsrs? (r[0-9]+), r0, #16 +** vdup.16 (d[0-9]+), \1 +** vmov r0, r1, \2 @ v4hf +** | + hard +** vdup.16 d0, d0\[1\] +** ) +** bx lr +*/ float16x8_t test_vdupq_lane_f16 (float16x4_t a) { return vdupq_lane_f16 (a, 1); } -/* { dg-final { scan-assembler-times {vdup\.16\tq[0-9]+, d[0-9]+\[1\]} 1 } } */ +/* +** test_vdupq_lane_f16: +** ( + softfp +** lsrs? (r[0-9]+), r0, #16 +** vdup.16 q[0-9], \1 +** vmov r0, r1, d[0-9]+ @ v8hf +** vmov r2, r3, d[0-9]+ +** | + hard +** vdup.16 q0, d0\[1\] +** ) +** bx lr +*/ float16x4_t test_vext_f16 (float16x4_t a, float16x4_t b) diff --git a/gcc/testsuite/gcc.target/arm/crypto-vsha1cq_u32.c b/gcc/testsuite/gcc.target/arm/crypto-vsha1cq_u32.c index e2835cf4122f3..61c2ee9468c0e 100644 --- a/gcc/testsuite/gcc.target/arm/crypto-vsha1cq_u32.c +++ b/gcc/testsuite/gcc.target/arm/crypto-vsha1cq_u32.c @@ -32,4 +32,3 @@ TEST_SHA1C_VEC_SELECT (GET_LANE) /* { dg-final { scan-assembler-times {sha1c.32\tq[0-9]+, q[0-9]+} 5 } } */ /* { dg-final { scan-assembler-times {vdup.32\tq[0-9]+, (?:r[0-9]+|d[0-9]+\[[0-9]+\])} 4 { xfail { arm_thumb2 && arm_hf_eabi } } } } */ -/* { dg-final { scan-assembler-times {vmov.32\tr[0-9]+, d[0-9]+\[[0-9]+\]} 3 } } */ diff --git a/gcc/testsuite/gcc.target/arm/crypto-vsha1h_u32.c b/gcc/testsuite/gcc.target/arm/crypto-vsha1h_u32.c index c67048ab36337..a4e9a48698c3c 100644 --- a/gcc/testsuite/gcc.target/arm/crypto-vsha1h_u32.c +++ b/gcc/testsuite/gcc.target/arm/crypto-vsha1h_u32.c @@ -28,4 +28,3 @@ TEST_SHA1H_VEC_SELECT (GET_LANE) /* { dg-final { scan-assembler-times {sha1h.32\tq[0-9]+, q[0-9]+} 5 } } */ /* { dg-final { scan-assembler-times {vdup.32\tq[0-9]+, (?:r[0-9]+|d[0-9]+\[[0-9]+\])} 4 { xfail { arm_thumb2 && arm_hf_eabi } } } } */ -/* { dg-final { scan-assembler-times {vmov.32\tr[0-9]+, d[0-9]+\[[0-9]+\]} 3 } } */ diff --git a/gcc/testsuite/gcc.target/arm/crypto-vsha1mq_u32.c b/gcc/testsuite/gcc.target/arm/crypto-vsha1mq_u32.c index 967b682de27ff..d1f30d647e366 100644 --- a/gcc/testsuite/gcc.target/arm/crypto-vsha1mq_u32.c +++ b/gcc/testsuite/gcc.target/arm/crypto-vsha1mq_u32.c @@ -32,4 +32,3 @@ TEST_SHA1M_VEC_SELECT (GET_LANE) /* { dg-final { scan-assembler-times {sha1m.32\tq[0-9]+, q[0-9]+} 5 } } */ /* { dg-final { scan-assembler-times {vdup.32\tq[0-9]+, (?:r[0-9]+|d[0-9]+\[[0-9]+\])} 4 { xfail { arm_thumb2 && arm_hf_eabi } } } } */ -/* { dg-final { scan-assembler-times {vmov.32\tr[0-9]+, d[0-9]+\[[0-9]+\]} 3 } } */ diff --git a/gcc/testsuite/gcc.target/arm/crypto-vsha1pq_u32.c b/gcc/testsuite/gcc.target/arm/crypto-vsha1pq_u32.c index 09e7632569615..43425f3d5ecf7 100644 --- a/gcc/testsuite/gcc.target/arm/crypto-vsha1pq_u32.c +++ b/gcc/testsuite/gcc.target/arm/crypto-vsha1pq_u32.c @@ -32,4 +32,3 @@ TEST_SHA1P_VEC_SELECT (GET_LANE) /* { dg-final { scan-assembler-times {sha1p.32\tq[0-9]+, q[0-9]+} 5 } } */ /* { dg-final { scan-assembler-times {vdup.32\tq[0-9]+, (?:r[0-9]+|d[0-9]+\[[0-9]+\])} 4 { xfail { arm_thumb2 && arm_hf_eabi } } } } */ -/* { dg-final { scan-assembler-times {vmov.32\tr[0-9]+, d[0-9]+\[[0-9]+\]} 3 } } */ -- 2.54.0