[PATCH] RISC-V: Fix single-step expansion [PR126550].

Hi,

In expand_const_vector_single_step_npatterns, we use a second vector
builder that is derived from the main one, in order to create a
different alternating pattern for constant synthesis.  We later use the
second builder's number of patterns for creating an intermediate=20
operation. The second builder can have a different number of patterns=20
than the first one, however, for example when its "global" pattern is=20
simpler.

This patch uses npatterns from the original builder.

Regtested on rv64gcv_zvl512b.

It's surprising that this went unnoticed for so long.  Definitely=20
requires backporting to 16, 15, and maybe 14.

Regards
 Robin


	PR target/126550

gcc/ChangeLog:

	* config/riscv/riscv-v.cc (expand_const_vector_single_step_npatterns):
	User global builder's npatterns.

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/rvv/autovec/pr126550-2.c: New test.
	* gcc.target/riscv/rvv/autovec/pr126550.c: New test.
---
 gcc/config/riscv/riscv-v.cc                   |  2 +-
 .../gcc.target/riscv/rvv/autovec/pr126550-2.c | 14 +++++++
 .../gcc.target/riscv/rvv/autovec/pr126550.c   | 41 +++++++++++++++++++
 3 files changed, 56 insertions(+), 1 deletion(-)
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/pr126550-2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/pr126550.c

diff --git a/gcc/config/riscv/riscv-v.cc b/gcc/config/riscv/riscv-v.cc
index fd4fd89d05d..c7d67be01a0 100644
--- a/gcc/config/riscv/riscv-v.cc
+++ b/gcc/config/riscv/riscv-v.cc
@@ -1570,7 +1570,7 @@ expand_const_vector_single_step_npatterns (rtx target=
, rvv_builder *builder)
 	  rtx tmp2 =3D gen_reg_rtx (builder->mode ());
 	  rtx step
 	    =3D simplify_binary_operation (MINUS, builder->inner_mode (),
-					 builder->elt (v.npatterns()),
+					 builder->elt (builder->npatterns ()),
 					 builder->elt (0));
 	  expand_vec_series (tmp2, const0_rtx, step, tmp1);
=20
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr126550-2.c b/gcc/=
testsuite/gcc.target/riscv/rvv/autovec/pr126550-2.c
new file mode 100644
index 00000000000..d04231f6e09
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr126550-2.c
@@ -0,0 +1,14 @@
+/* { dg-do compile } */
+/* { dg-options "-O3 -march=3Drv64gcv_zvl256b -mabi=3Dlp64d" } */
+
+#include <stdint.h>
+typedef uint16_t v16 __attribute__((vector_size(32)));
+
+v16
+foo (v16 x)
+{
+  return __builtin_shufflevector (x, x, 0, 1, 0, 1, 2, 3, 2, 3, 4, 5, 4, 5=
, 6,
+				  7, 6, 7);
+}
+
+/* { dg-final { scan-assembler-not "vmv.v.i\\sv\[0-9\]+,0" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr126550.c b/gcc/te=
stsuite/gcc.target/riscv/rvv/autovec/pr126550.c
new file mode 100644
index 00000000000..41b04d1c596
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr126550.c
@@ -0,0 +1,41 @@
+/* { dg-do run } */
+/* { dg-require-effective-target rvv_zvl256b_ok } */
+/* { dg-additional-options "-O3 -march=3Drv64gcv_zvl256b -mabi=3Dlp64d -fn=
o-vect-cost-model -std=3Dgnu99" } */
+
+#include <stdint.h>
+
+struct Pair { uint16_t first, second; };
+struct S { uint16_t a[2], b[2]; uint32_t r; };
+
+__attribute__((noipa))
+void load(struct S *dst, const struct Pair *src, unsigned long n)
+{
+  for (unsigned long k =3D 0; k < n; k++) {
+    dst[k].a[0] =3D src[k].first;
+    dst[k].a[1] =3D src[k].second;
+    dst[k].b[0] =3D src[k].first;
+    dst[k].b[1] =3D src[k].second;
+  }
+}
+
+#define N 40
+static struct Pair src[N];
+static struct S    out[N];
+
+int main(void)
+{
+  for (unsigned i =3D 0; i < N; i++) {
+    src[i].first =3D (uint16_t)(i * 2u + 1);
+    src[i].second =3D (uint16_t)(i * 3u + 2);
+  }
+  load(out, src, N);
+
+  for (unsigned i =3D 0; i < N; i++) {
+    uint16_t f =3D src[i].first, s =3D src[i].second;
+    if (out[i].a[0] !=3D f || out[i].a[1] !=3D s ||
+      out[i].b[0] !=3D f || out[i].b[1] !=3D s) {
+        __builtin_abort ();
+    }
+  }
+  return 0;
+}
--=20
2.54.0