Re: [PATCH v5] RISC-V: Fix riscv_subword_address for big-endian targets.

On 7/20/2026 8:54 AM, Aleksa Paunovic wrote:
> From: Chao-ying Fu <[email protected]>
>
> Ensure the proper sub-word address is computed
> when using built-in atomics on big-endian RISC-V targets.
>
> Without this change, multiple tests were failing, including:
>      libatomic.c/atomic-compare-exchange-1.c
>      libatomic.c/atomic-compare-exchange-2.c
>      libatomic.c/atomic-exchange-1.c
>      libatomic.c/atomic-exchange-2.c
>      libatomic.c/atomic-op-1.c
>      libatomic.c/atomic-op-2.c
>      libatomic.c/generic-2.c
>      gcc.target/riscv/amo/inline-atomics-3.c
>      gcc.target/riscv/amo/inline-atomics-4.c
>      gcc.target/riscv/amo/inline-atomics-5.c
>      gcc.target/riscv/amo/inline-atomics-6.c
>      gcc.target/riscv/amo/inline-atomics-7.c
>      gcc.target/riscv/amo/inline-atomics-8.c
>
> The patch was tested using QEMU modified to run big-endian RISC-V
> executables [1].
>
> [1] https://github.com/djtodoro/qemu/tree/riscvbe/current#
>
> Signed-off-by: Aleksa Paunovic <[email protected]>
>
> gcc/ChangeLog:
>
> 	* config/riscv/riscv.cc (riscv_subword_address): Add emit_move_insn for big-endian.
>
> gcc/testsuite/ChangeLog:
>
> 	* gcc.target/riscv/amo/big-endian-subword-amo-hi.c: New test.
> 	* gcc.target/riscv/amo/big-endian-subword-amo-qi.c: New test.
Thanks.  I've pushed this to the trunk.
jeff