[PATCH] RISC-V: Don't synthesize VLS vector constants.

Hi,

In PR126550 I noticed that we expand a constant vector using a "VLA"
stepped-pattern expansion with several ops (vid, shift, add) while we
could just load the constant from the constant pool.  On top, this
particular expansion uses a different constant that it stores in the
constant pool anyway, so it's twice as bad.  Until we have better 
heuristics, this patch forces known-length vector constants to memory.

Regtested on rv64gcv_zvl512b.

Regards
 Robin

gcc/ChangeLog:

	* config/riscv/riscv-v.cc (expand_const_vector): Force VLS
	constants to mem.

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/rvv/autovec/pr126550-2.c: Expect
	constant-pool vector load.
---
 gcc/config/riscv/riscv-v.cc                          | 12 ++++++++++++
 .../gcc.target/riscv/rvv/autovec/pr126550-2.c        |  1 +
 2 files changed, 13 insertions(+)

diff --git a/gcc/config/riscv/riscv-v.cc b/gcc/config/riscv/riscv-v.cc
index 096e986c740..bec1c9ebaec 100644
--- a/gcc/config/riscv/riscv-v.cc
+++ b/gcc/config/riscv/riscv-v.cc
@@ -1736,6 +1736,18 @@ expand_const_vector (rtx target, rtx src)
   if (const_vec_series_p (src, &base, &step))
     return expand_const_vec_series (target, base, step);
 
+  /* It's often better to just load a constant vector rather than
+     trying to synthesize is.  For now, do that when we know we're
+     dealing with a VLS mode.  */
+  machine_mode mode = GET_MODE (src);
+  if (GET_MODE_NUNITS (mode).is_constant ()
+      && !targetm.cannot_force_const_mem (mode, src))
+    {
+      src = force_const_mem (mode, src);
+      emit_move_insn (target, src);
+      return;
+    }
+
   /* Handle variable-length vector.  */
   unsigned int nelts_per_pattern = CONST_VECTOR_NELTS_PER_PATTERN (src);
   unsigned int npatterns = CONST_VECTOR_NPATTERNS (src);
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr126550-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr126550-2.c
index d04231f6e09..3cd567b42fb 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr126550-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr126550-2.c
@@ -12,3 +12,4 @@ foo (v16 x)
 }
 
 /* { dg-final { scan-assembler-not "vmv.v.i\\sv\[0-9\]+,0" } } */
+/* { dg-final { scan-assembler-times "vle16" 2 } } */
-- 
2.54.0