Re: Re：[PATCH] RISC-V: Implement reassociation width ho ok

>> We didn't solve it :) How many tests are affected?
> I turn the default vec_reassoc_width to 2 but find no new failed test. But the 
> case will trigger the spill. I think this is a possible side effect of the reassoc
> optimization. Given that vector loads/stores are quite expensive, we should be
> careful when increasing vec_reassoc_width in the future.
> ```
> /* option: -O3 -march=rv64gcv -mabi=lp64d -mrvv-vector-bits=zvl */
> typedef unsigned char v128qi __attribute__ ((vector_size (128)));
> v128qi
> sum4 (const volatile v128qi *p)
> {
>  v128qi hold1 = p[4];
>  v128qi hold2 = p[5];
>  v128qi sum = p[0] + p[1] + p[2] + p[3];
>  return (sum ^ hold1) - hold2;
> }
> ```

That's LMUL8 for zvl128b?  Not totally surprising but also nothing I 
would have thought of right away.  With reductions, register pressure 
must grow I guess, otherwise we couldn't reassociate.  But that's an 
LMUL issue more than it is a reassociation issue IMHO.
I don't see a good way of reassociating freely with only four 
registers...


-- 
Regards
 Robin