Re: [PATCH v4 3/5] RISC-V: Widen fusion pair bitmask to unsigned HOST_WIDE_INT

On 7/29/2026 1:17 AM, Jin Ma wrote:
> The riscv_fusion_pairs enum and the fusible_ops tune field use
> unsigned int, leaving only 18 bits for new fusion types.  Widen
> them to unsigned HOST_WIDE_INT so that future CPUs can define
> more than 32 fusion pairs without overflow.
>
> gcc/ChangeLog:
>
> 	* config/riscv/riscv-protos.h (enum riscv_fusion_pairs): Use
> 	HOST_WIDE_INT_1U for bit masks.
> 	(riscv_get_fusible_ops): Return unsigned HOST_WIDE_INT.
> 	* config/riscv/riscv.cc (struct riscv_tune_param): Change
> 	fusible_ops to unsigned HOST_WIDE_INT.
> 	(riscv_get_fusible_ops): Likewise.
OK.  Also note that if this is insufficient we can always add more 
fields in this structure.

jeff