[v5,3/3] aarch64: Add `SME_MOP4` instrinsics and corresponding insns

Hi Karl,

Sorry for the long delay... Right, so I asked to split the patterns to avoid non-existing
instructions. However you can still combine some patterns where only the accumulator is
different, eg these:

+;; _za16_bf16_bf16 (only if __ARM_FEATURE_SME_B16B16 != 0)
+;; _za32_bf16_bf16

and:

+;; _za16_f16_f16 (only if __ARM_FEATURE_SME_F16F16 != 0)
+;; _za32_f16_f16

(the extra condition for the instruction would be part of the iterator).

It's less obvious whether you could do these given the signed/unsigned combinations
are not identical (so unless it's easy, best to leave them separately):

+;; _za32_s16_s16
+;; _za32_u16_u16

and:

+;; _za64_s16_s16 (only if __ARM_FEATURE_SME_I16I64 != 0)
+;; _za64_u16_u16 (only if __ARM_FEATURE_SME_I16I64 != 0)
+;; _za64_s16_u16 (only if __ARM_FEATURE_SME_I16I64 != 0)
+;; _za64_u16_s16 (only if __ARM_FEATURE_SME_I16I64 != 0)


About the iterators, I count around 31 new iterators, of which only 13 are used. I don't
think it makes sense to introduce iterators with just a single value like this:

+;; {u8, s8, mf8}
+(define_mode_iterator SVE_FULL_BI [VNx16QI])
+
+;; {u8, s8, mf8}x2
+(define_mode_iterator SVE_FULL_BIx2 [VNx32QI])

Since the single iterators are unused, why add them when you can just write the 2
iterators you actually want like this:

+;; {u8, s8, mf8}{x1,x2}
+(define_mode_iterator SVE_FULL_BIx12   [[VNx16QI] [VNx32QI]])
+(define_mode_iterator SVE_FULL_BIx12_2 [[VNx16QI] [VNx32QI]])

Note also several others are defined but completely unused, like:

+;; {u8, s8, mf8, u16, s16}x2
+(define_mode_iterator SVE_FULL_BHIx2 [VNx32QI VNx16HI])
+
+;; {u8, s8, mf8, u16, s16}{x1,x2}
+(define_mode_iterator SVE_FULL_BHIx12   [SVE_FULL_BHI SVE_FULL_BHIx2])
+(define_mode_iterator SVE_FULL_BHIx12_2 [SVE_FULL_BHIx12])


--- a/gcc/config/aarch64/constraints.md
+++ b/gcc/config/aarch64/constraints.md
@@ -48,6 +48,17 @@  (define_register_constraint "x" "FP_LO_REGS"
 (define_register_constraint "y" "FP_LO8_REGS"
   "SVE/AdvSIMD/FP  registers, V0 - V7.")
 
+(define_register_constraint "z" "FP_HI_REGS"
+  "SVE/NEON/FP registers, V16 - V31.")
+
+(define_register_constraint "Ux2" "FP_LO_REGS"
+  "Even SVE/NEON/FP registers, V0, V2, ..., V14."
+  "regno % 2 == 0")
+
+(define_register_constraint "Uz2" "FP_HI_REGS"
+  "Even SVE/NEON/FP registers, V16, V18, ..., V30."
+  "regno % 2 == 0")

These should follow the above and use AdvSIMD rather than NEON.

The rest looks good to me.

Cheers,
Wilco