[PATCH] LoongArch: simplify RTL template 'bstrins_bstrpick_for_and_imm'

Since this RTL template only applies to 64-bit target, we can simplify it.

gcc/ChangeLog:

        * config/loongarch/loongarch.cc: Remove redundant check of 64-bit
          target in helper function 'loongarch_use_bstrins_bstrpick_for_and'.

        * config/loongarch/loongarch.md: Simplify RTL template
          'bstrins_bstrpick_for_and_imm' to 64-bit target only.

Signed-off-by: Ben Shi <[email protected]>
---
 gcc/config/loongarch/loongarch.cc |  3 ---
 gcc/config/loongarch/loongarch.md | 17 +++++++++--------
 2 files changed, 9 insertions(+), 11 deletions(-)

diff --git a/gcc/config/loongarch/loongarch.cc b/gcc/config/loongarch/loongarch.cc
index b0f7abc0483..c1ab0fb02bb 100644
--- a/gcc/config/loongarch/loongarch.cc
+++ b/gcc/config/loongarch/loongarch.cc
@@ -4013,9 +4013,6 @@ loongarch_use_bstrins_for_ior_with_mask_1 (machine_mode mode,
 bool
 loongarch_use_bstrins_bstrpick_for_and (rtx op, machine_mode mode)
 {
-  if (!TARGET_64BIT)
-    return false;
-
   /* Avoid aggressive optimization of combine before reload.  */
   if (!reload_completed)
     return false;
diff --git a/gcc/config/loongarch/loongarch.md b/gcc/config/loongarch/loongarch.md
index 37ae5a2223e..78a76496570 100644
--- a/gcc/config/loongarch/loongarch.md
+++ b/gcc/config/loongarch/loongarch.md
@@ -1765,11 +1765,12 @@
     DONE;
   })

-(define_insn_and_split "bstrins_bstrpick_for_and_imm<mode>"
-  [(set (match_operand:X 0 "register_operand" "=r")
-       (and:X (match_operand:X 1 "register_operand" "r")
-              (match_operand:X 2 "const_int_operand" "i")))]
-  "loongarch_use_bstrins_bstrpick_for_and (operands[2], <mode>mode)"
+(define_insn_and_split "bstrins_bstrpick_for_and_imm"
+  [(set (match_operand:DI 0 "register_operand" "=r")
+       (and:DI (match_operand:DI 1 "register_operand" "r")
+               (match_operand:DI 2 "const_int_operand" "i")))]
+  "TARGET_64BIT
+   &amp;&amp; loongarch_use_bstrins_bstrpick_for_and (operands[2], DImode)"
   "#"
   "&amp;&amp; true"
   [(const_int 0)]
@@ -1777,9 +1778,9 @@
   unsigned HOST_WIDE_INT op2 = INTVAL (operands[2]);
   int leading_zero_bit = __builtin_clzll (op2);
   unsigned HOST_WIDE_INT mask = (~0ULL) &lt;&lt; (64 - leading_zero_bit);
-  emit_insn (gen_extzv<mode> (operands[0], operands[1],
-                             GEN_INT (64 - leading_zero_bit), const0_rtx));
-  emit_insn (gen_and<mode>3 (operands[0], operands[0], GEN_INT (op2 | mask)));
+  emit_insn (gen_extzvdi (operands[0], operands[1],
+                         GEN_INT (64 - leading_zero_bit), const0_rtx));
+  emit_insn (gen_anddi3 (operands[0], operands[0], GEN_INT (op2 | mask)));
 }
   [(set_attr "length" "8")])

--
2.39.3</mode></mode></mode></mode></[email protected]>