Re: [RFC] ifcvt: Account for parallelism when costing noce sequences

On 8/12/2026 7:07 AM, Kyrylo Tkachov wrote:
> I like the idea, and it makes sense.
> One thing I’ve been hitting with my if-conversion work recently is that if-conversion increasing the dependency chain length is what’s hurting wide cores. Adding more instructions that can go parallel is not a problem otherwise.
Right.  It's a problem we've largely ignored, but as has been shown, 
it's ripe for getting fixed.

>
>> Estimate the dependency level of simple, single-cycle register operations
>> and cost each level using the target issue rate.  Keep the existing serial
>> cost for size optimization and for sequences that need resource or alias
>> analysis.
>>
> I notice that mips has a pretty elaborate mips_seq_time mechanism. I wouldn’t advocate using it, just found it interesting when looking around.
Never saw all that before.   It's actually calling back into the 
scheduler which is a huge surprise, I didn't expect that the scheduler 
would support that.  It's not called often (looks like only during 
target initialization and some of the bits are re-used for the vr4130 
code to align code for parallel execution.  I'd worry it's probably too 
heavy-weight for where we need to call it.

jeff