[PATCH] RISC-V: Add Ascalon XG cpu support

Peter Bergner <[email protected]> Wed, 12 Aug 2026 14:04:58 -0500
Newsgroups	gmane.comp.gcc.patches
Message-ID	<[email protected]>
This adds support for the global version of Ascalon X (tt-ascalon-xg)
to the list of known cores.  The difference between Ascalon X & XG is XG
does not have the zvkng extension and it has reduced vector FP64 throughput.

Notes on my implementation: I decided against renaming tt_ascalon_d8 to
tt_ascalon_x as I thought that was too much churn for little benefit.  Given the
huge similarity between the X and XG, I used the same tt_ascalon_d8 automaton
for both cores, just redirecting XG's FP64 vector ops into a new non-pipelined
unit to reduce their throughput.

Regtested on rv64gcv-linux with no regressions.
Ok for trunk?

I'd eventually like to backport this too.  Ok for backports once it has
baked on trunk for a while?

Peter



2026-08-12  Peter Bergner  <[email protected]>

gcc/
	* config/riscv/riscv-cores.def (RISCV_TUNE): Add tt-ascalon-xg.
	(RISCV_CORE): Likewise.
	* config/riscv/riscv-opts.h (enum riscv_microarchitecture_type):
	Add tt_ascalon_xg.
	* config/riscv/riscv.md (tune): Likewise.
	* config/riscv/tt-ascalon-d8.md (asc-xg-fp64-vec0, asc-xg-fp64-vec1):
	New define_cpu_unit.
	(tt_ascalon_xg_fp64_vec): New define_reservation.
	(tt_ascalon_d8_int_load, tt_ascalon_d8_alu, tt_ascalon_d8_sfb,
	tt_ascalon_d8_branch, tt_ascalon_d8_float_move, tt_ascalon_d8_fcvt,
	tt_ascalon_d8_fcmp, tt_ascalon_d8_imul, tt_ascalon_d8_idiv,
	tt_ascalon_d8_fadd, tt_ascalon_d8_mul, tt_ascalon_d8_float_fma,
	tt_ascalon_d8_float_div_half, tt_ascalon_d8_float_div_single,
	tt_ascalon_d8_float_div_double, tt_ascalon_d8_popcount,
	tt_ascalon_d8_vec_load, tt_ascalon_d8_vec_store,
	tt_ascalon_d8_vec_load_strided, tt_ascalon_d8_vec_store_strided,
	tt_ascalon_d8_vec_load_indexed, tt_ascalon_d8_vec_store_indexed,
	tt_ascalon_d8_vec_loadstore_seg, tt_ascalon_d8_vec_alu_1,
	tt_ascalon_d8_vec_alu_2, tt_ascalon_d8_vec_alu_3,
	tt_ascalon_d8_vec_alu_4, tt_ascalon_d8_vec_imul, tt_ascalon_d8_vec_pop,
	tt_ascalon_d8_vec_crypto_aes, tt_ascalon_d8_vec_crypto_sha,
	tt_ascalon_d8_vec_perm_1, tt_ascalon_d8_vec_perm_3,
	tt_ascalon_d8_vec_perm_4, tt_ascalon_d8_vec_reduction,
	tt_ascalon_d8_vec_ordered_reduction, tt_ascalon_d8_vec_idiv_byte,
	tt_ascalon_d8_vec_idiv_half, tt_ascalon_d8_vec_idiv_single,
	tt_ascalon_d8_vec_idiv_double, tt_ascalon_d8_vec_float_divsqrt_half,
	tt_ascalon_d8_vec_float_divsqrt_single,
	tt_ascalon_d8_vec_float_divsqrt_double, tt_ascalon_d8_vec_mask,
	tt_ascalon_d8_vec_vesetvl, tt_ascalon_d8_vec_setrm,
	tt_ascalon_d8_vec_readlen, tt_ascalon_d8_vec_unknown):
	Use tt_ascalon_xg.
	(tt_ascalon_d8_vec_fcmp, tt_ascalon_d8_vec_fadd,
	tt_ascalon_d8_vec_fmul): Disable vector instructions that produce FP64
	output values when tuning for tt_ascalon_xg.
	(tt_ascalon_xg_fp64_vec_insns): New define_insn_reservation.
	* doc/riscv-mcpu.texi: Regenerate.
	* doc/riscv-mtune.texi: Likewise.

Signed-off-by: Peter Bergner <[email protected]>
---
 gcc/config/riscv/riscv-cores.def  |   6 ++
 gcc/config/riscv/riscv-opts.h     |   1 +
 gcc/config/riscv/riscv.md         |   4 +-
 gcc/config/riscv/tt-ascalon-d8.md | 127 ++++++++++++++++++------------
 gcc/doc/riscv-mcpu.texi           |   2 +
 gcc/doc/riscv-mtune.texi          |   2 +
 6 files changed, 89 insertions(+), 53 deletions(-)

diff --git a/gcc/config/riscv/riscv-cores.def b/gcc/config/riscv/riscv-cores.def
index e7ae1cb934f..7be951ae2fc 100644
--- a/gcc/config/riscv/riscv-cores.def
+++ b/gcc/config/riscv/riscv-cores.def
@@ -41,6 +41,7 @@ RISCV_TUNE("sifive-7-series", sifive_7, sifive_7_tune_info)
 RISCV_TUNE("sifive-p400-series", sifive_p400, sifive_p400_tune_info)
 RISCV_TUNE("sifive-p600-series", sifive_p600, sifive_p600_tune_info)
 RISCV_TUNE("tt-ascalon-x", tt_ascalon_d8, tt_ascalon_d8_tune_info)
+RISCV_TUNE("tt-ascalon-xg", tt_ascalon_xg, tt_ascalon_d8_tune_info)
 RISCV_TUNE("thead-c906", generic, thead_c906_tune_info)
 RISCV_TUNE("xt-c908", xt_c908, xt_c908_tune_info)
 RISCV_TUNE("xt-c908v", generic, generic_ooo_tune_info)
@@ -180,6 +181,11 @@ RISCV_CORE("tt-ascalon-x",    "rva23s64_zfbfmin_zfh_zkr_zvbc_zvfbfmin_zvfbfwma_"
 			      "tt-ascalon-x")
 RISCV_CORE_ALIAS("tt-ascalon-x", "tt-ascalon-d8")
 
+RISCV_CORE("tt-ascalon-xg",   "rva23s64_zfbfmin_zfh_zkr_zvbc_zvfbfmin_zvfbfwma_"
+			      "zvfh_zvl256b_smaia_smmpm_smnpm_smrnmi_smstateen_"
+			      "ssaia_ssstrict_svadu",
+			      "tt-ascalon-xg")
+
 RISCV_CORE("xiangshan-nanhu",      "rv64imafdc_zba_zbb_zbc_zbs_"
 			      "zbkb_zbkc_zbkx_zknd_zkne_zknh_zksed_zksh_"
 			      "svinval_zicbom_zicboz",
diff --git a/gcc/config/riscv/riscv-opts.h b/gcc/config/riscv/riscv-opts.h
index 2a4e9260dce..25e827e9fb5 100644
--- a/gcc/config/riscv/riscv-opts.h
+++ b/gcc/config/riscv/riscv-opts.h
@@ -61,6 +61,7 @@ enum riscv_microarchitecture_type {
   generic_ooo,
   mips_p8700,
   tt_ascalon_d8,
+  tt_ascalon_xg,
   andes_25_series,
   andes_23_series,
   andes_45_series,
diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md
index 6f66f983d87..b9014b28b61 100644
--- a/gcc/config/riscv/riscv.md
+++ b/gcc/config/riscv/riscv.md
@@ -677,8 +677,8 @@ (define_attr "cannot_copy" "no,yes" (const_string "no"))
 ;; Keep this in sync with enum riscv_microarchitecture.
 (define_attr "tune"
   "generic,sifive_7,sifive_p400,sifive_p600,xiangshan,generic_ooo,mips_p8700,
-   tt_ascalon_d8,andes_25_series,andes_23_series,andes_45_series,spacemit_x60,
-   arcv_rmx100,arcv_rhx100,xt_c908"
+   tt_ascalon_d8,tt_ascalon_xg,andes_25_series,andes_23_series,andes_45_series,
+   spacemit_x60,arcv_rmx100,arcv_rhx100,xt_c908"
   (const (symbol_ref "((enum attr_tune) riscv_microarchitecture)")))
 
 ;; Describe a user's asm statement.
diff --git a/gcc/config/riscv/tt-ascalon-d8.md b/gcc/config/riscv/tt-ascalon-d8.md
index 7f7ed18004c..1ca4eb31876 100644
--- a/gcc/config/riscv/tt-ascalon-d8.md
+++ b/gcc/config/riscv/tt-ascalon-d8.md
@@ -27,6 +27,7 @@ (define_cpu_unit "asc-lsu0,asc-lsu1,asc-lsu2" "tt_ascalon_d8")
 (define_cpu_unit "asc-fxu0,asc-fxu1,asc-fxu2,asc-fxu3,asc-fxu4,asc-fxu5" "tt_ascalon_d8")
 (define_cpu_unit "asc-fpu0,asc-fpu1" "tt_ascalon_d8")
 (define_cpu_unit "asc-vec0,asc-vec1" "tt_ascalon_d8")
+(define_cpu_unit "asc-xg-fp64-vec0,asc-xg-fp64-vec1" "tt_ascalon_d8")
 
 ;; Shortcuts
 (define_reservation "tt_ascalon_d8_decode" "asc-decode0|asc-decode1|asc-decode2|asc-decode3|asc-decode4|asc-decode5|asc-decode6|asc-decode7")
@@ -41,16 +42,17 @@ (define_reservation "tt_ascalon_d8_fp" "asc-fpu0|asc-fpu1")
 (define_reservation "tt_ascalon_d8_vec0" "asc-vec0")
 (define_reservation "tt_ascalon_d8_vec1" "asc-vec1")
 (define_reservation "tt_ascalon_d8_vec" "asc-vec0|asc-vec1")
+(define_reservation "tt_ascalon_xg_fp64_vec" "asc-xg-fp64-vec0*4 | asc-xg-fp64-vec1*4")
 
 ;; Integer/float load/store
 (define_insn_reservation "tt_ascalon_d8_int_load" 4
-  (and (eq_attr "tune" "tt_ascalon_d8")
+  (and (eq_attr "tune" "tt_ascalon_d8,tt_ascalon_xg")
        (eq_attr "type" "load,store,fpload,fpstore"))
   "tt_ascalon_d8_decode,tt_ascalon_d8_ls")
 
 ;; Generic integer instructions.
 (define_insn_reservation "tt_ascalon_d8_alu" 1
-  (and (eq_attr "tune" "tt_ascalon_d8")
+  (and (eq_attr "tune" "tt_ascalon_d8,tt_ascalon_xg")
        (eq_attr "type" "unknown,const,arith,shift,slt,multi,auipc,nop,logical,\
 			move,bitmanip,rotate,min,max,minu,maxu,clz,ctz,atomic,\
 			condmove,mvpair,zicond"))
@@ -58,13 +60,13 @@ (define_insn_reservation "tt_ascalon_d8_alu" 1
 
 ;; Short forward branch
 (define_insn_reservation "tt_ascalon_d8_sfb" 1
-  (and (eq_attr "tune" "tt_ascalon_d8")
+  (and (eq_attr "tune" "tt_ascalon_d8,tt_ascalon_xg")
        (eq_attr "type" "sfb_alu"))
   "tt_ascalon_d8_decode,tt_ascalon_d8_br")
 
 ;; Branch instructions
 (define_insn_reservation "tt_ascalon_d8_branch" 1
-  (and (eq_attr "tune" "tt_ascalon_d8")
+  (and (eq_attr "tune" "tt_ascalon_d8,tt_ascalon_xg")
        (eq_attr "type" "branch,jump,call,jalr,ret,trap"))
   "tt_ascalon_d8_decode,tt_ascalon_d8_br")
 
@@ -72,23 +74,23 @@ (define_insn_reservation "tt_ascalon_d8_branch" 1
 ;; INT -> FP moves are executed by the FXU and FP -> INT moves
 ;; are executed by the FPU, but we can't model that at the moment.
 (define_insn_reservation "tt_ascalon_d8_float_move" 4
-  (and (eq_attr "tune" "tt_ascalon_d8")
+  (and (eq_attr "tune" "tt_ascalon_d8,tt_ascalon_xg")
        (eq_attr "type" "fmove"))
   "tt_ascalon_d8_decode,tt_ascalon_d8_fp")
 
 (define_insn_reservation "tt_ascalon_d8_fcvt" 3
-  (and (eq_attr "tune" "tt_ascalon_d8")
+  (and (eq_attr "tune" "tt_ascalon_d8,tt_ascalon_xg")
        (eq_attr "type" "fcvt,fcvt_i2f,fcvt_f2i"))
   "tt_ascalon_d8_decode,tt_ascalon_d8_fp")
 
 (define_insn_reservation "tt_ascalon_d8_fcmp" 2
-  (and (eq_attr "tune" "tt_ascalon_d8")
+  (and (eq_attr "tune" "tt_ascalon_d8,tt_ascalon_xg")
        (eq_attr "type" "fcmp"))
   "tt_ascalon_d8_decode,tt_ascalon_d8_fp")
 
 ;; Integer multiplication.
 (define_insn_reservation "tt_ascalon_d8_imul" 3
-  (and (eq_attr "tune" "tt_ascalon_d8")
+  (and (eq_attr "tune" "tt_ascalon_d8,tt_ascalon_xg")
        (eq_attr "type" "imul"))
   "tt_ascalon_d8_decode,tt_ascalon_d8_mul")
 
@@ -97,116 +99,119 @@ (define_insn_reservation "tt_ascalon_d8_imul" 3
 ;; non-pipelined instructions.  Division is variable cycles so pick a value
 ;; in the middle.
 (define_insn_reservation "tt_ascalon_d8_idiv" 15
-  (and (eq_attr "tune" "tt_ascalon_d8")
+  (and (eq_attr "tune" "tt_ascalon_d8,tt_ascalon_xg")
        (eq_attr "type" "idiv"))
   "tt_ascalon_d8_decode,tt_ascalon_d8_div,tt_ascalon_d8_div*3")
 
 ;; Float addition.
 (define_insn_reservation "tt_ascalon_d8_fadd" 2
-  (and (eq_attr "tune" "tt_ascalon_d8")
+  (and (eq_attr "tune" "tt_ascalon_d8,tt_ascalon_xg")
        (eq_attr "type" "fadd"))
   "tt_ascalon_d8_decode,tt_ascalon_d8_fp")
 
 ;; Float multiplication.
 (define_insn_reservation "tt_ascalon_d8_mul" 3
-  (and (eq_attr "tune" "tt_ascalon_d8")
+  (and (eq_attr "tune" "tt_ascalon_d8,tt_ascalon_xg")
        (eq_attr "type" "fmul"))
   "tt_ascalon_d8_decode,tt_ascalon_d8_fp")
 
 ;; Float FMA.
 (define_insn_reservation "tt_ascalon_d8_float_fma" 3
-  (and (eq_attr "tune" "tt_ascalon_d8")
+  (and (eq_attr "tune" "tt_ascalon_d8,tt_ascalon_xg")
        (eq_attr "type" "fmadd"))
   "tt_ascalon_d8_decode,tt_ascalon_d8_fp")
 
 ;; Float division.
 (define_insn_reservation "tt_ascalon_d8_float_div_half" 6
-  (and (eq_attr "tune" "tt_ascalon_d8")
+  (and (eq_attr "tune" "tt_ascalon_d8,tt_ascalon_xg")
        (and (eq_attr "type" "fdiv,fsqrt")
 	    (eq_attr "mode" "HF")))
   "tt_ascalon_d8_decode,(tt_ascalon_d8_fp0*3 | tt_ascalon_d8_fp1*3)")
 
 (define_insn_reservation "tt_ascalon_d8_float_div_single" 9
-  (and (eq_attr "tune" "tt_ascalon_d8")
+  (and (eq_attr "tune" "tt_ascalon_d8,tt_ascalon_xg")
        (and (eq_attr "type" "fdiv,fsqrt")
 	    (eq_attr "mode" "SF")))
   "tt_ascalon_d8_decode,(tt_ascalon_d8_fp0*3 | tt_ascalon_d8_fp1*3)")
 
 (define_insn_reservation "tt_ascalon_d8_float_div_double" 16
-  (and (eq_attr "tune" "tt_ascalon_d8")
+  (and (eq_attr "tune" "tt_ascalon_d8,tt_ascalon_xg")
        (and (eq_attr "type" "fdiv,fsqrt")
 	    (eq_attr "mode" "DF")))
   "tt_ascalon_d8_decode,(tt_ascalon_d8_fp0*3 | tt_ascalon_d8_fp1*3)")
 
 ;; Popcount and clmul.
 (define_insn_reservation "tt_ascalon_d8_popcount" 1
-  (and (eq_attr "tune" "tt_ascalon_d8")
+  (and (eq_attr "tune" "tt_ascalon_d8,tt_ascalon_xg")
        (eq_attr "type" "cpop,clmul"))
   "tt_ascalon_d8_decode,tt_ascalon_d8_alu")
 
 ;; Vector loads and stores
 (define_insn_reservation "tt_ascalon_d8_vec_load" 5
-  (and (eq_attr "tune" "tt_ascalon_d8")
+  (and (eq_attr "tune" "tt_ascalon_d8,tt_ascalon_xg")
        (eq_attr "type" "vlde,vldm,vldff,vldr"))
   "tt_ascalon_d8_decode,tt_ascalon_d8_ls")
 
 (define_insn_reservation "tt_ascalon_d8_vec_store" 5
-  (and (eq_attr "tune" "tt_ascalon_d8")
+  (and (eq_attr "tune" "tt_ascalon_d8,tt_ascalon_xg")
        (eq_attr "type" "vste,vstm,vstr"))
   "tt_ascalon_d8_decode,tt_ascalon_d8_ls")
 
 (define_insn_reservation "tt_ascalon_d8_vec_load_strided" 16
-  (and (eq_attr "tune" "tt_ascalon_d8")
+  (and (eq_attr "tune" "tt_ascalon_d8,tt_ascalon_xg")
        (eq_attr "type" "vlds"))
   "tt_ascalon_d8_decode,tt_ascalon_d8_ls")
 
 (define_insn_reservation "tt_ascalon_d8_vec_store_strided" 16
-  (and (eq_attr "tune" "tt_ascalon_d8")
+  (and (eq_attr "tune" "tt_ascalon_d8,tt_ascalon_xg")
        (eq_attr "type" "vsts"))
   "tt_ascalon_d8_decode,tt_ascalon_d8_ls")
 
 (define_insn_reservation "tt_ascalon_d8_vec_load_indexed" 16
-  (and (eq_attr "tune" "tt_ascalon_d8")
+  (and (eq_attr "tune" "tt_ascalon_d8,tt_ascalon_xg")
        (eq_attr "type" "vldux,vldox"))
   "tt_ascalon_d8_decode,tt_ascalon_d8_ls")
 
 (define_insn_reservation "tt_ascalon_d8_vec_store_indexed" 16
-  (and (eq_attr "tune" "tt_ascalon_d8")
+  (and (eq_attr "tune" "tt_ascalon_d8,tt_ascalon_xg")
        (eq_attr "type" "vstux,vstox"))
   "tt_ascalon_d8_decode,tt_ascalon_d8_ls")
 
 ;; Vector segment loads/stores.
 (define_insn_reservation "tt_ascalon_d8_vec_loadstore_seg" 11
-  (and (eq_attr "tune" "tt_ascalon_d8")
+  (and (eq_attr "tune" "tt_ascalon_d8,tt_ascalon_xg")
        (eq_attr "type" "vlsegde,vlsegds,vlsegdux,vlsegdox,vlsegdff,\
 			vssegte,vssegts,vssegtux,vssegtox"))
   "tt_ascalon_d8_decode,tt_ascalon_d8_vec")
 
 ;; Regular vector operations and integer comparisons.
 (define_insn_reservation "tt_ascalon_d8_vec_alu_1" 1
-  (and (eq_attr "tune" "tt_ascalon_d8")
+  (and (eq_attr "tune" "tt_ascalon_d8,tt_ascalon_xg")
        (eq_attr "type" "vector,vialu,vicalu,viminmax,vimov,vmov,vfmov,\
 			vandn,vbrev,vbrev8,vrev8,vclz,vctz,vrol,vror"))
   "tt_ascalon_d8_decode,tt_ascalon_d8_vec")
 
 (define_insn_reservation "tt_ascalon_d8_vec_alu_2" 2
-  (and (eq_attr "tune" "tt_ascalon_d8")
+  (and (eq_attr "tune" "tt_ascalon_d8,tt_ascalon_xg")
        (eq_attr "type" "vshift,vsshift,vsalu,vaalu,vext"))
   "tt_ascalon_d8_decode,tt_ascalon_d8_vec")
 
 (define_insn_reservation "tt_ascalon_d8_vec_alu_3" 3
-  (and (eq_attr "tune" "tt_ascalon_d8")
+  (and (eq_attr "tune" "tt_ascalon_d8,tt_ascalon_xg")
        (eq_attr "type" "viwalu,vnshift,vwsll,vicmp"))
   "tt_ascalon_d8_decode,tt_ascalon_d8_vec")
 
 (define_insn_reservation "tt_ascalon_d8_vec_alu_4" 4
-  (and (eq_attr "tune" "tt_ascalon_d8")
+  (and (eq_attr "tune" "tt_ascalon_d8,tt_ascalon_xg")
        (eq_attr "type" "vnclip"))
   "tt_ascalon_d8_decode,tt_ascalon_d8_vec")
 
 ;; Vector float comparison, conversion etc.
 (define_insn_reservation "tt_ascalon_d8_vec_fcmp" 3
-  (and (eq_attr "tune" "tt_ascalon_d8")
+  (and (ior (eq_attr "tune" "tt_ascalon_d8")
+	    (and (eq_attr "tune" "tt_ascalon_xg")
+		 (not (and (eq_attr "type" "vfwcvtitof,vfwcvtftof")
+			   (eq_attr "sew" "32")))))
        (eq_attr "type" "vfrecp,vfminmax,vfcmp,vfsgnj,vfclass,vfcvtitof,\
 			vfcvtftoi,vfwcvtitof,vfwcvtftoi,vfwcvtftof,vfncvtitof,\
 			vfncvtftoi,vfncvtftof,vfncvtbf16,vfwcvtbf16"))
@@ -214,61 +219,81 @@ (define_insn_reservation "tt_ascalon_d8_vec_fcmp" 3
 
 ;; Vector integer multiplication.
 (define_insn_reservation "tt_ascalon_d8_vec_imul" 4
-  (and (eq_attr "tune" "tt_ascalon_d8")
+  (and (eq_attr "tune" "tt_ascalon_d8,tt_ascalon_xg")
        (eq_attr "type" "vimul,viwmul,vimuladd,viwmuladd,vsmul,vclmul,vclmulh,\
 			vghsh,vgmul"))
   "tt_ascalon_d8_decode,tt_ascalon_d8_vec")
 
 ;; Vector float addition.
 (define_insn_reservation "tt_ascalon_d8_vec_fadd" 2
-  (and (eq_attr "tune" "tt_ascalon_d8")
+  (and (ior (eq_attr "tune" "tt_ascalon_d8")
+	    (and (eq_attr "tune" "tt_ascalon_xg")
+		 (not (eq_attr "sew" "64"))
+		 (not (and (eq_attr "type" "vfwalu")
+			   (eq_attr "sew" "32")))))
        (eq_attr "type" "vfalu,vfwalu"))
   "tt_ascalon_d8_decode,tt_ascalon_d8_vec")
 
 ;; Vector float multiplication and FMA.
 (define_insn_reservation "tt_ascalon_d8_vec_fmul" 4
-  (and (eq_attr "tune" "tt_ascalon_d8")
+  (and (ior (eq_attr "tune" "tt_ascalon_d8")
+	    (and (eq_attr "tune" "tt_ascalon_xg")
+		 (not (eq_attr "sew" "64"))
+		 (not (and (eq_attr "type" "vfwmul,vfwmuladd")
+			   (eq_attr "sew" "32")))))
        (eq_attr "type" "vfmul,vfwmul,vfmuladd,vfwmuladd,vfwmaccbf16"))
   "tt_ascalon_d8_decode,tt_ascalon_d8_vec")
 
+;; The global version of Ascalon X (tt-ascalon-xg) has reduced FP64 throughput
+;; compared to Ascalon X in order to meet export restrictions.  Implement the
+;; reduced throughput via an extra vector pipeline stage used only by the
+;; affected instructions.  All other vector instructions are unaffected.
+(define_insn_reservation "tt_ascalon_xg_fp64_vec_insns" 9
+  (and (eq_attr "tune" "tt_ascalon_xg")
+       (ior (and (eq_attr "type" "vfalu,vfmul,vfmuladd")
+		 (eq_attr "sew" "64"))
+	    (and (eq_attr "type" "vfwalu,vfwmul,vfwmuladd,vfwcvtftof,vfwcvtitof")
+		 (eq_attr "sew" "32"))))
+  "tt_ascalon_d8_decode,tt_ascalon_d8_vec,tt_ascalon_xg_fp64_vec")
+
 ;; Vector population count.
 (define_insn_reservation "tt_ascalon_d8_vec_pop" 2
-  (and (eq_attr "tune" "tt_ascalon_d8")
+  (and (eq_attr "tune" "tt_ascalon_d8,tt_ascalon_xg")
        (eq_attr "type" "vcpop"))
   "tt_ascalon_d8_decode,tt_ascalon_d8_vec")
 
 ;; Vector crypto, AES.
 (define_insn_reservation "tt_ascalon_d8_vec_crypto_aes" 3
-  (and (eq_attr "tune" "tt_ascalon_d8")
+  (and (eq_attr "tune" "tt_ascalon_d8,tt_ascalon_xg")
        (eq_attr "type" "crypto,vaesef,vaesem,vaesdf,vaesdm,vaeskf1,vaeskf2,vaesz"))
   "tt_ascalon_d8_decode,tt_ascalon_d8_vec")
 
 ;; Vector SHA.
 (define_insn_reservation "tt_ascalon_d8_vec_crypto_sha" 4
-  (and (eq_attr "tune" "tt_ascalon_d8")
+  (and (eq_attr "tune" "tt_ascalon_d8,tt_ascalon_xg")
        (eq_attr "type" "vsha2ms,vsha2ch,vsha2cl"))
   "tt_ascalon_d8_decode,tt_ascalon_d8_vec")
 
 ;; Vector permute.
 (define_insn_reservation "tt_ascalon_d8_vec_perm_1" 1
-  (and (eq_attr "tune" "tt_ascalon_d8")
+  (and (eq_attr "tune" "tt_ascalon_d8,tt_ascalon_xg")
        (eq_attr "type" "vimerge,vfmerge"))
   "tt_ascalon_d8_decode,tt_ascalon_d8_vec")
 
 (define_insn_reservation "tt_ascalon_d8_vec_perm_3" 3
-  (and (eq_attr "tune" "tt_ascalon_d8")
+  (and (eq_attr "tune" "tt_ascalon_d8,tt_ascalon_xg")
        (eq_attr "type" "vislide1up,vislide1down,vfslide1up,vfslide1down,\
 			vgather,vcompress"))
   "tt_ascalon_d8_decode,tt_ascalon_d8_vec")
 
 (define_insn_reservation "tt_ascalon_d8_vec_perm_4" 4
-  (and (eq_attr "tune" "tt_ascalon_d8")
+  (and (eq_attr "tune" "tt_ascalon_d8,tt_ascalon_xg")
        (eq_attr "type" "vslideup,vslidedown"))
   "tt_ascalon_d8_decode,tt_ascalon_d8_vec")
 
 ;; Vector reduction.
 (define_insn_reservation "tt_ascalon_d8_vec_reduction" 4
-  (and (eq_attr "tune" "tt_ascalon_d8")
+  (and (eq_attr "tune" "tt_ascalon_d8,tt_ascalon_xg")
        (eq_attr "type" "vired,viwred,vfredu,vfwredu"))
   "tt_ascalon_d8_decode,tt_ascalon_d8_vec")
 
@@ -277,82 +302,82 @@ (define_insn_reservation "tt_ascalon_d8_vec_reduction" 4
 ;; riscv_sched_adjust_cost for larger vectors.
 ;; NOTE: The latency depends on the SEW, we should be checking it
 (define_insn_reservation "tt_ascalon_d8_vec_ordered_reduction" 10
-  (and (eq_attr "tune" "tt_ascalon_d8")
+  (and (eq_attr "tune" "tt_ascalon_d8,tt_ascalon_xg")
        (eq_attr "type" "vfredo,vfwredo"))
   "tt_ascalon_d8_decode,(tt_ascalon_d8_vec0*3 | tt_ascalon_d8_vec1*3)")
 
 ;; Vector integer division
 (define_insn_reservation "tt_ascalon_d8_vec_idiv_byte" 16
-  (and (eq_attr "tune" "tt_ascalon_d8")
+  (and (eq_attr "tune" "tt_ascalon_d8,tt_ascalon_xg")
        (eq_attr "type" "vidiv")
        (eq_attr "sew" "8"))
   "tt_ascalon_d8_decode,(tt_ascalon_d8_vec0*3 | tt_ascalon_d8_vec1*3)")
 
 (define_insn_reservation "tt_ascalon_d8_vec_idiv_half" 16
-  (and (eq_attr "tune" "tt_ascalon_d8")
+  (and (eq_attr "tune" "tt_ascalon_d8,tt_ascalon_xg")
        (eq_attr "type" "vidiv")
        (eq_attr "sew" "16"))
   "tt_ascalon_d8_decode,(tt_ascalon_d8_vec0*3 | tt_ascalon_d8_vec1*3)")
 
 (define_insn_reservation "tt_ascalon_d8_vec_idiv_single" 13
-  (and (eq_attr "tune" "tt_ascalon_d8")
+  (and (eq_attr "tune" "tt_ascalon_d8,tt_ascalon_xg")
        (eq_attr "type" "vidiv")
        (eq_attr "sew" "32"))
   "tt_ascalon_d8_decode,(tt_ascalon_d8_vec0*3 | tt_ascalon_d8_vec1*3)")
 
 (define_insn_reservation "tt_ascalon_d8_vec_idiv_double" 20
-  (and (eq_attr "tune" "tt_ascalon_d8")
+  (and (eq_attr "tune" "tt_ascalon_d8,tt_ascalon_xg")
        (eq_attr "type" "vidiv")
        (eq_attr "sew" "64"))
   "tt_ascalon_d8_decode,(tt_ascalon_d8_vec0*3 | tt_ascalon_d8_vec1*3)")
 
 ;; Vector float divisions and sqrt
 (define_insn_reservation "tt_ascalon_d8_vec_float_divsqrt_half" 11
-  (and (eq_attr "tune" "tt_ascalon_d8")
+  (and (eq_attr "tune" "tt_ascalon_d8,tt_ascalon_xg")
        (eq_attr "type" "vfdiv,vfsqrt")
        (eq_attr "sew" "16"))
   "tt_ascalon_d8_decode,(tt_ascalon_d8_vec0*3 | tt_ascalon_d8_vec1*3)")
 
 (define_insn_reservation "tt_ascalon_d8_vec_float_divsqrt_single" 10
-  (and (eq_attr "tune" "tt_ascalon_d8")
+  (and (eq_attr "tune" "tt_ascalon_d8,tt_ascalon_xg")
        (eq_attr "type" "vfdiv,vfsqrt")
        (eq_attr "sew" "32"))
   "tt_ascalon_d8_decode,(tt_ascalon_d8_vec0*3 | tt_ascalon_d8_vec1*3)")
 
 (define_insn_reservation "tt_ascalon_d8_vec_float_divsqrt_double" 17
-  (and (eq_attr "tune" "tt_ascalon_d8")
+  (and (eq_attr "tune" "tt_ascalon_d8,tt_ascalon_xg")
        (eq_attr "type" "vfdiv,vfsqrt")
        (eq_attr "sew" "64"))
   "tt_ascalon_d8_decode,(tt_ascalon_d8_vec0*3 | tt_ascalon_d8_vec1*3)")
 
 ;; Vector mask operations.
 (define_insn_reservation "tt_ascalon_d8_vec_mask" 3
-  (and (eq_attr "tune" "tt_ascalon_d8")
+  (and (eq_attr "tune" "tt_ascalon_d8,tt_ascalon_xg")
        (eq_attr "type" "vmalu,vmpop,vmffs,vmsfs,vmiota,vmidx,vimovvx,vimovxv,\
 			vfmovvf,vfmovfv"))
   "tt_ascalon_d8_decode,tt_ascalon_d8_vec")
 
 ;; Vector vsetvl.
 (define_insn_reservation "tt_ascalon_d8_vec_vesetvl" 1
-  (and (eq_attr "tune" "tt_ascalon_d8")
+  (and (eq_attr "tune" "tt_ascalon_d8,tt_ascalon_xg")
        (eq_attr "type" "vsetvl,vsetvl_pre"))
   "tt_ascalon_d8_decode,tt_ascalon_d8_vec")
 
 ;; Vector rounding mode setters, assume pipeline barrier.
 (define_insn_reservation "tt_ascalon_d8_vec_setrm" 20
-  (and (eq_attr "tune" "tt_ascalon_d8")
+  (and (eq_attr "tune" "tt_ascalon_d8,tt_ascalon_xg")
        (eq_attr "type" "wrvxrm,wrfrm"))
   "tt_ascalon_d8_decode,tt_ascalon_d8_vec*3")
 
 ;; Vector read vlen/vlenb.
 (define_insn_reservation "tt_ascalon_d8_vec_readlen" 4
-  (and (eq_attr "tune" "tt_ascalon_d8")
+  (and (eq_attr "tune" "tt_ascalon_d8,tt_ascalon_xg")
        (eq_attr "type" "rdvlenb,rdvl"))
   "tt_ascalon_d8_decode,tt_ascalon_d8_vec")
 
 ;; Vector unknown.
 (define_insn_reservation "tt_ascalon_d8_vec_unknown" 1
-  (and (eq_attr "tune" "tt_ascalon_d8")
+  (and (eq_attr "tune" "tt_ascalon_d8,tt_ascalon_xg")
        (eq_attr "type" "sf_vc,sf_vc_se,sf_vqmacc,sf_vfnrclip,\
 			vsm3me,vsm4r,vsm4k,vsm3c,ghost,\
 			mfc,mtc,rdfrm"))
diff --git a/gcc/doc/riscv-mcpu.texi b/gcc/doc/riscv-mcpu.texi
index 6e3c2adc2fb..9a5475ebb17 100644
--- a/gcc/doc/riscv-mcpu.texi
+++ b/gcc/doc/riscv-mcpu.texi
@@ -64,6 +64,8 @@ by particular CPU name.  Permissible values for this option are:
 
 @samp{tt-ascalon-x},
 
+@samp{tt-ascalon-xg},
+
 @samp{xiangshan-nanhu},
 
 @samp{xiangshan-kunminghu},
diff --git a/gcc/doc/riscv-mtune.texi b/gcc/doc/riscv-mtune.texi
index 101d81d3709..9b167ed9018 100644
--- a/gcc/doc/riscv-mtune.texi
+++ b/gcc/doc/riscv-mtune.texi
@@ -32,6 +32,8 @@ particular CPU name.  Permissible values for this option are:
 
 @samp{tt-ascalon-x},
 
+@samp{tt-ascalon-xg},
+
 @samp{thead-c906},
 
 @samp{xt-c908},
-- 
2.43.0