Re: [PATCH v5 13/18] RISC-V: Add POSTINDEX_LD macro-fusion recognition

On 8/14/2026 12:00 AM, Jin Ma wrote:
> Recognize a scalar integer or floating-point load followed by a
> non-word ADDI-type in-place update of its base register.  Reuse the
> indexed-memory helper shared with the pre-index rules and accept either
> load-destination relationship.
>
> Leave the fusion disabled by default and XFAIL its positive dump
> checks until a CPU enables it.
>
> gcc/ChangeLog:
>
> 	* config/riscv/riscv-fusion.cc (riscv_fuse_postindex_ld): New
> 	function.
> 	(riscv_fusion_table): Add RISCV_FUSE_POSTINDEX_LD.
> 	* config/riscv/riscv-protos.h (enum riscv_fusion_pairs): Add
> 	RISCV_FUSE_POSTINDEX_LD.
>
> gcc/testsuite/ChangeLog:
>
> 	* gcc.target/riscv/fusion-load-dest-equal-rtl-postindex.c: New test.
> 	* gcc.target/riscv/fusion-postindex-ldst.c: Likewise.
OK once prereqs are approved.

Thanks,
jeff