[PATCH 0/3] middle-end: three independent correctness fixes

Three unrelated middle-end fixes that were found together.  Patches 2 and
3 both touch gcc/expmed.cc, but in unrelated functions; each applies to
trunk on its own and any of the three may be dropped.  They are sent as
one series only because they were tested as one.

  1. tree-ssa-loop-im.cc: the guard that keeps a shift with an
     out-of-range count from being speculatively hoisted tests the
     opposite of what its comment describes, so it pins the well-defined
     shifts instead, along with every invariant computed from them.

  2. expmed.cc: expand_divmod's memory of the last division it expanded
     is a static that is never reset, so a function's code depends on
     what was expanded before it in the same translation unit.  Two
     character-for-character identical functions compile differently,
     and reordering them in the source changes the output.  The reset
     goes in prepare_function_start, which already does the same for
     expr.cc's bitint_extended.

  3. store_fixed_bit_field_1: a bit-field store that fills its storage
     unit entirely still reads the destination first.  The read is dead
     for ordinary memory, but a volatile read cannot be deleted, so a
     write-only store to a misaligned volatile object emits a spurious
     load of it -- wrong code for an I/O register with read side effects
     (read-to-clear, FIFO pop, W1C).  PR71048.

Testing.  Bootstrapped on x86_64-pc-linux-gnu at trunk 7f549ea2b47 with
the stage2/stage3 comparison successful, and a full make check run:
227924 gcc and 278399 g++ expected passes, 20109 libstdc++, with 112
unexpected results.  Every one of those 112 is pre-existing: the
compiler was rebuilt with the three patches reverted and each was
re-run, including the whole gcc.dg/guality suite, whose 95 unexpected
results (72 FAIL, 23 XPASS) form a set identical to the patched run.
The remainder are 4 g++.dg/modules xtreme-header at -std=c++29, 4
gcc.target/i386 (pr115102, shift-gf2p8affine-2, xchg-4 x2), 3
g++.dg/tree-ssa/vec-narrow-minmax-2.C, 3 libgomp alloc-pinned execution
tests (this machine's locked-memory limit), 1 analyzer excess-errors, 1
g++ guality under LTO, and 1 i386 XPASS -- all of them failing
identically without the series.

The two ARM testcases were additionally checked with a compile-only
arm-none-eabi cross (make all-gcc, --without-headers --with-newlib
--disable-multilib, so no libgcc or newlib) over gcc.target/arm/arm.exp.
In that configuration 383 results are unresolved, 385 unsupported and 69
fail for want of a target library, identically with and without the
series; the only change in the fail set is the two new tests, 1364 ->
1366 passes and 71 -> 69 failures.

Each test was checked to discriminate, by reverting the code with the
tests kept: the lim2 dump then moves no statements instead of three,
divmod-order-1.c emits one bl __aeabi_idivmod instead of two, and
pr71048.c emits four or five loads of the volatile destination instead
of none.  For pr71048.c that was checked on arm1176jzf-s, armv7-a,
cortex-m4 and armv5te, so that the test is not vacuous on the
configurations that allow unaligned access.

The series also applies cleanly to 968c8e7dd70.

These patches were prepared with the assistance of an AI coding tool,
recorded per-patch with Assisted-by:.  I reviewed and verified every
line, and take responsibility for the result.

Dominic P (3):
  tree-optimization: hoist shifts by an in-range constant count
  expmed: do not carry last_div_const between functions
  middle-end: don't read a memory destination fully overwritten by a
    bit-field store [PR71048]

 gcc/expmed.cc                                 | 18 ++++++++++++-
 gcc/expmed.h                                  |  4 +++
 gcc/function.cc                               |  4 +++
 .../gcc.dg/tree-ssa/loop-im-shift-1.c         | 23 +++++++++++++++++
 gcc/testsuite/gcc.target/arm/divmod-order-1.c | 25 +++++++++++++++++++
 gcc/testsuite/gcc.target/arm/pr71048.c        | 19 ++++++++++++++
 gcc/tree-ssa-loop-im.cc                       |  2 +-
 7 files changed, 93 insertions(+), 2 deletions(-)
 create mode 100644 gcc/testsuite/gcc.dg/tree-ssa/loop-im-shift-1.c
 create mode 100644 gcc/testsuite/gcc.target/arm/divmod-order-1.c
 create mode 100644 gcc/testsuite/gcc.target/arm/pr71048.c

-- 
2.55.0