[committed][RISC-V] Adjust more RISC-V tests

Jeffrey Law <[email protected]>
Newsgroups gmane.comp.gcc.patches
Message-ID <[email protected]> 
I cobbled this together many weeks ago, but never got around to pushing it.

Some generic change (I forget which) made subtle changes in the 
generated output for a variety of RISC-V tests.  I reviewd these and 
concluded the changes were sensible from a code generation standpoint, 
so I just adjusted the expected outputs.

Pushed to the trunk.

jeff
riscv-tests-2.patch (text/plain, 13.5 KB) 
commit 01237555768d0eea9355ac83723cc2d74b483d7a
Author: Jeff Law <[email protected]>
Date:   Tue Aug 18 09:26:52 2026 -0600

    [RISC-V] Adjust more RISC-V tests
    
    I cobbled this together many weeks ago, but never got around to pushing it.
    
    Some generic change (I forget which) made subtle changes in the generated
    output for a variety of RISC-V tests.  I reviewd these and concluded the
    changes were sensible from a code generation standpoint, so I just adjusted the
    expected outputs.
    
    Pushed to the trunk.
    
    gcc/testsuite
            * gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-3-s16.c: Adjust
            expected output.
            * gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-3-s32.c: Likewise.
            * gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-3-s64.c: Likewise.
            * gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-3-s8.c: Likewise.
            * gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-4-s16.c: Likewise.
            * gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-4-s32.c: Likewise.
            * gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-4-s64.c: Likewise.
            * gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-4-s8.c: Likewise.
            * gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add_imm-1-i16.c: Likewise.
            * gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add_imm-1-i32.c: Likewise.
            * gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add_imm-1-i64.c: Likewise.
            * gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add_imm-1-i8.c: Likewise.
            * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_trunc-1-u8.c: Likewise.
            * gcc.target/riscv/rvv/base/float-point-dynamic-frm-12.c: Likewise.
            * gcc.target/riscv/rvv/base/float-point-dynamic-frm-13.c: Likewise.

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-3-s16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-3-s16.c
index de121556891..3d2aed0636c 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-3-s16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-3-s16.c
@@ -5,6 +5,5 @@
 
 DEF_VEC_SAT_S_ADD_FMT_3(int16_t, uint16_t, INT16_MIN, INT16_MAX)
 
-/* { dg-final { scan-tree-dump-times ".SAT_ADD " 1 "optimized" { target { no-opts "-O2" } } } } */
-/* { dg-final { scan-tree-dump-times ".SAT_ADD " 2 "optimized" { target { no-opts "-O3" } } } } */
+/* { dg-final { scan-tree-dump-times ".SAT_ADD " 2 "optimized" } } */
 /* { dg-final { scan-assembler-times {vsadd\.vv} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-3-s32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-3-s32.c
index 187c8b1f62f..17511a41e74 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-3-s32.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-3-s32.c
@@ -5,6 +5,5 @@
 
 DEF_VEC_SAT_S_ADD_FMT_3(int32_t, uint32_t, INT32_MIN, INT32_MAX)
 
-/* { dg-final { scan-tree-dump-times ".SAT_ADD " 1 "optimized" { target { no-opts "-O2" } } } } */
-/* { dg-final { scan-tree-dump-times ".SAT_ADD " 2 "optimized" { target { no-opts "-O3" } } } } */
+/* { dg-final { scan-tree-dump-times ".SAT_ADD " 2 "optimized" } } */
 /* { dg-final { scan-assembler-times {vsadd\.vv} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-3-s64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-3-s64.c
index 61ca265125a..b38a6c5c6b1 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-3-s64.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-3-s64.c
@@ -5,6 +5,5 @@
 
 DEF_VEC_SAT_S_ADD_FMT_3(int64_t, uint64_t, INT64_MIN, INT64_MAX)
 
-/* { dg-final { scan-tree-dump-times ".SAT_ADD " 1 "optimized" { target { no-opts "-O2" } } } } */
-/* { dg-final { scan-tree-dump-times ".SAT_ADD " 2 "optimized" { target { no-opts "-O3" } } } } */
+/* { dg-final { scan-tree-dump-times ".SAT_ADD " 2 "optimized" } } */
 /* { dg-final { scan-assembler-times {vsadd\.vv} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-3-s8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-3-s8.c
index eaffe5f4fd1..83891b649fe 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-3-s8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-3-s8.c
@@ -5,6 +5,5 @@
 
 DEF_VEC_SAT_S_ADD_FMT_3(int8_t, uint8_t, INT8_MIN, INT8_MAX)
 
-/* { dg-final { scan-tree-dump-times ".SAT_ADD " 1 "optimized" { target { no-opts "-O2" } } } } */
-/* { dg-final { scan-tree-dump-times ".SAT_ADD " 2 "optimized" { target { no-opts "-O3" } } } } */
+/* { dg-final { scan-tree-dump-times ".SAT_ADD " 2 "optimized" } } */
 /* { dg-final { scan-assembler-times {vsadd\.vv} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-4-s16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-4-s16.c
index 9808fc5be1e..12de03c5909 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-4-s16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-4-s16.c
@@ -5,6 +5,5 @@
 
 DEF_VEC_SAT_S_ADD_FMT_4(int16_t, uint16_t, INT16_MIN, INT16_MAX)
 
-/* { dg-final { scan-tree-dump-times ".SAT_ADD " 1 "optimized" { target { no-opts "-O2" } } } } */
-/* { dg-final { scan-tree-dump-times ".SAT_ADD " 2 "optimized" { target { no-opts "-O3" } } } } */
+/* { dg-final { scan-tree-dump-times ".SAT_ADD " 2 "optimized" } } */
 /* { dg-final { scan-assembler-times {vsadd\.vv} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-4-s32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-4-s32.c
index ab691cbc2c7..625965df65b 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-4-s32.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-4-s32.c
@@ -5,6 +5,5 @@
 
 DEF_VEC_SAT_S_ADD_FMT_4(int32_t, uint32_t, INT32_MIN, INT32_MAX)
 
-/* { dg-final { scan-tree-dump-times ".SAT_ADD " 1 "optimized" { target { no-opts "-O2" } } } } */
-/* { dg-final { scan-tree-dump-times ".SAT_ADD " 2 "optimized" { target { no-opts "-O3" } } } } */
+/* { dg-final { scan-tree-dump-times ".SAT_ADD " 2 "optimized" } } */
 /* { dg-final { scan-assembler-times {vsadd\.vv} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-4-s64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-4-s64.c
index 30326886a80..6efbb2c1d0b 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-4-s64.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-4-s64.c
@@ -5,6 +5,5 @@
 
 DEF_VEC_SAT_S_ADD_FMT_4(int64_t, uint64_t, INT64_MIN, INT64_MAX)
 
-/* { dg-final { scan-tree-dump-times ".SAT_ADD " 1 "optimized" { target { no-opts "-O2" } } } } */
-/* { dg-final { scan-tree-dump-times ".SAT_ADD " 2 "optimized" { target { no-opts "-O3" } } } } */
+/* { dg-final { scan-tree-dump-times ".SAT_ADD " 2 "optimized" } } */
 /* { dg-final { scan-assembler-times {vsadd\.vv} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-4-s8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-4-s8.c
index 928b4b66867..52736fa1eac 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-4-s8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-4-s8.c
@@ -5,6 +5,5 @@
 
 DEF_VEC_SAT_S_ADD_FMT_4(int8_t, uint8_t, INT8_MIN, INT8_MAX)
 
-/* { dg-final { scan-tree-dump-times ".SAT_ADD " 1 "optimized" { target { no-opts "-O2" } } } } */
-/* { dg-final { scan-tree-dump-times ".SAT_ADD " 2 "optimized" { target { no-opts "-O3" } } } } */
+/* { dg-final { scan-tree-dump-times ".SAT_ADD " 2 "optimized" } } */
 /* { dg-final { scan-assembler-times {vsadd\.vv} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add_imm-1-i16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add_imm-1-i16.c
index 396c741d321..fd152a066ad 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add_imm-1-i16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add_imm-1-i16.c
@@ -5,6 +5,5 @@
 
 DEF_VEC_SAT_S_ADD_IMM_FMT_1(0, int16_t, uint16_t, 9, INT16_MIN, INT16_MAX)
 
-/* { dg-final { scan-tree-dump-times ".SAT_ADD " 1 "optimized" { target { no-opts "-O2" } } } } */
-/* { dg-final { scan-tree-dump-times ".SAT_ADD " 2 "optimized" { target { no-opts "-O3" } } } } */
+/* { dg-final { scan-tree-dump-times ".SAT_ADD " 2 "optimized" } } */
 /* { dg-final { scan-assembler-times {vsadd\.vi} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add_imm-1-i32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add_imm-1-i32.c
index da9e53879d1..98a23b91e62 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add_imm-1-i32.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add_imm-1-i32.c
@@ -5,6 +5,5 @@
 
 DEF_VEC_SAT_S_ADD_IMM_FMT_1(0, int32_t, uint32_t, 9, INT32_MIN, INT32_MAX)
 
-/* { dg-final { scan-tree-dump-times ".SAT_ADD " 1 "optimized" { target { no-opts "-O2" } } } } */
-/* { dg-final { scan-tree-dump-times ".SAT_ADD " 2 "optimized" { target { no-opts "-O3" } } } } */
+/* { dg-final { scan-tree-dump-times ".SAT_ADD " 2 "optimized" } } */
 /* { dg-final { scan-assembler-times {vsadd\.vi} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add_imm-1-i64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add_imm-1-i64.c
index e9af1a159df..18e8cd69d5f 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add_imm-1-i64.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add_imm-1-i64.c
@@ -5,6 +5,5 @@
 
 DEF_VEC_SAT_S_ADD_IMM_FMT_1(0, int64_t, uint64_t, 9, INT64_MIN, INT64_MAX)
 
-/* { dg-final { scan-tree-dump-times ".SAT_ADD " 1 "optimized" { target { no-opts "-O2" } } } } */
-/* { dg-final { scan-tree-dump-times ".SAT_ADD " 2 "optimized" { target { no-opts "-O3" } } } } */
+/* { dg-final { scan-tree-dump-times ".SAT_ADD " 2 "optimized" } } */
 /* { dg-final { scan-assembler-times {vsadd\.vi} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add_imm-1-i8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add_imm-1-i8.c
index 66b9d7f4a2d..1248a8780b7 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add_imm-1-i8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add_imm-1-i8.c
@@ -5,6 +5,5 @@
 
 DEF_VEC_SAT_S_ADD_IMM_FMT_1(0, int8_t, uint8_t, 9, INT8_MIN, INT8_MAX)
 
-/* { dg-final { scan-tree-dump-times ".SAT_ADD " 1 "optimized" { target { no-opts "-O2" } } } } */
-/* { dg-final { scan-tree-dump-times ".SAT_ADD " 2 "optimized" { target { no-opts "-O3" } } } } */
+/* { dg-final { scan-tree-dump-times ".SAT_ADD " 2 "optimized" } } */
 /* { dg-final { scan-assembler-times {vsadd\.vi} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_trunc-1-u8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_trunc-1-u8.c
index 492c3168216..c5947d92fe9 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_trunc-1-u8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_trunc-1-u8.c
@@ -5,6 +5,7 @@
 
 DEF_VEC_SAT_U_SUB_TRUNC_FMT_1(uint8_t, uint16_t)
 
-/* { dg-final { scan-tree-dump-times ".SAT_SUB " 1 "optimized" } } */
+/* { dg-final { scan-tree-dump-times ".SAT_SUB " 2 "optimized" { target { no-opts "-O2" } } } } */
+/* { dg-final { scan-tree-dump-times ".SAT_SUB " 1 "optimized" { target { no-opts "-O3" } } } } */
 /* { dg-final { scan-assembler-times {vssubu\.vv} 1 } } */
 /* { dg-final { scan-assembler-times {vnsrl\.wi} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-12.c b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-12.c
index 99b2b3befe8..5732f4c772c 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-12.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-12.c
@@ -22,8 +22,8 @@ test_float_point_dynamic_frm (vfloat32m1_t op1, vfloat32m1_t op2,
   return result;
 }
 
-/* { dg-final { scan-assembler-times {vfadd\.v[vf]\s+v[0-9]+,\s*v[0-9]+,\s*[fav]+[0-9]+} 4 } } */
+/* { dg-final { scan-assembler-times {vfadd\.v[vf]\s+v[0-9]+,\s*v[0-9]+,\s*[fav]+[0-9]+} 3 } } */
 /* { dg-final { scan-assembler-times {frrm\s+[axs][0-9]+} 1 } } */
 /* { dg-final { scan-assembler-times {fsrmi\s+[01234]} 2 } } */
-/* { dg-final { scan-assembler-times {fsrm\s+[axs][0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {fsrm\s+[axs][0-9]+} 1 } } */
 /* { dg-final { scan-assembler-not {fsrmi\s+[axs][0-9]+,\s*[01234]} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-13.c b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-13.c
index 57cad049e0c..01a949e805f 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-13.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-13.c
@@ -22,8 +22,8 @@ test_float_point_dynamic_frm (vfloat32m1_t op1, vfloat32m1_t op2,
   return result;
 }
 
-/* { dg-final { scan-assembler-times {vfadd\.v[vf]\s+v[0-9]+,\s*v[0-9]+,\s*[fav]+[0-9]+} 4 } } */
+/* { dg-final { scan-assembler-times {vfadd\.v[vf]\s+v[0-9]+,\s*v[0-9]+,\s*[fav]+[0-9]+} 3 } } */
 /* { dg-final { scan-assembler-times {frrm\s+[axs][0-9]+} 1 } } */
-/* { dg-final { scan-assembler-times {fsrm\s+[axs][0-9]+} 3 } } */
-/* { dg-final { scan-assembler-times {fsrmi\s+[01234]} 3 } } */
+/* { dg-final { scan-assembler-times {fsrm\s+[axs][0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {fsrmi\s+[01234]} 2 } } */
 /* { dg-final { scan-assembler-not {fsrmi\s+[axs][0-9]+,\s*[01234]} } } */
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