[PATCH][PR target/126803] RISC-V: GCC fails to process <riscv_vector.h> when targeting the valid zve32f_zvl256b ISA combination in C++.
Milan Tripkovic <[email protected]>
| Newsgroups | gmane.comp.gcc.patches |
|---|---|
| Message-ID | <AM6PR08MB4280CBD0610182CB1F4D9856A9A52@AM6PR08MB4280.eurprd08.prod.outlook.com> |
This patch implementing TARGET_COMP_TYPE_ATTRIBUTES to compare "RVV type" and "RVV sizeless type" and prevent the C++ frontend from treating them as identical, fixing the "ambiguating new declaration" error. Suggested by: Zhongyao Chen <[email protected]> 2026-08-19 Milan Tripkovic <[email protected]> gcc/ChangeLog: * config/riscv/riscv.cc (riscv_comp_type_attributes): New function. (TARGET_COMP_TYPE_ATTRIBUTES): Define. gcc/testsuite/ChangeLog: * g++.target/riscv/pr126803.C: New test. CONFIDENTIALITY: The contents of this e-mail are confidential and intended only for the above addressee(s). If you are not the intended recipient, or the person responsible for delivering it to the intended recipient, copying or delivering it to anyone else or using it in any unauthorized manner is prohibited and may be unlawful. If you receive this e-mail by mistake, please notify the sender and the systems administrator at [email protected] immediately.
0001-126803.patch.txt
(text/plain, 2 KB)
---
gcc/config/riscv/riscv.cc | 25 +++++++++++++++++++++++
gcc/testsuite/g++.target/riscv/pr126803.C | 4 ++++
2 files changed, 29 insertions(+)
create mode 100644 gcc/testsuite/g++.target/riscv/pr126803.C
diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index a2a51c019ec..115333a66b7 100644
--- a/gcc/config/riscv/riscv.cc
+++ b/gcc/config/riscv/riscv.cc
@@ -12887,6 +12887,28 @@ riscv_set_current_function (tree decl)
riscv_save_restore_target_globals (new_tree);
}
+/* Implement TARGET_COMP_TYPE_ATTRIBUTES. */
+static int
+riscv_comp_type_attributes (const_tree type1, const_tree type2)
+{
+ auto check_attr = [&](const char *name)
+ {
+ tree attr1 = lookup_attribute (name, TYPE_ATTRIBUTES (type1));
+ tree attr2 = lookup_attribute (name, TYPE_ATTRIBUTES (type2));
+ if (!attr1 && !attr2)
+ return true;
+
+ return attr1 && attr2 && attribute_value_equal (attr1, attr2);
+ };
+
+ if (!check_attr ("RVV type"))
+ return 0;
+ if (!check_attr ("RVV sizeless type"))
+ return 0;
+
+ return 1;
+}
+
/* Implement TARGET_MERGE_DECL_ATTRIBUTES. */
static tree
riscv_merge_decl_attributes (tree olddecl, tree newdecl)
@@ -16834,6 +16856,9 @@ riscv_memtag_tag_bitsize ()
#undef TARGET_CONSTANT_ALIGNMENT
#define TARGET_CONSTANT_ALIGNMENT riscv_constant_alignment
+#undef TARGET_COMP_TYPE_ATTRIBUTES
+#define TARGET_COMP_TYPE_ATTRIBUTES riscv_comp_type_attributes
+
#undef TARGET_MERGE_DECL_ATTRIBUTES
#define TARGET_MERGE_DECL_ATTRIBUTES riscv_merge_decl_attributes
diff --git a/gcc/testsuite/g++.target/riscv/pr126803.C b/gcc/testsuite/g++.target/riscv/pr126803.C
new file mode 100644
index 00000000000..2c3e1c983dd
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/pr126803.C
@@ -0,0 +1,4 @@
+/* { dg-do compile } */
+/* { dg-options "-std=c++17 -march=rv64imafc_zve32f_zvl256b -mabi=lp64f" } */
+#include <riscv_vector.h>
+vfloat32m1_t identity(vfloat32m1_t value) { return value; }
\ No newline at end of file
--
2.34.1