Re: [PATCH][v2] aarch64: implement ctz2 for the Advanced SIMD byte and halfword modes

Hi Kyrill,

> Reversing the bits of an element turns its trailing zeros into leading
> ones, so a count of trailing zeros is a bit reversal followed by a CLZ.
> ctz<mode>2 only covered V2SI and V4SI, so the byte and halfword loops were
> expanded by the middle end into the generic negate/and/clz/subtract
> sequence, which needs two vector constants as well as four instructions.
>
> RBIT reverses the bits within each byte, so a byte element needs nothing
> else and a halfword element needs REV16 to put its two bytes in the
> opposite order.  That is the same shape the V2SI and V4SI expander already
> had, so fold all of them into one expander over VDQ_BHSI and give
> bitreverse<mode>2 the wider modes it builds on.

Looks good - OK.

Cheers,
Wilco