Instruction field constraints within igen

Hi,

I am trying to understand how to make igen correctly deal with constraints
between instruction fields.  I will firstly provide an example and then I will 
explain my problem.  The following igen file describes two instructions which
both have the constraint that the RT field must match the RS field.

:option:32::insn-specifying-widths:true 

000000,5.RS,5.RT=RS,5.RD,00000,100000:SPECIAL:32::INSN1
"insn1"
{
}

100000,5.RS,5.RT=RS,5.RD,00000,100000:SPECIAL:32::INSN2
"insn2"
{
}

:internal::::illegal:
{
}


If the igen file is built using the following igen command line and decoder
file:

igen -F 32 -N 0 -B 32 -H 31  -i test.igen -o mips.dc -P tmp_ -x  -d idecode.c

>> mips.dc <<<
# most instructions
# ------ options ------ : Fst : Lst : ff : fl : fe : word : --- fmt --- : model ...
# { : mask : value : word }

# Top level - create a very big switch statement.

  padded-switch,combine :  31 :  26 :    :    :    :      :             :

  switch,combine        :   5 :   0 :    :    :    :      :             :

  switch,combine        :  20 :  16 :    :    :    :      :             :

  switch,combine        :  25 :  21 :    :    :    :      :             :

  switch,combine        :  10 :   6 :    :    :    :      :             :


I get the following idecode_issue function generated:


INLINE_IDECODE\
(tmp_instruction_address)
tmp_idecode_issue (SIM_DESC sd,
                   tmp_instruction_word instruction_0,
                   tmp_instruction_address cia)
{
  tmp_instruction_address nia;
  switch (EXTRACTED32 (instruction_0, 31, 31))
    {
    case 0:
      {
        nia =tmp_semantic_INSN1_SPECIAL (sd, instruction_0, cia);
        break;
      }
    case 1:
      {
        nia =tmp_semantic_INSN2_SPECIAL (sd, instruction_0, cia);
        break;
      }
    default:
      sim_engine_abort (SD, CPU, cia, "Internal error - bad switch generated");
      nia =NULL_CIA;
      break;
    }
  return nia;}


What you can notice is that there is no checking of the RT=RS constraint
within the decoder.  I was wondering if anyone could tell me if there is
anything I am going incorrectly here?

Many thanks,


Andrew

Andrew Bennett
Software Design Engineer, MIPS Processor IP
Imagination Technologies Limited
t: +44 (0)113 2429814
www.imgtec.com