read target register to decide breakpoint size

I'm still working on RISC-V support for gdb. Any given RISC-V core may
support a compressed instruction set (2 bytes per instruction as
opposed to 4). There are corresponding 2-byte and 4-byte breakpoint
instructions. On cores that support the compressed instruction set it
is safe to just always use the 2-byte version, and there is a register
I can read to tell me whether the compressed instruction set is
supported. What I would like to do is read (and cache) that register
when breakpoint size is determined. That seems more robust than making
a decision based on ELF info, which may not reflect what is actually
being executed.

Is that a good idea? Are there examples of operations that read target
registers to complete?

Thank you,
Tim