(unknown)

Ramana Radhakrishnan <[email protected]>
Newsgroups gmane.linux.ports.arm.kernel,gmane.comp.lib.glibc.alpha,gmane.comp.gdb.devel
Message-ID <CAJA7tRbYgrD-Y7Em6Fcybv3xxCUnJjP8vgjMYhn+81Ns9YbsjA@mail.gmail.com> 
>
> By the way, how is this implemented?  Some of them overlap existing
> callee-saved registers.


The AArch64 PCS requires that only the bottom 64 bits of SIMD
registers (v8-v15) are callee-saved. The top 64 bits of the current
Advanced SIMD registers are the responsibility of the caller. This
naturally extends to SVE.


Ramana
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