Tagged registers and memory

I work with a research CPU architecture (CHERI) that adds 1-bit tags to
certain CPU registers as well as in memory.  CHERI currently comes in two
flavors, but the main one involves 128-bit registers that have a 1-bit tag
(kind of like the 'nat' bits on ia64 GPRs), so you could think of them as
really being 129 bit registers.  In addition, memory for a CHERI CPU also
stores 1-bit tags for each aligned 128-bit word.

Currently to support this in GDB I have a special pseudo-register
($cap_valid) that holds a bit mask of the tags for the capability registers
in the CHERI version of MIPS (kind of like the ar.nat register from ia64
that held a bitmask of the GPR nat bits) and I don't handle tags in memory.
When displaying these registers I just display the 128-bit value and not the
tag.

However, I would like to be able to deal with the registers as 129 bit
registers with a 1 byte tag field (they are already split up into a structure
in my XML feature description that I'm using).  I would also like to
eventually be able to deal with tags in memory and some way to display them
at least initially.  I have more work to do to deal with how to store
tags in core dumps and how ptrace will handle them etc., but I can figure
those parts out, it's the GDB parts that I could use some suggestions on
how best to model this.

The current patchset relative to GDB 8.2 can be found here.  I haven't
made any push to upstream it simply because it's a research CPU (and the
current patches are a bit hackish, more of the bits currently in
mips-fbsd-tdep.c probably belong in mips-tdep.c, etc.).

https://github.com/CTSRD-CHERI/gdb/compare/gdb-8.2-release...mips_cheri-8.2

-- 
John Baldwin