Re: [PULL 06/23] tests/tcg: add an explicit gdbstub register tester
Alex Bennée via Gdb <[email protected]> Thu, 16 Nov 2023 14:59:07 +0000
| Newsgroups | gmane.comp.gdb.devel,gmane.comp.emulators.qemu,gmane.comp.gdb.general |
|---|---|
| Message-ID | <[email protected]> |
Luis Machado <[email protected]> writes: > On 11/15/23 20:56, Alex Benn=C3=A9e via Gdb wrote: >> "Nicholas Piggin" <[email protected]> writes: >> >>> On Wed Nov 8, 2023 at 12:23 AM AEST, Alex Benn=C3=A9e wrote: >>>> We already do a couple of "info registers" for specific tests but this >>>> is a more comprehensive multiarch test. It also has some output >>>> helpful for debugging the gdbstub by showing which XML features are >>>> advertised and what the underlying register numbers are. >>>> >>>> My initial motivation was to see if there are any duplicate register >>>> names exposed via the gdbstub while I was reviewing the proposed >>>> register interface for TCG plugins. >>>> >>>> Mismatches between the xml and remote-desc are reported for debugging >>>> but do not fail the test. >>>> >>>> We also skip the tests for the following arches for now until we can >>>> investigate and fix any issues: >>>> >>>> - s390x (fails to read v0l->v15l, not seen in remote-registers) >>>> - ppc64 (fails to read vs0h->vs31h, not seen in remote-registers) >>> >>> binutils-gdb.git/gdb/rs6000-tdep.c has: >>> >>> static const char * >>> rs6000_register_name (struct gdbarch *gdbarch, int regno) >>> { >>> ppc_gdbarch_tdep *tdep =3D (ppc_gdbarch_tdep *) gdbarch_tdep (gdbarch= ); >>> >>> /* The upper half "registers" have names in the XML description, >>> but we present only the low GPRs and the full 64-bit registers >>> to the user. */ >>> if (tdep->ppc_ev0_upper_regnum >=3D 0 >>> && tdep->ppc_ev0_upper_regnum <=3D regno >>> && regno < tdep->ppc_ev0_upper_regnum + ppc_num_gprs) >>> return ""; >>> >>> /* Hide the upper halves of the vs0~vs31 registers. */ >>> if (tdep->ppc_vsr0_regnum >=3D 0 >>> && tdep->ppc_vsr0_upper_regnum <=3D regno >>> && regno < tdep->ppc_vsr0_upper_regnum + ppc_num_gprs) >>> return ""; >>> >>> (s390 looks similar for V0-V15 lower). >>> >>> I guess it is because the upper half is not a real register but an >>> extension of an existing FP register to make a vector register. I >>> just don't know how that should be resolved with QEMU. >>> >>> Should we put an exception in the test case for these? Or is there >>> something we should be doing differently with the XML regs? >> >> Yeah I suspect this is just inconsistency between targets on gdb. My >> naive assumption was XML should match the displayed registers but it >> seems there is additional filtering going on. >> >> It seems in this case the registers are still there and have regnums (so >> I assume the stub could be asked for them) but the names have been >> squashed. I guess we could detect that and accept it? >> >>> >>> i386 gdb does similar: >>> >>> static const char * >>> i386_register_name (struct gdbarch *gdbarch, int regnum) >>> { >>> /* Hide the upper YMM registers. */ >>> if (i386_ymmh_regnum_p (gdbarch, regnum)) >>> return ""; >>> >>> /* Hide the upper YMM16-31 registers. */ >>> if (i386_ymmh_avx512_regnum_p (gdbarch, regnum)) >>> return ""; >>> >>> /* Hide the upper ZMM registers. */ >>> if (i386_zmmh_regnum_p (gdbarch, regnum)) >>> return ""; >>> >>> return tdesc_register_name (gdbarch, regnum); >>> } >>> >>> So, I'm not sure how they don't fail this test. Does QEMU just >>> not have YMM/ZMM in XML regmap? >> >> No I think we only send the core one with XMM regs and there are no >> additional registers sent via gdb_register_coprocessor. >> >>> >>> Thanks, >>> Nick > > FTR, [email protected] doesn't exist anymore. > > As for the XML, it serves as an architecture hint/description of what fea= tures and registers > are available. > > GDB will process that and will potentially include additional pseudo-regi= sters (so QEMU doesn't > need to do so, unless it is some pseudo-register not accounted by gdb). > > The rest of the features/registers gdb doesn't care about, it will just a= dd them to the end of the > list, and will assign whatever number is next. GDB will be able to read/w= rite them, but nothing more > than that. So with a bit of fiddling I can do: modified tests/tcg/multiarch/gdbstub/registers.py @@ -44,7 +44,6 @@ def fetch_xml_regmap(): =20 total_regs =3D 0 reg_map =3D {} - frame =3D gdb.selected_frame() =20 tree =3D ET.fromstring(xml) for f in tree.findall("feature"): @@ -61,12 +60,8 @@ def fetch_xml_regmap(): for r in regs: name =3D r.attrib["name"] regnum =3D int(r.attrib["regnum"]) - try: - value =3D frame.read_register(name) - except ValueError: - report(False, f"failed to read reg: {name}") =20 - entry =3D { "name": name, "initial": value, "regnum": regnum } + entry =3D { "name": name, "regnum": regnum } =20 if name in reg_map: report(False, f"duplicate register {entry} vs {reg_map[nam= e]}") @@ -80,6 +75,15 @@ def fetch_xml_regmap(): =20 return reg_map =20 +def get_register_by_regnum(reg_map, regnum): + """ + Helper to find a register from the map via its XML regnum + """ + for regname, entry in reg_map.items(): + if entry['regnum'] =3D=3D regnum: + return entry + return None + def crosscheck_remote_xml(reg_map): """ Cross-check the list of remote-registers with the XML info. @@ -90,6 +94,7 @@ def crosscheck_remote_xml(reg_map): =20 total_regs =3D len(reg_map.keys()) total_r_regs =3D 0 + total_r_elided_regs =3D 0 =20 for r in r_regs: fields =3D r.split() @@ -100,6 +105,15 @@ def crosscheck_remote_xml(reg_map): r_name =3D fields[0] r_regnum =3D int(fields[6]) =20 + # Some registers are "hidden" so don't have a name + # although they still should have a register number + if r_name =3D=3D "''": + total_r_elided_regs +=3D 1 + x_reg =3D get_register_by_regnum(reg_map, r_regnum) + if x_reg is not None: + x_reg["hidden"] =3D True + continue + # check in the XML try: x_reg =3D reg_map[r_name] @@ -118,13 +132,38 @@ def crosscheck_remote_xml(reg_map): # registers on a 32 bit machine. Also print what is missing to # help with debug. if total_regs !=3D total_r_regs: - print(f"xml-tdesc has ({total_regs}) registers") - print(f"remote-registers has ({total_r_regs}) registers") + print(f"xml-tdesc has {total_regs} registers") + print(f"remote-registers has {total_r_regs} registers") + print(f"of which {total_r_elided_regs} are hidden") =20 for x_key in reg_map.keys(): x_reg =3D reg_map[x_key] - if "seen" not in x_reg: - print(f"{x_reg} wasn't seen in remote-registers") + if "hidden" in x_reg: + print(f"{x_reg} elided by gdb") + elif "seen" not in x_reg: + report(False, f"{x_reg} wasn't seen in remote-registers") + +def initial_register_read(reg_map): + """ + Do an initial read of all registers that we know gdb cares about + (so ignore the elided ones). + """ + frame =3D gdb.selected_frame() + + for e in reg_map.values(): + name =3D e["name"] + regnum =3D e["regnum"] + + try: + if "hidden" in e: + value =3D frame.read_register(regnum) + else: + value =3D frame.read_register(name) + + e["initial"] =3D value + except ValueError: + report(False, f"failed to read reg: {name}") + =20 def complete_and_diff(reg_map): """ @@ -144,18 +183,19 @@ def complete_and_diff(reg_map): changed =3D 0 =20 for e in reg_map.values(): - name =3D e["name"] - old_val =3D e["initial"] + if "hidden" not in e: + name =3D e["name"] + old_val =3D e["initial"] =20 - try: - new_val =3D frame.read_register(name) - except: - report(False, f"failed to read {name} at end of run") - continue + try: + new_val =3D frame.read_register(name) + except ValueError: + report(False, f"failed to read {name} at end of run") + continue =20 - if new_val !=3D old_val: - print(f"{name} changes from {old_val} to {new_val}") - changed +=3D 1 + if new_val !=3D old_val: + print(f"{name} changes from {old_val} to {new_val}") + changed +=3D 1 =20 # as long as something changed we can be confident its working report(changed > 0, f"{changed} registers were changed") @@ -168,6 +208,7 @@ def run_test(): =20 if reg_map is not None: crosscheck_remote_xml(reg_map) + initial_register_read(reg_map) complete_and_diff(reg_map) I'll wrap that into my next set of patches. --=20 Alex Benn=C3=A9e Virtualisation Tech Lead @ Linaro