[PATCH 4/7] MIPS: Correct BLEZL single-stepping

From: Maciej W. Rozycki <[email protected]>

Correct `mips32_next_pc' and also consider BLEZL taken for the value of 
zero held in the source register as per the instruction's semantics, 
restoring `less_zero_branch' label discarded with commit 54f1137d66be 
and actually matching the comment present in the source.

Verification will be provided with the test cases in the next change.

Co-Authored-By: Andrew Bennett <[email protected]>
Co-Authored-By: Matthew Fortune <[email protected]>
Co-Authored-By: Faraz Shahbazker <[email protected]>
Co-Authored-By: Milica Matic <[email protected]>
Co-Authored-By: Jovan Dmitrović <[email protected]>
Approved-by: Maciej W. Rozycki <[email protected]>
---
 gdb/mips-tdep.c |    4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

gdb-mips-next-pc-blezl.diff
Index: binutils-gdb/gdb/mips-tdep.c
===================================================================
--- binutils-gdb.orig/gdb/mips-tdep.c
+++ binutils-gdb/gdb/mips-tdep.c
@@ -1662,7 +1662,7 @@ mips32_next_pc (struct regcache *regcach
 	    case 1:		/* BNEL */
 	      goto neq_branch;
 	    case 2:		/* BLEZL */
-	      goto less_branch;
+	      goto less_equal_branch;
 	    case 3:		/* BGTZL */
 	      goto greater_branch;
 	    default:
@@ -1751,7 +1751,6 @@ mips32_next_pc (struct regcache *regcach
 	      case 2:		/* BLTZL */
 	      case 16:		/* BLTZAL */
 	      case 18:		/* BLTZALL */
-	      less_branch:
 		if (regcache_raw_get_signed (regcache, itype_rs (inst)) < 0)
 		  pc += mips32_relative_offset (inst) + 4;
 		else
@@ -1817,6 +1816,7 @@ mips32_next_pc (struct regcache *regcach
 	    pc += 8;
 	  break;
 	case 6:		/* BLEZ, BLEZL */
+	less_equal_branch:
 	  if (regcache_raw_get_signed (regcache, itype_rs (inst)) <= 0)
 	    pc += mips32_relative_offset (inst) + 4;
 	  else