[PATCH v4 07/44] gdb, arch, intelgt: add intelgt arch definitions
Markus Metzger <[email protected]>
| Newsgroups | gmane.comp.gdb.patches |
|---|---|
| Message-ID | <[email protected]> |
Provide Intel GT architecture-specific definitions that can be used by both the low target at the server side and tdep at the GDB side. Other than, for example, IA, Intel GT does not have a dedicated breakpoint instruction. Instead, it has a breakpoint bit in each instruction. We define arch methods for dealing with instruction breakpoint bits. Co-authored-by: Tankut Baris Aktemur <[email protected]> Co-authored-by: Mihails Strasuns <[email protected]> Co-authored-by: Natalia Saiapova <[email protected]> Reviewed-By: Thiago Jung Bauermann <[email protected]> Approved-By: Simon Marchi <[email protected]> --- gdb/Makefile.in | 1 + gdb/arch/intelgt.c | 191 +++++++++++++++++++++++++++++++++++++++++++++ gdb/arch/intelgt.h | 185 +++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 377 insertions(+) create mode 100644 gdb/arch/intelgt.c create mode 100644 gdb/arch/intelgt.h diff --git a/gdb/Makefile.in b/gdb/Makefile.in index 57f384170ab..4794e01246e 100644 --- a/gdb/Makefile.in +++ b/gdb/Makefile.in @@ -749,6 +749,7 @@ ALL_64_TARGET_OBS = \ arch/aarch64-scalable-linux.o \ arch/amd64-linux-tdesc.o \ arch/amd64.o \ + arch/intelgt.o \ arch/riscv.o \ bpf-tdep.o \ ia64-linux-tdep.o \ diff --git a/gdb/arch/intelgt.c b/gdb/arch/intelgt.c new file mode 100644 index 00000000000..7453de2e465 --- /dev/null +++ b/gdb/arch/intelgt.c @@ -0,0 +1,191 @@ +/* Copyright (C) 2019-2026 Free Software Foundation, Inc. + + This file is part of GDB. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see <http://www.gnu.org/licenses/>. */ + +#include "intelgt.h" +#include <stdlib.h> + +namespace intelgt { + +/* Get the bit at POS in INST. */ + +bool +get_inst_bit (gdb::array_view<const gdb_byte> inst, int pos) +{ + if (pos < 0 || (inst.size () * 8) <= pos) + internal_error (_("bad bit offset: %d"), pos); + + const int idx = pos >> 3; + const int off = pos & 7; + const int mask = 1 << off; + const gdb_byte byte = inst[idx]; + + return (byte & mask) != 0; +} + +/* Set the bit at POS in INST. */ + +bool +set_inst_bit (gdb::array_view<gdb_byte> inst, int pos) +{ + if (pos < 0 || (inst.size () * 8) <= pos) + internal_error (_("bad bit offset: %d"), pos); + + const int idx = pos >> 3; + const int off = pos & 7; + const int mask = 1 << off; + const gdb_byte byte = inst[idx]; + + const bool old = (byte & mask) != 0; + inst[idx] |= mask; + + return old; +} + +/* Clear the bit at POS in INST. */ + +bool +clear_inst_bit (gdb::array_view<gdb_byte> inst, int pos) +{ + if (pos < 0 || (inst.size () * 8) <= pos) + internal_error (_("bad bit offset: %d"), pos); + + const int idx = pos >> 3; + const int off = pos & 7; + const int mask = 1 << off; + const gdb_byte byte = inst[idx]; + + const bool old = (byte & mask) != 0; + inst[idx] &= ~mask; + + return old; +} + +/* See arch/intelgt.h. */ + +xe_version +get_xe_version (uint32_t device_id) +{ + switch (device_id) + { + case 0x4F80: + case 0x4F81: + case 0x4F82: + case 0x4F83: + case 0x4F84: + case 0x4F85: + case 0x4F86: + case 0x4F87: + case 0x4F88: + case 0x5690: + case 0x5691: + case 0x5692: + case 0x5693: + case 0x5694: + case 0x5695: + case 0x5696: + case 0x5697: + case 0x5698: + case 0x56A0: + case 0x56A1: + case 0x56A2: + case 0x56A3: + case 0x56A4: + case 0x56A5: + case 0x56A6: + case 0x56A7: + case 0x56A8: + case 0x56A9: + case 0x56B0: + case 0x56B1: + case 0x56B2: + case 0x56B3: + case 0x56BA: + case 0x56BB: + case 0x56BC: + case 0x56BD: + case 0x56C0: + case 0x56C1: + case 0x56C2: + case 0x56CF: + case 0x7D40: + case 0x7D45: + case 0x7D67: + case 0x7D41: + case 0x7D55: + case 0x7DD5: + case 0x7D51: + case 0x7DD1: + return xe_version::XE_HPG; + + case 0x0201: + case 0x0202: + case 0x0203: + case 0x0204: + case 0x0205: + case 0x0206: + case 0x0207: + case 0x0208: + case 0x0209: + case 0x020A: + case 0x020B: + case 0x020C: + case 0x020D: + case 0x020E: + case 0x020F: + case 0x0210: + return xe_version::XE_HP; + + case 0x0BD0: + case 0x0BD4: + case 0x0BD5: + case 0x0BD6: + case 0x0BD7: + case 0x0BD8: + case 0x0BD9: + case 0x0BDA: + case 0x0BDB: + case 0x0B69: + case 0x0B6E: + return xe_version::XE_HPC; + + case 0x6420: + case 0x64A0: + case 0x64B0: + + case 0xE202: + case 0xE20B: + case 0xE20C: + case 0xE20D: + case 0xE212: + return xe_version::XE2; + + case 0xB080: + case 0xB081: + case 0xB082: + case 0xB083: + case 0xB08F: + case 0xB090: + case 0xB0A0: + case 0xB0B0: + return xe_version::XE3; + + default: + return xe_version::INVALID; + } +} + +} /* namespace intelgt */ diff --git a/gdb/arch/intelgt.h b/gdb/arch/intelgt.h new file mode 100644 index 00000000000..1803810add9 --- /dev/null +++ b/gdb/arch/intelgt.h @@ -0,0 +1,185 @@ +/* Copyright (C) 2019-2026 Free Software Foundation, Inc. + + This file is part of GDB. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see <http://www.gnu.org/licenses/>. */ + +#ifndef GDB_ARCH_INTELGT_H +#define GDB_ARCH_INTELGT_H + +namespace intelgt { + +/* Various arch constants. */ + +enum breakpoint_kind : int +{ + BP_INSTRUCTION = 1, +}; + +/* The length of a full and compact IntelGT instruction in bytes. */ + +constexpr int MAX_INST_LENGTH = 16; +constexpr int COMPACT_INST_LENGTH = 8; + +/* Feature names. + + They correspond to register sets defined in zet_intel_gpu_debug.h. We + declare feature names in the order used in that header. + + The SBA register set consists of a set of base registers in the order + defined in that header file. + + Not all registers have DWARF numbers. See DWARF_REGSETS below for a + list of features that do. */ +constexpr const char *FEATURE_GRF = "org.gnu.gdb.intelgt.grf"; +constexpr const char *FEATURE_ADDR = "org.gnu.gdb.intelgt.addr"; +constexpr const char *FEATURE_FLAG = "org.gnu.gdb.intelgt.flag"; +constexpr const char *FEATURE_CE = "org.gnu.gdb.intelgt.ce"; +constexpr const char *FEATURE_SR = "org.gnu.gdb.intelgt.sr"; +constexpr const char *FEATURE_CR = "org.gnu.gdb.intelgt.cr"; +constexpr const char *FEATURE_TDR = "org.gnu.gdb.intelgt.tdr"; +constexpr const char *FEATURE_ACC = "org.gnu.gdb.intelgt.acc"; +constexpr const char *FEATURE_MME = "org.gnu.gdb.intelgt.mme"; +constexpr const char *FEATURE_SP = "org.gnu.gdb.intelgt.sp"; +constexpr const char *FEATURE_SBA = "org.gnu.gdb.intelgt.sba"; +constexpr const char *FEATURE_DBG = "org.gnu.gdb.intelgt.dbg"; +constexpr const char *FEATURE_FC = "org.gnu.gdb.intelgt.fc"; +constexpr const char *FEATURE_DEBUGGER = "org.gnu.gdb.intelgt.debugger"; + +/* Register sets/groups needed for DWARF mapping. Used for + declaring static arrays for various mapping tables. */ + +enum dwarf_regsets : int +{ + REGSET_SBA = 0, + REGSET_GRF, + REGSET_ADDR, + REGSET_FLAG, + REGSET_ACC, + REGSET_MME, + REGSET_COUNT +}; + +/* Map of dwarf_regset values to the target description + feature names. */ + +constexpr const char *DWARF_REGSET_FEATURES[REGSET_COUNT] = { + FEATURE_SBA, + FEATURE_GRF, + FEATURE_ADDR, + FEATURE_FLAG, + FEATURE_ACC, + FEATURE_MME +}; + +/* The encoding for XE version enumerators follows this pattern, which is + aligned with the Intel Graphics (dis)Assembler (IGA) encoding. */ + +constexpr int XE_VERSION (int major, int minor) +{ + return ((major << 24) | minor); +} + +/* Supported GDB XE platforms. */ + +enum class xe_version +{ + INVALID = 0, + XE_HP = XE_VERSION (1, 1), + XE_HPG = XE_VERSION (1, 2), + XE_HPC = XE_VERSION (1, 4), + XE2 = XE_VERSION (2, 0), + XE3 = XE_VERSION (3, 0), +}; + +/* Helper function to translate the device id to a device version. */ + +xe_version get_xe_version (uint32_t device_id); + +/* Get the bit at POS in INST. */ + +bool get_inst_bit (gdb::array_view<const gdb_byte> inst, int pos); + +/* Set the bit at POS in INST. */ + +bool set_inst_bit (gdb::array_view<gdb_byte> inst, int pos); + +/* Clear the bit at POS in INST. */ + +bool clear_inst_bit (gdb::array_view<gdb_byte> inst, int pos); + +static inline int +breakpoint_bit_offset (gdb::array_view<const gdb_byte> inst, + uint32_t device_id) +{ + xe_version device_version = get_xe_version (device_id); + switch (device_version) + { + case intelgt::xe_version::XE_HP: + case intelgt::xe_version::XE_HPG: + case intelgt::xe_version::XE_HPC: + case intelgt::xe_version::XE2: + case intelgt::xe_version::XE3: + /* Check the CmptCtrl flag (bit 29). */ + return (((inst[3] & 0x20) != 0) ? 7 : 30); + + case intelgt::xe_version::INVALID: + break; + } + error (_("Unsupported device id 0x%" PRIx32), device_id); +} + +static inline bool +set_breakpoint (gdb::array_view<gdb_byte> inst, uint32_t device_id) +{ + return set_inst_bit (inst, breakpoint_bit_offset (inst, device_id)); +} + +static inline bool +clear_breakpoint (gdb::array_view<gdb_byte> inst, uint32_t device_id) +{ + return clear_inst_bit (inst, breakpoint_bit_offset (inst, device_id)); +} + +static inline bool +has_breakpoint (gdb::array_view<const gdb_byte> inst, uint32_t device_id) +{ + return get_inst_bit (inst, breakpoint_bit_offset (inst, device_id)); +} + +static inline unsigned int +inst_length (gdb::array_view<const gdb_byte> inst, uint32_t device_id) +{ + xe_version device_version = get_xe_version (device_id); + switch (device_version) + { + case intelgt::xe_version::XE_HP: + case intelgt::xe_version::XE_HPG: + case intelgt::xe_version::XE_HPC: + case intelgt::xe_version::XE2: + case intelgt::xe_version::XE3: + /* Check the CmptCtrl flag (bit 29). */ + return (((inst[3] & 0x20) != 0) + ? COMPACT_INST_LENGTH + : MAX_INST_LENGTH); + + case intelgt::xe_version::INVALID: + break; + } + error (_("Unsupported device id 0x%" PRIx32), device_id); +} + +} /* namespace intelgt */ + +#endif /* GDB_ARCH_INTELGT_H */ -- 2.43.0 ________________________________________ Intel Deutschland GmbH Registered Address: Dornacher Strasse 1, 85622 Feldkirchen, Germany Tel: +49 (89) 99143-0 www.intel.de Managing Directors: Candice Moore, Jeffrey Schneiderman, Ramachandran Sitaraman Chairperson of the Supervisory Board: Sonja Pierer Registered Seat: Munich Commercial Register B: Amtsgericht Munich HRB 186928 This e-mail and any attachments may contain confidential material for the sole use of the intended recipient(s). Any review or distribution by others is strictly prohibited. If you are not the intended recipient, please contact the sender and delete all copies.