[PATCH v2 5/6] sim/mips: Keep the pending interrupts in Cause
Sebastian Huber <[email protected]>
| Newsgroups | gmane.comp.gdb.patches |
|---|---|
| Message-ID | <[email protected]> |
signal_exception() assigned the whole Cause register. It discarded
the interrupt pending field, so the handler of an interrupt read
Cause.IP as zero. The handler could not tell which interrupt the
processor delivered. The R3900 path keeps the field already.
Keep the interrupt pending field on the other targets as well. Add
cause_IPALL_mask for the complete field, because cause_IP_mask covers
only the six hardware interrupts.
---
sim/mips/interp.c | 4 ++--
sim/mips/sim-main.h | 4 ++++
2 files changed, 6 insertions(+), 2 deletions(-)
diff --git a/sim/mips/interp.c b/sim/mips/interp.c
index dc918bb9281..8118b290a17 100644
--- a/sim/mips/interp.c
+++ b/sim/mips/interp.c
@@ -1962,7 +1962,7 @@ signal_exception (SIM_DESC sd,
/* See figure 5-17 for an outline of the code below */
if (! (SR & status_EXL))
{
- CAUSE = (exception << 2);
+ CAUSE = (CAUSE & cause_IPALL_mask) | (exception << 2);
if (STATE & simDELAYSLOT)
{
STATE &= ~simDELAYSLOT;
@@ -1976,7 +1976,7 @@ signal_exception (SIM_DESC sd,
}
else
{
- CAUSE = (exception << 2);
+ CAUSE = (CAUSE & cause_IPALL_mask) | (exception << 2);
/* vector = 0x180; */
}
SR |= status_EXL;
diff --git a/sim/mips/sim-main.h b/sim/mips/sim-main.h
index b6cb4e12258..28a4221dfd5 100644
--- a/sim/mips/sim-main.h
+++ b/sim/mips/sim-main.h
@@ -557,6 +557,10 @@ struct mips_sim_state {
#define cause_SW1 (1 << 9) /* Software interrupt 1 */
#define cause_IP_mask (0x3f) /* Interrupt pending field */
#define cause_IP_shift (10)
+/* The complete interrupt pending field, IP7:IP0. Its bits meet the
+ Status.IM bits. */
+#define cause_IPALL_mask ((cause_IP_mask << cause_IP_shift) \
+ | cause_SW1 | cause_SW0)
#define cause_set_EXC(x) CAUSE = (CAUSE & ~cause_EXC_mask) | ((x << cause_EXC_shift) & cause_EXC_mask)
#define cause_set_EXC2(x) CAUSE = (CAUSE & ~cause_EXC2_mask) | ((x << cause_EXC2_shift) & cause_EXC2_mask)
--
2.51.0