[mono/llvm] a8df6e18: Disable a backend optimization which can fail on thumb.

"Zoltan Varga ([email protected])" <[email protected]> Sun, 17 Nov 2013 22:46:57 +0000
Newsgroups gmane.comp.gnome.mono.patches
Message-ID <00000142683ed33d-3afdaf2a-34b3-48df-b659-66134761879c-000000@email.amazonses.com>
   Branch: refs/heads/mono4
     Home: https://github.com/mono/llvm
  Compare: https://github.com/mono/llvm/compare/f41e74e4a298...a8df6e181c3f

   Commit: a8df6e181c3f5c20a4c9d842774774458c17fe4a
   Author: Zoltan Varga <[email protected]> (vargaz)
     Date: 2013-11-17 22:45:43 GMT
      URL: https://github.com/mono/llvm/commit/a8df6e181c3f5c20a4c9d842774774458c17fe4a

Disable a backend optimization which can fail on thumb.

Changed paths:
  M lib/Target/ARM/ARMBaseInstrInfo.cpp

Modified: lib/Target/ARM/ARMBaseInstrInfo.cpp
===================================================================
@@ -2402,6 +2402,19 @@ inline static bool isRedundantFlagInstr(MachineInstr *CmpI, unsigned SrcReg,
           return false;
     }
 
+	// FIXME:
+	// Enabling this causes codegen failures with -mtriple=thumbv7-ios:
+	// http://llvm.org/bugs/show_bug.cgi?id=17971
+	// Probably because the alloca is dce-d away even through it sets CPSR.
+	//define internal hidden i1 @FOO() {
+	//BB0:
+	//%0 = alloca i32, align 4
+	//%1 = ptrtoint i32* %0 to i32
+	//%2 = icmp eq i32 %1, 0
+	//ret i1 %2
+	//}
+	return false;
+
     // Toggle the optional operand to CPSR.
     MI->getOperand(5).setReg(ARM::CPSR);
     MI->getOperand(5).setIsDef(true);


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