[binutils-gdb] PR 34029: bpf: allow w regs in load/store insns similar to llvm
"Jose E. Marchesi via Binutils-cvs" <[email protected]>
| Newsgroups | gmane.comp.gnu.binutils.cvs |
|---|---|
| Message-ID | <[email protected]> |
https://sourceware.org/git/gitweb.cgi?p=binutils-gdb.git;h=774c54454b1f7bf0bf2303bcb1370e4333300424 commit 774c54454b1f7bf0bf2303bcb1370e4333300424 Author: Vineet Gupta <[email protected]> Date: Tue Mar 31 13:42:12 2026 -0700 PR 34029: bpf: allow w regs in load/store insns similar to llvm e.g. | *(u32 *)(r9 +0) = w0 | Error: unexpected register name `w0' in expression | w0 = *(u32 *)(r9 +0) | Error: unexpected register name `w0' in expression This syntax is allowed by llvm, athough encoding wise it is same as the insn with rN reg. Use newly added %dR and %sR to accept either r or w prefix registers in load and store insns respectively (except u64 variants which have no w-form). The original motivation was a now abondoned gcc change which would generate these patterns. Signed-off-by: Vineet Gupta <[email protected]> Diff: --- gas/testsuite/gas/bpf/mem-be-pseudoc.d | 32 +++++++++++++++++++------------- gas/testsuite/gas/bpf/mem-pseudoc.d | 32 +++++++++++++++++++------------- gas/testsuite/gas/bpf/mem-pseudoc.s | 6 ++++++ opcodes/bpf-opc.c | 12 ++++++------ 4 files changed, 50 insertions(+), 32 deletions(-) diff --git a/gas/testsuite/gas/bpf/mem-be-pseudoc.d b/gas/testsuite/gas/bpf/mem-be-pseudoc.d index b7715c463a2..e53b20c0e22 100644 --- a/gas/testsuite/gas/bpf/mem-be-pseudoc.d +++ b/gas/testsuite/gas/bpf/mem-be-pseudoc.d @@ -18,16 +18,22 @@ Disassembly of section .text: 38: 69 21 7e ef 00 00 00 00 r2=\*\(u16\*\)\(r1\+0x7eef\) 40: 71 21 7e ef 00 00 00 00 r2=\*\(u8\*\)\(r1\+0x7eef\) 48: 79 21 ff fe 00 00 00 00 r2=\*\(u64\*\)\(r1\+0xfffe\) - 50: 63 12 7e ef 00 00 00 00 \*\(u32\*\)\(r1\+0x7eef\)=r2 - 58: 6b 12 7e ef 00 00 00 00 \*\(u16\*\)\(r1\+0x7eef\)=r2 - 60: 73 12 7e ef 00 00 00 00 \*\(u8\*\)\(r1\+0x7eef\)=r2 - 68: 7b 12 ff fe 00 00 00 00 \*\(u64\*\)\(r1\+0xfffe\)=r2 - 70: 72 10 7e ef 11 22 33 44 \*\(u8\*\)\(r1\+0x7eef\)=0x11223344 - 78: 6a 10 7e ef 11 22 33 44 \*\(u16\*\)\(r1\+0x7eef\)=0x11223344 - 80: 62 10 7e ef 11 22 33 44 \*\(u32\*\)\(r1\+0x7eef\)=0x11223344 - 88: 7a 10 ff fe 11 22 33 44 \*\(u64\*\)\(r1\+0xfffe\)=0x11223344 - 90: 81 21 7e ef 00 00 00 00 r2=\*\(s32\*\)\(r1\+0x7eef\) - 98: 89 21 7e ef 00 00 00 00 r2=\*\(s16\*\)\(r1\+0x7eef\) - a0: 91 21 7e ef 00 00 00 00 r2=\*\(s8\*\)\(r1\+0x7eef\) - a8: 99 21 7e ef 00 00 00 00 r2=\*\(s64\*\)\(r1\+0x7eef\) - b0: 61 21 00 00 00 00 00 00 r2=\*\(u32\*\)\(r1\+0x0\) + 50: 61 21 7e ef 00 00 00 00 r2=\*\(u32\*\)\(r1\+0x7eef\) + 58: 69 21 7e ef 00 00 00 00 r2=\*\(u16\*\)\(r1\+0x7eef\) + 60: 71 21 7e ef 00 00 00 00 r2=\*\(u8\*\)\(r1\+0x7eef\) + 68: 63 12 7e ef 00 00 00 00 \*\(u32\*\)\(r1\+0x7eef\)=r2 + 70: 6b 12 7e ef 00 00 00 00 \*\(u16\*\)\(r1\+0x7eef\)=r2 + 78: 73 12 7e ef 00 00 00 00 \*\(u8\*\)\(r1\+0x7eef\)=r2 + 80: 7b 12 ff fe 00 00 00 00 \*\(u64\*\)\(r1\+0xfffe\)=r2 + 88: 63 12 7e ef 00 00 00 00 \*\(u32\*\)\(r1\+0x7eef\)=r2 + 90: 6b 12 7e ef 00 00 00 00 \*\(u16\*\)\(r1\+0x7eef\)=r2 + 98: 73 12 7e ef 00 00 00 00 \*\(u8\*\)\(r1\+0x7eef\)=r2 + a0: 72 10 7e ef 11 22 33 44 \*\(u8\*\)\(r1\+0x7eef\)=0x11223344 + a8: 6a 10 7e ef 11 22 33 44 \*\(u16\*\)\(r1\+0x7eef\)=0x11223344 + b0: 62 10 7e ef 11 22 33 44 \*\(u32\*\)\(r1\+0x7eef\)=0x11223344 + b8: 7a 10 ff fe 11 22 33 44 \*\(u64\*\)\(r1\+0xfffe\)=0x11223344 + c0: 81 21 7e ef 00 00 00 00 r2=\*\(s32\*\)\(r1\+0x7eef\) + c8: 89 21 7e ef 00 00 00 00 r2=\*\(s16\*\)\(r1\+0x7eef\) + d0: 91 21 7e ef 00 00 00 00 r2=\*\(s8\*\)\(r1\+0x7eef\) + d8: 99 21 7e ef 00 00 00 00 r2=\*\(s64\*\)\(r1\+0x7eef\) + e0: 61 21 00 00 00 00 00 00 r2=\*\(u32\*\)\(r1\+0x0\) diff --git a/gas/testsuite/gas/bpf/mem-pseudoc.d b/gas/testsuite/gas/bpf/mem-pseudoc.d index b704de51f8f..4f6a7131be3 100644 --- a/gas/testsuite/gas/bpf/mem-pseudoc.d +++ b/gas/testsuite/gas/bpf/mem-pseudoc.d @@ -18,16 +18,22 @@ Disassembly of section .text: 38: 69 12 ef 7e 00 00 00 00 r2=\*\(u16\*\)\(r1\+0x7eef\) 40: 71 12 ef 7e 00 00 00 00 r2=\*\(u8\*\)\(r1\+0x7eef\) 48: 79 12 fe ff 00 00 00 00 r2=\*\(u64\*\)\(r1\+0xfffe\) - 50: 63 21 ef 7e 00 00 00 00 \*\(u32\*\)\(r1\+0x7eef\)=r2 - 58: 6b 21 ef 7e 00 00 00 00 \*\(u16\*\)\(r1\+0x7eef\)=r2 - 60: 73 21 ef 7e 00 00 00 00 \*\(u8\*\)\(r1\+0x7eef\)=r2 - 68: 7b 21 fe ff 00 00 00 00 \*\(u64\*\)\(r1\+0xfffe\)=r2 - 70: 72 01 ef 7e 44 33 22 11 \*\(u8\*\)\(r1\+0x7eef\)=0x11223344 - 78: 6a 01 ef 7e 44 33 22 11 \*\(u16\*\)\(r1\+0x7eef\)=0x11223344 - 80: 62 01 ef 7e 44 33 22 11 \*\(u32\*\)\(r1\+0x7eef\)=0x11223344 - 88: 7a 01 fe ff 44 33 22 11 \*\(u64\*\)\(r1\+0xfffe\)=0x11223344 - 90: 81 12 ef 7e 00 00 00 00 r2=\*\(s32\*\)\(r1\+0x7eef\) - 98: 89 12 ef 7e 00 00 00 00 r2=\*\(s16\*\)\(r1\+0x7eef\) - a0: 91 12 ef 7e 00 00 00 00 r2=\*\(s8\*\)\(r1\+0x7eef\) - a8: 99 12 ef 7e 00 00 00 00 r2=\*\(s64\*\)\(r1\+0x7eef\) - b0: 61 12 00 00 00 00 00 00 r2=\*\(u32\*\)\(r1\+0x0\) + 50: 61 12 ef 7e 00 00 00 00 r2=\*\(u32\*\)\(r1\+0x7eef\) + 58: 69 12 ef 7e 00 00 00 00 r2=\*\(u16\*\)\(r1\+0x7eef\) + 60: 71 12 ef 7e 00 00 00 00 r2=\*\(u8\*\)\(r1\+0x7eef\) + 68: 63 21 ef 7e 00 00 00 00 \*\(u32\*\)\(r1\+0x7eef\)=r2 + 70: 6b 21 ef 7e 00 00 00 00 \*\(u16\*\)\(r1\+0x7eef\)=r2 + 78: 73 21 ef 7e 00 00 00 00 \*\(u8\*\)\(r1\+0x7eef\)=r2 + 80: 7b 21 fe ff 00 00 00 00 \*\(u64\*\)\(r1\+0xfffe\)=r2 + 88: 63 21 ef 7e 00 00 00 00 \*\(u32\*\)\(r1\+0x7eef\)=r2 + 90: 6b 21 ef 7e 00 00 00 00 \*\(u16\*\)\(r1\+0x7eef\)=r2 + 98: 73 21 ef 7e 00 00 00 00 \*\(u8\*\)\(r1\+0x7eef\)=r2 + a0: 72 01 ef 7e 44 33 22 11 \*\(u8\*\)\(r1\+0x7eef\)=0x11223344 + a8: 6a 01 ef 7e 44 33 22 11 \*\(u16\*\)\(r1\+0x7eef\)=0x11223344 + b0: 62 01 ef 7e 44 33 22 11 \*\(u32\*\)\(r1\+0x7eef\)=0x11223344 + b8: 7a 01 fe ff 44 33 22 11 \*\(u64\*\)\(r1\+0xfffe\)=0x11223344 + c0: 81 12 ef 7e 00 00 00 00 r2=\*\(s32\*\)\(r1\+0x7eef\) + c8: 89 12 ef 7e 00 00 00 00 r2=\*\(s16\*\)\(r1\+0x7eef\) + d0: 91 12 ef 7e 00 00 00 00 r2=\*\(s8\*\)\(r1\+0x7eef\) + d8: 99 12 ef 7e 00 00 00 00 r2=\*\(s64\*\)\(r1\+0x7eef\) + e0: 61 12 00 00 00 00 00 00 r2=\*\(u32\*\)\(r1\+0x0\) diff --git a/gas/testsuite/gas/bpf/mem-pseudoc.s b/gas/testsuite/gas/bpf/mem-pseudoc.s index 19907753916..f9f94db4acb 100644 --- a/gas/testsuite/gas/bpf/mem-pseudoc.s +++ b/gas/testsuite/gas/bpf/mem-pseudoc.s @@ -11,10 +11,16 @@ r2 = *(u16 *)(r1 + 32495) r2 = *(u8 *)(r1 + 32495) r2 = *(u64 *)(r1 - 2) + w2 = *(u32 *)(r1 + 32495) + w2 = *(u16 *)(r1 + 32495) + w2 = *(u8 *)(r1 + 32495) *(u32 *)(r1 + 32495) = r2 *(u16 *)(r1 + 32495) = r2 *(u8 *)(r1 + 32495) = r2 *(u64 *)(r1 - 2) = r2 + *(u32 *)(r1 + 32495) = w2 + *(u16 *)(r1 + 32495) = w2 + *(u8 *)(r1 + 32495) = w2 *(u8 *)(r1 + 0x7eef) = 0x11223344 *(u16 *)(r1 + 0x7eef) = 0x11223344 *(u32 *)(r1 + 0x7eef) = 0x11223344 diff --git a/opcodes/bpf-opc.c b/opcodes/bpf-opc.c index aa5493280ea..4babf6e8649 100644 --- a/opcodes/bpf-opc.c +++ b/opcodes/bpf-opc.c @@ -208,11 +208,11 @@ const struct bpf_opcode bpf_opcodes[] = BPF_V1, BPF_CODE, BPF_CLASS_LD|BPF_SIZE_W|BPF_MODE_ABS}, /* Generic load instructions (to register.) */ - {BPF_INSN_LDXB, "ldxb%W%dr , [ %sr %o16 ]", "%dr = * ( u8 * ) ( %sr %o16 )", + {BPF_INSN_LDXB, "ldxb%W%dr , [ %sr %o16 ]", "%dR = * ( u8 * ) ( %sr %o16 )", BPF_V1, BPF_CODE, BPF_CLASS_LDX|BPF_SIZE_B|BPF_MODE_MEM}, - {BPF_INSN_LDXH, "ldxh%W%dr , [ %sr %o16 ]", "%dr = * ( u16 * ) ( %sr %o16 )", + {BPF_INSN_LDXH, "ldxh%W%dr , [ %sr %o16 ]", "%dR = * ( u16 * ) ( %sr %o16 )", BPF_V1, BPF_CODE, BPF_CLASS_LDX|BPF_SIZE_H|BPF_MODE_MEM}, - {BPF_INSN_LDXW, "ldxw%W%dr , [ %sr %o16 ]", "%dr = * ( u32 * ) ( %sr %o16 )", + {BPF_INSN_LDXW, "ldxw%W%dr , [ %sr %o16 ]", "%dR = * ( u32 * ) ( %sr %o16 )", BPF_V1, BPF_CODE, BPF_CLASS_LDX|BPF_SIZE_W|BPF_MODE_MEM}, {BPF_INSN_LDXDW, "ldxdw%W%dr , [ %sr %o16 ]","%dr = * ( u64 * ) ( %sr %o16 )", BPF_V1, BPF_CODE, BPF_CLASS_LDX|BPF_SIZE_DW|BPF_MODE_MEM}, @@ -228,11 +228,11 @@ const struct bpf_opcode bpf_opcodes[] = BPF_V4, BPF_CODE, BPF_CLASS_LDX|BPF_SIZE_DW|BPF_MODE_SMEM}, /* Generic store instructions (from register.) */ - {BPF_INSN_STXBR, "stxb%W[ %dr %o16 ] , %sr", "* ( u8 * ) ( %dr %o16 ) = %sr", + {BPF_INSN_STXBR, "stxb%W[ %dr %o16 ] , %sr", "* ( u8 * ) ( %dr %o16 ) = %sR", BPF_V1, BPF_CODE, BPF_CLASS_STX|BPF_SIZE_B|BPF_MODE_MEM}, - {BPF_INSN_STXHR, "stxh%W[ %dr %o16 ] , %sr", "* ( u16 * ) ( %dr %o16 ) = %sr", + {BPF_INSN_STXHR, "stxh%W[ %dr %o16 ] , %sr", "* ( u16 * ) ( %dr %o16 ) = %sR", BPF_V1, BPF_CODE, BPF_CLASS_STX|BPF_SIZE_H|BPF_MODE_MEM}, - {BPF_INSN_STXWR, "stxw%W[ %dr %o16 ], %sr", "* ( u32 * ) ( %dr %o16 ) = %sr", + {BPF_INSN_STXWR, "stxw%W[ %dr %o16 ], %sr", "* ( u32 * ) ( %dr %o16 ) = %sR", BPF_V1, BPF_CODE, BPF_CLASS_STX|BPF_SIZE_W|BPF_MODE_MEM}, {BPF_INSN_STXDWR, "stxdw%W[ %dr %o16 ] , %sr", "* ( u64 * ) ( %dr %o16 ) = %sr", BPF_V1, BPF_CODE, BPF_CLASS_STX|BPF_SIZE_DW|BPF_MODE_MEM},