[binutils-gdb] aarch64: Remove unused operand SM3_IMM2

https://sourceware.org/git/gitweb.cgi?p=binutils-gdb.git;h=9c0b9c4d841a34d8300aac9e86c6bcf5fcda19e3

commit 9c0b9c4d841a34d8300aac9e86c6bcf5fcda19e3
Author: Alice Carlotti <[email protected]>
Date:   Wed Apr 29 17:10:54 2026 +0100

    aarch64: Remove unused operand SM3_IMM2
    
    This operand was intended to be used for the sm3tt* instructions, but
    those were added with operand Em instead.

Diff:
---
 gas/config/tc-aarch64.c  | 2 --
 include/opcode/aarch64.h | 1 -
 opcodes/aarch64-asm-2.c  | 1 -
 opcodes/aarch64-dis-2.c  | 1 -
 opcodes/aarch64-opc-2.c  | 1 -
 opcodes/aarch64-opc.c    | 1 -
 opcodes/aarch64-tbl.h    | 2 --
 7 files changed, 9 deletions(-)

diff --git a/gas/config/tc-aarch64.c b/gas/config/tc-aarch64.c
index 0b72fc1a54f..bc279ff32ca 100644
--- a/gas/config/tc-aarch64.c
+++ b/gas/config/tc-aarch64.c
@@ -6460,7 +6460,6 @@ process_omitted_operand (enum aarch64_opnd type, const aarch64_opcode *opcode,
     case AARCH64_OPND_Em:
     case AARCH64_OPND_Em16:
     case AARCH64_OPND_Em8:
-    case AARCH64_OPND_SM3_IMM2:
       operand->reglane.regno = default_value;
       break;
 
@@ -7050,7 +7049,6 @@ parse_operands (char *str, const aarch64_opcode *opcode)
 	case AARCH64_OPND_Em:
 	case AARCH64_OPND_Em16:
 	case AARCH64_OPND_Em8:
-	case AARCH64_OPND_SM3_IMM2:
 	  reg_type = REG_TYPE_V;
 	vector_reg_index:
 	  reg = aarch64_reg_parse (&str, reg_type, &vectype);
diff --git a/include/opcode/aarch64.h b/include/opcode/aarch64.h
index 222de5f49ab..30087f5fe3c 100644
--- a/include/opcode/aarch64.h
+++ b/include/opcode/aarch64.h
@@ -987,7 +987,6 @@ enum aarch64_opnd
   AARCH64_OPND_SME_ZT0_INDEX_MUL_VL,/* ZT0[<imm>], bits [13:12].  */
   AARCH64_OPND_SME_ZT0_LIST,	/* { zt0/ZT0 } (not encoded).  */
   AARCH64_OPND_TME_UIMM16,	/* TME unsigned 16-bit immediate.  */
-  AARCH64_OPND_SM3_IMM2,	/* SM3 encodes lane in bits [13, 14].  */
   AARCH64_OPND_MOPS_ADDR_Rd,	/* [Rd]!, in bits [0, 4].  */
   AARCH64_OPND_MOPS_ADDR_Rs,	/* [Rs]!, in bits [16, 20].  */
   AARCH64_OPND_MOPS_WB_Rn,	/* Rn!, in bits [5, 9].  */
diff --git a/opcodes/aarch64-asm-2.c b/opcodes/aarch64-asm-2.c
index a5533c43421..d2e302e6100 100644
--- a/opcodes/aarch64-asm-2.c
+++ b/opcodes/aarch64-asm-2.c
@@ -866,7 +866,6 @@ aarch64_insert_operand (const aarch64_operand *self,
     case AARCH64_OPND_Em:
     case AARCH64_OPND_Em16:
     case AARCH64_OPND_Em8:
-    case AARCH64_OPND_SM3_IMM2:
       return aarch64_ins_reglane (self, info, code, inst, errors);
     case AARCH64_OPND_Em_INDEX1_14:
     case AARCH64_OPND_Em_INDEX2_13:
diff --git a/opcodes/aarch64-dis-2.c b/opcodes/aarch64-dis-2.c
index 69bf6f90564..3cbf33db77c 100644
--- a/opcodes/aarch64-dis-2.c
+++ b/opcodes/aarch64-dis-2.c
@@ -37851,7 +37851,6 @@ aarch64_extract_operand (const aarch64_operand *self,
     case AARCH64_OPND_Em:
     case AARCH64_OPND_Em16:
     case AARCH64_OPND_Em8:
-    case AARCH64_OPND_SM3_IMM2:
       return aarch64_ext_reglane (self, info, code, inst, errors);
     case AARCH64_OPND_Em_INDEX1_14:
     case AARCH64_OPND_Em_INDEX2_13:
diff --git a/opcodes/aarch64-opc-2.c b/opcodes/aarch64-opc-2.c
index fb8f664d195..8a2c560e53f 100644
--- a/opcodes/aarch64-opc-2.c
+++ b/opcodes/aarch64-opc-2.c
@@ -365,7 +365,6 @@ const struct aarch64_operand aarch64_operands[] =
   {AARCH64_OPND_CLASS_IMMEDIATE, "SME_ZT0_INDEX_MUL_VL", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_imm3_12}, "a ZT0 index"},
   {AARCH64_OPND_CLASS_SYSTEM, "SME_ZT0_LIST", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {}, "{ ZT0 }"},
   {AARCH64_OPND_CLASS_IMMEDIATE, "TME_UIMM16", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_imm16_5}, "a 16-bit unsigned immediate for TME tcancel"},
-  {AARCH64_OPND_CLASS_SIMD_ELEMENT, "SM3_IMM2", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SM3_imm2}, "an indexed SM3 vector immediate"},
   {AARCH64_OPND_CLASS_INT_REG, "MOPS_ADDR_Rd", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rd}, "a register destination address with writeback"},
   {AARCH64_OPND_CLASS_INT_REG, "MOPS_ADDR_Rs", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rs}, "a register source address with writeback"},
   {AARCH64_OPND_CLASS_INT_REG, "MOPS_WB_Rn", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn}, "an integer register with writeback"},
diff --git a/opcodes/aarch64-opc.c b/opcodes/aarch64-opc.c
index 3beecc00fe3..fb4213e44b2 100644
--- a/opcodes/aarch64-opc.c
+++ b/opcodes/aarch64-opc.c
@@ -4311,7 +4311,6 @@ aarch64_print_operand (char *buf, size_t size, bfd_vma pc,
     case AARCH64_OPND_Em:
     case AARCH64_OPND_Em16:
     case AARCH64_OPND_Em8:
-    case AARCH64_OPND_SM3_IMM2:
       snprintf (buf, size, "%s[%s]",
 		style_reg (styler, "v%d.%s", opnd->reglane.regno,
 			   aarch64_get_qualifier_name (opnd->qualifier)),
diff --git a/opcodes/aarch64-tbl.h b/opcodes/aarch64-tbl.h
index fc57f83b120..a6913b8073f 100644
--- a/opcodes/aarch64-tbl.h
+++ b/opcodes/aarch64-tbl.h
@@ -8674,8 +8674,6 @@ const struct aarch64_opcode aarch64_opcode_table[] =
     Y(SYSTEM, none, "SME_ZT0_LIST", 0, F (), "{ ZT0 }")			\
     Y(IMMEDIATE, imm, "TME_UIMM16", 0, F(FLD_imm16_5),			\
       "a 16-bit unsigned immediate for TME tcancel")			\
-    Y(SIMD_ELEMENT, reglane, "SM3_IMM2", 0, F(FLD_SM3_imm2),		\
-      "an indexed SM3 vector immediate")				\
     /* These next two are really register fields; the [...] notation	\
        is just syntactic sugar.  */					\
     Y(INT_REG, x0_to_x30, "MOPS_ADDR_Rd", 0, F(FLD_Rd),			\