[binutils-gdb] aarch64: Remove F_STRICT
Alice Carlotti via Binutils-cvs <[email protected]>
| Newsgroups | gmane.comp.gnu.binutils.cvs |
|---|---|
| Message-ID | <[email protected]> |
https://sourceware.org/git/gitweb.cgi?p=binutils-gdb.git;h=ece614ad0606cb6f39b7060ae895d719917ee597 commit ece614ad0606cb6f39b7060ae895d719917ee597 Author: Alice Carlotti <[email protected]> Date: Tue May 5 15:30:06 2026 +0100 aarch64: Remove F_STRICT With the introduction of AARCH64_OPND_QLF_UNKNOWN, the F_STRICT flag is no longer needed and can be deleted. Diff: --- include/opcode/aarch64.h | 5 +- opcodes/aarch64-tbl.h | 158 +++++++++++++++++++++++------------------------ 2 files changed, 81 insertions(+), 82 deletions(-) diff --git a/include/opcode/aarch64.h b/include/opcode/aarch64.h index aaced69c744..9a1767fa6c0 100644 --- a/include/opcode/aarch64.h +++ b/include/opcode/aarch64.h @@ -1480,8 +1480,7 @@ extern const aarch64_opcode aarch64_opcode_table[]; /* Instruction has the field of 'sz'. */ #define F_LSE_SZ (1 << 27) /* Require an exact qualifier match, even for NIL qualifiers. */ -#define F_STRICT (1ULL << 28) -/* This system instruction is used to read system registers. */ + #define F_SYS_READ (1ULL << 29) /* This system instruction is used to write system registers. */ #define F_SYS_WRITE (1ULL << 30) @@ -1543,7 +1542,7 @@ extern const aarch64_opcode aarch64_opcode_table[]; /* As above, plus PN registers. */ #define F_INVALID_IMM_SYMS_3 (3ULL << 42) -/* Next bit is 44. */ +/* Next bit is 44, and 28 is also unused. */ /* Instruction constraints. */ /* This instruction has a predication constraint on the instruction at PC+4. */ diff --git a/opcodes/aarch64-tbl.h b/opcodes/aarch64-tbl.h index 3300ddbb57a..518109ecfd6 100644 --- a/opcodes/aarch64-tbl.h +++ b/opcodes/aarch64-tbl.h @@ -3335,10 +3335,10 @@ static const aarch64_feature_set aarch64_feature_mpamv2 = { NAME, OPCODE, MASK, CLASS, 0, FPRCVT, OPS, QUALS, FLAGS, 0, 0, NULL } #define _SVE_INSN(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS,TIED) \ { NAME, OPCODE, MASK, CLASS, OP, SVE, OPS, QUALS, \ - FLAGS | F_STRICT | F_INVALID_IMM_SYMS_2, 0, TIED, NULL } + FLAGS | F_INVALID_IMM_SYMS_2, 0, TIED, NULL } #define _SVE_INSNC(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS,CONSTRAINTS,TIED) \ { NAME, OPCODE, MASK, CLASS, OP, SVE, OPS, QUALS, \ - FLAGS | F_STRICT | F_INVALID_IMM_SYMS_2, CONSTRAINTS, TIED, NULL } + FLAGS | F_INVALID_IMM_SYMS_2, CONSTRAINTS, TIED, NULL } #define PAUTH_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS) \ { NAME, OPCODE, MASK, CLASS, 0, PAUTH, OPS, QUALS, FLAGS, 0, 0, NULL } #define CNUM_INSN(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS) \ @@ -3377,105 +3377,105 @@ static const aarch64_feature_set aarch64_feature_mpamv2 = { NAME, OPCODE, MASK, CLASS, OP, TME, OPS, QUALS, FLAGS | F_INVALID_IMM_SYMS_1, 0, 0, NULL } #define SVE2_INSN(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS,TIED) \ { NAME, OPCODE, MASK, CLASS, OP, SVE2, OPS, QUALS, \ - FLAGS | F_STRICT | F_INVALID_IMM_SYMS_2, 0, TIED, NULL } + FLAGS | F_INVALID_IMM_SYMS_2, 0, TIED, NULL } #define SME2p1_INSN(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS,TIED) \ { NAME, OPCODE, MASK, CLASS, OP, SME2p1, OPS, QUALS, \ - FLAGS | F_STRICT, 0, TIED, NULL } + FLAGS, 0, TIED, NULL } #define SVE_F16F32MM_INSN(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS,CONSTRAINTS) \ - { NAME, OPCODE, MASK, CLASS, OP, SVE_F16F32MM, OPS, QUALS, FLAGS | F_STRICT, CONSTRAINTS, 0, NULL } + { NAME, OPCODE, MASK, CLASS, OP, SVE_F16F32MM, OPS, QUALS, FLAGS, CONSTRAINTS, 0, NULL } #define F8F32MM_INSN(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS) \ { NAME, OPCODE, MASK, CLASS, OP, F8F32MM, OPS, QUALS, FLAGS, 0, 0, NULL } #define F8F32MM_SVE2_INSN(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS,CONSTRAINTS) \ - { NAME, OPCODE, MASK, CLASS, OP, F8F32MM_SVE2, OPS, QUALS, FLAGS | F_STRICT, CONSTRAINTS, 0, NULL } + { NAME, OPCODE, MASK, CLASS, OP, F8F32MM_SVE2, OPS, QUALS, FLAGS, CONSTRAINTS, 0, NULL } #define F8F16MM_INSN(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS) \ { NAME, OPCODE, MASK, CLASS, OP, F8F16MM, OPS, QUALS, FLAGS, 0, 0, NULL } #define F8F16MM_SVE2_INSN(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS,CONSTRAINTS) \ - { NAME, OPCODE, MASK, CLASS, OP, F8F16MM_SVE2, OPS, QUALS, FLAGS | F_STRICT, CONSTRAINTS, 0, NULL } + { NAME, OPCODE, MASK, CLASS, OP, F8F16MM_SVE2, OPS, QUALS, FLAGS, CONSTRAINTS, 0, NULL } #define SVE2_INSNC(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS,CONSTRAINTS,TIED) \ { NAME, OPCODE, MASK, CLASS, OP, SVE2, OPS, QUALS, \ - FLAGS | F_STRICT | F_INVALID_IMM_SYMS_2, CONSTRAINTS, TIED, NULL } + FLAGS | F_INVALID_IMM_SYMS_2, CONSTRAINTS, TIED, NULL } #define B16B16_SVE2_INSN(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS,TIED) \ { NAME, OPCODE, MASK, CLASS, OP, B16B16_SVE2, OPS, QUALS, \ - FLAGS | F_STRICT, 0, TIED, NULL } + FLAGS, 0, TIED, NULL } #define B16B16_SVE2_INSNC(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS,CONSTRAINTS,TIED) \ { NAME, OPCODE, MASK, CLASS, OP, B16B16_SVE2, OPS, QUALS, \ - FLAGS | F_STRICT, CONSTRAINTS, TIED, NULL } + FLAGS, CONSTRAINTS, TIED, NULL } #define SVE_B16B16_SME_INSN(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS,TIED) \ { NAME, OPCODE, MASK, CLASS, OP, SVE_B16B16_SME, OPS, QUALS, \ - FLAGS | F_STRICT, 0, TIED, NULL } + FLAGS, 0, TIED, NULL } #define SVE_B16B16_SME_INSNC(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS,CONSTRAINTS,TIED) \ { NAME, OPCODE, MASK, CLASS, OP, SVE_B16B16_SME, OPS, QUALS, \ - FLAGS | F_STRICT, CONSTRAINTS, TIED, NULL } + FLAGS, CONSTRAINTS, TIED, NULL } #define SME_B16B16_INSN(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS,TIED) \ { NAME, OPCODE, MASK, CLASS, OP, SME_B16B16, OPS, QUALS, \ - FLAGS | F_STRICT, 0, TIED, NULL } + FLAGS, 0, TIED, NULL } #define SVE2p1_INSN(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS,TIED) \ { NAME, OPCODE, MASK, CLASS, OP, SVE2p1, OPS, QUALS, \ - FLAGS | F_STRICT, 0, TIED, NULL } + FLAGS, 0, TIED, NULL } #define SVE2p1_INSNC(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS,CONSTRAINTS,TIED) \ { NAME, OPCODE, MASK, CLASS, OP, SVE2p1, OPS, QUALS, \ - FLAGS | F_STRICT, CONSTRAINTS, TIED, NULL } + FLAGS, CONSTRAINTS, TIED, NULL } #define SVE2AES_INSN(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS,TIED) \ { NAME, OPCODE, MASK, CLASS, OP, SVE2_AES, OPS, QUALS, \ - FLAGS | F_STRICT, 0, TIED, NULL } + FLAGS, 0, TIED, NULL } #define SVE_AES2_INSN(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS,TIED) \ { NAME, OPCODE, MASK, CLASS, OP, SVE_AES2, OPS, QUALS, \ - FLAGS | F_STRICT, 0, TIED, NULL } + FLAGS, 0, TIED, NULL } #define SVE2SHA3_INSN(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS,TIED) \ { NAME, OPCODE, MASK, CLASS, OP, SVE2_SHA3, OPS, QUALS, \ - FLAGS | F_STRICT, 0, TIED, NULL } + FLAGS, 0, TIED, NULL } #define SVE2SM4_INSN(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS,TIED) \ { NAME, OPCODE, MASK, CLASS, OP, SVE2_SM4, OPS, QUALS, \ - FLAGS | F_STRICT, 0, TIED, NULL } + FLAGS, 0, TIED, NULL } #define SVE2SM4_INSNC(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS,CONSTRAINTS,TIED) \ { NAME, OPCODE, MASK, CLASS, OP, SVE2_SM4, OPS, QUALS, \ - FLAGS | F_STRICT, CONSTRAINTS, TIED, NULL } + FLAGS, CONSTRAINTS, TIED, NULL } #define SME_INSN(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS,TIED) \ { NAME, OPCODE, MASK, CLASS, OP, SME, OPS, QUALS, \ - F_STRICT | F_INVALID_IMM_SYMS_2 | FLAGS, 0, TIED, NULL } + F_INVALID_IMM_SYMS_2 | FLAGS, 0, TIED, NULL } #define SME_F64F64_INSN(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS,TIED) \ { NAME, OPCODE, MASK, CLASS, OP, SME_F64F64, OPS, QUALS, \ - F_STRICT | FLAGS, 0, TIED, NULL } + FLAGS, 0, TIED, NULL } #define SME_I16I64_INSN(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS,TIED) \ { NAME, OPCODE, MASK, CLASS, OP, SME_I16I64, OPS, QUALS, \ - F_STRICT | FLAGS, 0, TIED, NULL } + FLAGS, 0, TIED, NULL } #define SME_INSNC(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS,CONSTRAINTS,TIED) \ { NAME, OPCODE, MASK, CLASS, OP, SME, OPS, QUALS, \ - F_STRICT | FLAGS, CONSTRAINTS, TIED, NULL } + FLAGS, CONSTRAINTS, TIED, NULL } #define SME2_INSN(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS,TIED) \ { NAME, OPCODE, MASK, CLASS, OP, SME2, OPS, QUALS, \ - F_STRICT | F_INVALID_IMM_SYMS_3 | FLAGS, 0, TIED, NULL } + F_INVALID_IMM_SYMS_3 | FLAGS, 0, TIED, NULL } #define SME2_INSNC(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS,CONSTRAINTS,TIED) \ { NAME, OPCODE, MASK, CLASS, OP, SME2, OPS, QUALS, \ - FLAGS | F_STRICT, CONSTRAINTS, TIED, NULL } + FLAGS, CONSTRAINTS, TIED, NULL } #define SME2_I16I64_INSN(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS,TIED) \ { NAME, OPCODE, MASK, CLASS, OP, SME2_I16I64, OPS, QUALS, \ - F_STRICT | FLAGS, 0, TIED, NULL } + FLAGS, 0, TIED, NULL } #define SME2_F64F64_INSN(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS,TIED) \ { NAME, OPCODE, MASK, CLASS, OP, SME2_F64F64, OPS, QUALS, \ - F_STRICT | FLAGS, 0, TIED, NULL } + FLAGS, 0, TIED, NULL } #define SVE2BITPERM_INSN(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS,TIED) \ { NAME, OPCODE, MASK, CLASS, OP, SVE2_BITPERM, OPS, QUALS, \ - FLAGS | F_STRICT, 0, TIED, NULL } + FLAGS, 0, TIED, NULL } #define SVE_BFSCALE_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS,CONSTRAINTS,TIED) \ - { NAME, OPCODE, MASK, CLASS, 0, SVE_BFSCALE, OPS, QUALS, FLAGS | F_STRICT, CONSTRAINTS, TIED, NULL } + { NAME, OPCODE, MASK, CLASS, 0, SVE_BFSCALE, OPS, QUALS, FLAGS, CONSTRAINTS, TIED, NULL } #define SVE_BFSCALE_SME2_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS,TIED) \ - { NAME, OPCODE, MASK, CLASS, 0, SVE_BFSCALE_SME2, OPS, QUALS, FLAGS | F_STRICT, 0, TIED, NULL } + { NAME, OPCODE, MASK, CLASS, 0, SVE_BFSCALE_SME2, OPS, QUALS, FLAGS, 0, TIED, NULL } #define BFLOAT16_SVE_INSNC(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS,CONSTRAINTS,TIED) \ - { NAME, OPCODE, MASK, CLASS, 0, BFLOAT16_SVE, OPS, QUALS, FLAGS | F_STRICT, \ + { NAME, OPCODE, MASK, CLASS, 0, BFLOAT16_SVE, OPS, QUALS, FLAGS, \ CONSTRAINTS, TIED, NULL } #define BFLOAT16_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS) \ { NAME, OPCODE, MASK, CLASS, 0, BFLOAT16, OPS, QUALS, FLAGS, 0, 0, NULL } #define INT8MATMUL_SVE_INSNC(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS, CONSTRAINTS, TIED) \ - { NAME, OPCODE, MASK, CLASS, 0, I8MM_SVE, OPS, QUALS, FLAGS | F_STRICT, CONSTRAINTS, TIED, NULL } + { NAME, OPCODE, MASK, CLASS, 0, I8MM_SVE, OPS, QUALS, FLAGS, CONSTRAINTS, TIED, NULL } #define INT8MATMUL_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS) \ { NAME, OPCODE, MASK, CLASS, 0, I8MM, OPS, QUALS, FLAGS, 0, 0, NULL } #define F64MATMUL_SVE_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS,TIED) \ - { NAME, OPCODE, MASK, CLASS, 0, F64MM_SVE, OPS, QUALS, FLAGS | F_STRICT, 0, TIED, NULL } + { NAME, OPCODE, MASK, CLASS, 0, F64MM_SVE, OPS, QUALS, FLAGS, 0, TIED, NULL } #define F64MATMUL_SVE_INSNC(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS, CONSTRAINTS, TIED) \ - { NAME, OPCODE, MASK, CLASS, 0, F64MM_SVE, OPS, QUALS, FLAGS | F_STRICT, CONSTRAINTS, TIED, NULL } + { NAME, OPCODE, MASK, CLASS, 0, F64MM_SVE, OPS, QUALS, FLAGS, CONSTRAINTS, TIED, NULL } #define F32MATMUL_SVE_INSNC(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS, CONSTRAINTS, TIED) \ - { NAME, OPCODE, MASK, CLASS, 0, F32MM_SVE, OPS, QUALS, FLAGS | F_STRICT, CONSTRAINTS, TIED, NULL } + { NAME, OPCODE, MASK, CLASS, 0, F32MM_SVE, OPS, QUALS, FLAGS, CONSTRAINTS, TIED, NULL } #define V8R_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS) \ { NAME, OPCODE, MASK, CLASS, 0, ARMV8R, OPS, QUALS, FLAGS, 0, 0, NULL } #define XS_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS) \ @@ -3521,36 +3521,36 @@ static const aarch64_feature_set aarch64_feature_mpamv2 = { NAME, OPCODE, MASK, CLASS, 0, CPA, OPS, QUALS, 0, 0, 0, NULL } #define CPA_SVE_INSNC(NAME,OPCODE,MASK,CLASS,OPS,QUALS,CONSTRAINTS,TIED) \ { NAME, OPCODE, MASK, CLASS, 0, CPA_SVE, OPS, QUALS, \ - F_STRICT, CONSTRAINTS, TIED, NULL } + 0, CONSTRAINTS, TIED, NULL } #define FAMINMAX_INSN(NAME,OPCODE,MASK,OPS,QUALS,FLAGS) \ { NAME, OPCODE, MASK, asimdsame, 0, FAMINMAX, OPS, QUALS, FLAGS, 0, 0, NULL } #define FAMINMAX_SVE2_INSN(NAME,OPCODE,MASK,OPS,QUALS,CONSTRAINTS) \ { NAME, OPCODE, MASK, sve_size_hsd, 0, FAMINMAX_SVE2, OPS, QUALS, \ - F_STRICT, CONSTRAINTS, 2, NULL } + 0, CONSTRAINTS, 2, NULL } #define FAMINMAX_SME2_INSN(NAME,OPCODE,MASK,OPS,QUALS) \ { NAME, OPCODE, MASK, sme_size_22_hsd, 0, FAMINMAX_SME2, OPS, QUALS, \ - F_STRICT, 0, 1, NULL } + 0, 0, 1, NULL } #define FP8_INSN(NAME, OPCODE, MASK, CLASS, OPS, QUALS, FLAGS) \ { NAME, OPCODE, MASK, CLASS, 0, FP8, OPS, QUALS, FLAGS, 0, 0, NULL } #define FP8_SVE2_INSN(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS,TIED) \ { NAME, OPCODE, MASK, CLASS, OP, FP8_SVE2, OPS, QUALS, \ - FLAGS | F_STRICT, 0, TIED, NULL } + FLAGS, 0, TIED, NULL } #define FP8_SME2_INSN(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS,TIED) \ { NAME, OPCODE, MASK, CLASS, OP, FP8_SME2, OPS, QUALS, \ - F_STRICT | FLAGS, 0, TIED, NULL } + FLAGS, 0, TIED, NULL } #define LUT_INSN(NAME,OPCODE,MASK,OPS,QUALS,FLAGS) \ { NAME, OPCODE, MASK, lut, 0, LUT, OPS, QUALS, FLAGS, 0, 0, NULL } #define LUT_SVE2_INSN(NAME,OPCODE,MASK,OPS,QUALS,FLAGS,CONSTRAINTS) \ { NAME, OPCODE, MASK, sve_misc, 0, LUT_SVE2, OPS, QUALS, \ - FLAGS | F_STRICT, CONSTRAINTS, 0, NULL } + FLAGS, CONSTRAINTS, 0, NULL } #define BRBE_INSN(NAME,OPCODE,MASK,OPS,QUALS,FLAGS) \ { NAME, OPCODE, MASK, ic_system, 0, BRBE, OPS, QUALS, FLAGS, 0, 0, NULL } #define LUTv2_SME2_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS) \ { NAME, OPCODE, MASK, CLASS, 0, LUTv2_SME2, OPS, QUALS, \ - FLAGS | F_STRICT, 0, 0, NULL } + FLAGS, 0, 0, NULL } #define LUTv2_SME2p1_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS) \ { NAME, OPCODE, MASK, CLASS, 0, LUTv2_SME2p1, OPS, QUALS, \ - FLAGS | F_STRICT, 0, 0, NULL } + FLAGS, 0, 0, NULL } #define FP8FMA_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS) \ { NAME, OPCODE, MASK, CLASS, 0, FP8FMA, OPS, QUALS, FLAGS, 0, 0, NULL } #define FP8DOT4_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS) \ @@ -3558,97 +3558,97 @@ static const aarch64_feature_set aarch64_feature_mpamv2 = #define FP8DOT2_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS) \ { NAME, OPCODE, MASK, CLASS, 0, FP8DOT2, OPS, QUALS, FLAGS, 0, 0, NULL } #define FP8FMA_SVE_INSNC(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS,CONSTRAINTS,TIED) \ - { NAME, OPCODE, MASK, CLASS, 0, FP8FMA_SVE, OPS, QUALS, F_STRICT | FLAGS, CONSTRAINTS, TIED, NULL } + { NAME, OPCODE, MASK, CLASS, 0, FP8FMA_SVE, OPS, QUALS, FLAGS, CONSTRAINTS, TIED, NULL } #define FP8DOT4_SVE_INSNC(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS,CONSTRAINTS,TIED) \ - { NAME, OPCODE, MASK, CLASS, 0, FP8DOT4_SVE, OPS, QUALS, F_STRICT | FLAGS, CONSTRAINTS, TIED, NULL } + { NAME, OPCODE, MASK, CLASS, 0, FP8DOT4_SVE, OPS, QUALS, FLAGS, CONSTRAINTS, TIED, NULL } #define FP8DOT2_SVE_INSNC(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS,CONSTRAINTS,TIED) \ - { NAME, OPCODE, MASK, CLASS, 0, FP8DOT2_SVE, OPS, QUALS, F_STRICT | FLAGS, CONSTRAINTS, TIED, NULL } + { NAME, OPCODE, MASK, CLASS, 0, FP8DOT2_SVE, OPS, QUALS, FLAGS, CONSTRAINTS, TIED, NULL } #define SME_F8F32_INSNC(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS,CONSTRAINTS) \ - { NAME, OPCODE, MASK, CLASS, 0, SME_F8F32, OPS, QUALS, F_STRICT | FLAGS, CONSTRAINTS, 0, NULL } + { NAME, OPCODE, MASK, CLASS, 0, SME_F8F32, OPS, QUALS, FLAGS, CONSTRAINTS, 0, NULL } #define SME_F8F16_INSNC(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS,CONSTRAINTS) \ - { NAME, OPCODE, MASK, CLASS, 0, SME_F8F16, OPS, QUALS, F_STRICT | FLAGS, CONSTRAINTS, 0, NULL } + { NAME, OPCODE, MASK, CLASS, 0, SME_F8F16, OPS, QUALS, FLAGS, CONSTRAINTS, 0, NULL } #define SME_F16F16_F8F16_INSNC(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS,CONSTRAINTS) \ - { NAME, OPCODE, MASK, CLASS, 0, SME_F16F16_F8F16, OPS, QUALS, F_STRICT | FLAGS, CONSTRAINTS, 0, NULL } + { NAME, OPCODE, MASK, CLASS, 0, SME_F16F16_F8F16, OPS, QUALS, FLAGS, CONSTRAINTS, 0, NULL } #define SME_F16F16_INSN(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS,TIED) \ { NAME, OPCODE, MASK, CLASS, OP, SME_F16F16, OPS, QUALS, \ - FLAGS | F_STRICT, 0, TIED, NULL } + FLAGS, 0, TIED, NULL } #define SVE2p1_SME_INSN(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS,TIED) \ { NAME, OPCODE, MASK, CLASS, OP, SVE2p1_SME, OPS, QUALS, \ - F_STRICT | FLAGS, 0, TIED, NULL } + FLAGS, 0, TIED, NULL } #define SVE2p1_SME_INSNC(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS,CONSTRAINTS,TIED) \ { NAME, OPCODE, MASK, CLASS, OP, SVE2p1_SME, OPS, QUALS, \ - F_STRICT | FLAGS, CONSTRAINTS, TIED, NULL } + FLAGS, CONSTRAINTS, TIED, NULL } #define SVE2p1_SME2_INSN(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS,TIED) \ { NAME, OPCODE, MASK, CLASS, OP, SVE2p1_SME2, OPS, QUALS, \ - F_STRICT | F_INVALID_IMM_SYMS_2 | FLAGS, 0, TIED, NULL } + F_INVALID_IMM_SYMS_2 | FLAGS, 0, TIED, NULL } #define SVE2p1_SME2_INSNC(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS,CONSTRAINTS,TIED) \ { NAME, OPCODE, MASK, CLASS, OP, SVE2p1_SME2, OPS, QUALS, \ - F_STRICT | FLAGS, CONSTRAINTS, TIED, NULL } + FLAGS, CONSTRAINTS, TIED, NULL } #define SVE2p1_SME2p1_INSN(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS,TIED) \ { NAME, OPCODE, MASK, CLASS, OP, SVE2p1_SME2p1, OPS, QUALS, \ - F_STRICT | FLAGS, 0, TIED, NULL } + FLAGS, 0, TIED, NULL } #define SVE2p1_SME2p1_INSNC(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS,CONSTRAINTS,TIED) \ { NAME, OPCODE, MASK, CLASS, OP, SVE2p1_SME2p1, OPS, QUALS, \ - F_STRICT | F_INVALID_IMM_SYMS_2 | FLAGS, CONSTRAINTS, TIED, NULL } + F_INVALID_IMM_SYMS_2 | FLAGS, CONSTRAINTS, TIED, NULL } #define SVE_SME2p2_INSN(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS,TIED) \ { NAME, OPCODE, MASK, CLASS, OP, SVE_SME2p2, OPS, QUALS, \ - FLAGS | F_STRICT, 0, TIED, NULL } + FLAGS, 0, TIED, NULL } #define SVE2p2_SME2p2_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS,CONSTRAINTS,TIED) \ { NAME, OPCODE, MASK, CLASS, 0, SVE2p2_SME2p2, OPS, QUALS, \ - F_STRICT | FLAGS, CONSTRAINTS, TIED, NULL } + FLAGS, CONSTRAINTS, TIED, NULL } #define SME2p2_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS,TIED) \ { NAME, OPCODE, MASK, CLASS, 0, SME2p2, OPS, QUALS, \ - F_STRICT | FLAGS, 0, TIED, NULL } + FLAGS, 0, TIED, NULL } #define GCIE_INSN(NAME,OPCODE,MASK,OPS,QUALS,FLAGS) \ { NAME, OPCODE, MASK, ic_system, 0, GCIE, OPS, QUALS, FLAGS, 0, 0, NULL } #define _SVE_SSVE_FEXPA_INSN(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS,TIED) \ { NAME, OPCODE, MASK, CLASS, OP, SVE_SSVE_FEXPA, OPS, QUALS, \ - FLAGS | F_STRICT, 0, TIED, NULL } + FLAGS, 0, TIED, NULL } #define SME_TMOP_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS,TIED) \ { NAME, OPCODE, MASK, CLASS, 0, SME_TMOP, OPS, QUALS, \ - FLAGS | F_STRICT, 0, TIED, NULL } + FLAGS, 0, TIED, NULL } #define SME_TMOP_B16B16_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS,TIED) \ { NAME, OPCODE, MASK, CLASS, 0, SME_TMOP_B16B16, OPS, QUALS, \ - FLAGS | F_STRICT, 0, TIED, NULL } + FLAGS, 0, TIED, NULL } #define SME_TMOP_F16F16_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS,TIED) \ { NAME, OPCODE, MASK, CLASS, 0, SME_TMOP_F16F16, OPS, QUALS, \ - FLAGS | F_STRICT, 0, TIED, NULL } + FLAGS, 0, TIED, NULL } #define SME_TMOP_F8F16_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS,TIED) \ { NAME, OPCODE, MASK, CLASS, 0, SME_TMOP_F8F16, OPS, QUALS, \ - FLAGS | F_STRICT, 0, TIED, NULL } + FLAGS, 0, TIED, NULL } #define SME_TMOP_F8F32_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS,TIED) \ { NAME, OPCODE, MASK, CLASS, 0, SME_TMOP_F8F32, OPS, QUALS, \ - FLAGS | F_STRICT, 0, TIED, NULL } + FLAGS, 0, TIED, NULL } #define SME_MOP4_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS,TIED) \ { NAME, OPCODE, MASK, CLASS, 0, SME_MOP4, OPS, QUALS, \ - FLAGS | F_STRICT, 0, TIED, NULL } + FLAGS, 0, TIED, NULL } #define SME_MOP4_B16B16_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS,TIED) \ { NAME, OPCODE, MASK, CLASS, 0, SME_MOP4_B16B16, OPS, QUALS, \ - FLAGS | F_STRICT, 0, TIED, NULL } + FLAGS, 0, TIED, NULL } #define SME_MOP4_F16F16_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS,TIED) \ { NAME, OPCODE, MASK, CLASS, 0, SME_MOP4_F16F16, OPS, QUALS, \ - FLAGS | F_STRICT, 0, TIED, NULL } + FLAGS, 0, TIED, NULL } #define SME_MOP4_F64F64_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS,TIED) \ { NAME, OPCODE, MASK, CLASS, 0, SME_MOP4_F64F64, OPS, QUALS, \ - FLAGS | F_STRICT, 0, TIED, NULL } + FLAGS, 0, TIED, NULL } #define SME_MOP4_F8F16_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS,TIED) \ { NAME, OPCODE, MASK, CLASS, 0, SME_MOP4_F8F16, OPS, QUALS, \ - FLAGS | F_STRICT, 0, TIED, NULL } + FLAGS, 0, TIED, NULL } #define SME_MOP4_F8F32_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS,TIED) \ { NAME, OPCODE, MASK, CLASS, 0, SME_MOP4_F8F32, OPS, QUALS, \ - FLAGS | F_STRICT, 0, TIED, NULL } + FLAGS, 0, TIED, NULL } #define SME_MOP4_I16I64_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS,TIED) \ { NAME, OPCODE, MASK, CLASS, 0, SME_MOP4_I16I64, OPS, QUALS, \ - FLAGS | F_STRICT, 0, TIED, NULL } + FLAGS, 0, TIED, NULL } #define SVE2p3_INSN(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS,CONSTRAINTS, TIED) \ { NAME, OPCODE, MASK, CLASS, OP, SVE2p3, OPS, QUALS, \ - F_STRICT | FLAGS, CONSTRAINTS, TIED, NULL } + FLAGS, CONSTRAINTS, TIED, NULL } #define SME2p3_INSN(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS,CONSTRAINTS, TIED) \ { NAME, OPCODE, MASK, CLASS, OP, SME2p3, OPS, QUALS, \ FLAGS, CONSTRAINTS, TIED, NULL } #define SVE2p3_SME2p3_INSN(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS,CONSTRAINTS, TIED) \ { NAME, OPCODE, MASK, CLASS, OP, SVE2p3_SME2p3, OPS, QUALS, \ - F_STRICT | F_INVALID_IMM_SYMS_3 | FLAGS, CONSTRAINTS, TIED, NULL } + F_INVALID_IMM_SYMS_3 | FLAGS, CONSTRAINTS, TIED, NULL } #define F16F32DOT_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS) \ { NAME, OPCODE, MASK, CLASS, 0, F16F32DOT, OPS, QUALS, FLAGS, 0, 0, NULL } @@ -3657,9 +3657,9 @@ static const aarch64_feature_set aarch64_feature_mpamv2 = #define F16MM_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS) \ { NAME, OPCODE, MASK, CLASS, 0, F16MM, OPS, QUALS, FLAGS, 0, 0, NULL } #define F16MM_SVE2p2_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS) \ - { NAME, OPCODE, MASK, CLASS, 0, F16MM, OPS, QUALS, FLAGS | F_STRICT, 0, 0, NULL } + { NAME, OPCODE, MASK, CLASS, 0, F16MM, OPS, QUALS, FLAGS, 0, 0, NULL } #define SVE_B16MM_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS) \ - { NAME, OPCODE, MASK, CLASS, 0, SVE_B16MM, OPS, QUALS, FLAGS | F_STRICT, 0, 0, NULL } + { NAME, OPCODE, MASK, CLASS, 0, SVE_B16MM, OPS, QUALS, FLAGS, 0, 0, NULL } #define POE2_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS, FLAGS) \ { NAME, OPCODE, MASK, CLASS, 0, POE2, OPS, QUALS, FLAGS | F_INVALID_IMM_SYMS_1, 0, 0, NULL } #define TEV_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS, FLAGS) \ @@ -7591,8 +7591,8 @@ const struct aarch64_opcode aarch64_opcode_table[] = LUT_SVE2_INSN ("luti4", 0x4520bc00, 0xff20fc00, OP3 (SVE_Zd, SVE_ZnxN, SVE_Zm2_22_INDEX), OP_SVE_HHU, F_OD(1), 0), /* SME2 lutv2. */ - LUTv2_SME2_INSN ("luti4", 0xc08b0000, 0xffffcc23, sme_size_12_b, OP3 (SME_Zdnx4, SME_ZT0, SME_Znx2_BIT_INDEX), OP_SVE_BUU, F_STRICT | 0), - LUTv2_SME2p1_INSN ("luti4", 0xc09b0000, 0xffffcc2c, sme_size_12_b, OP3 (SME_Ztx4_STRIDED, SME_ZT0, SME_Znx2_BIT_INDEX), OP_SVE_BUU, F_STRICT | 0), + LUTv2_SME2_INSN ("luti4", 0xc08b0000, 0xffffcc23, sme_size_12_b, OP3 (SME_Zdnx4, SME_ZT0, SME_Znx2_BIT_INDEX), OP_SVE_BUU, 0), + LUTv2_SME2p1_INSN ("luti4", 0xc09b0000, 0xffffcc2c, sme_size_12_b, OP3 (SME_Ztx4_STRIDED, SME_ZT0, SME_Znx2_BIT_INDEX), OP_SVE_BUU, 0), LUTv2_SME2_INSN ("movt", 0xc04f03e0, 0xffffcfe0, sme_misc, OP2 (SME_ZT0_INDEX_MUL_VL, SVE_Zt), QL_NIL2, 0), /* SME FP16 ZA-targeting addition instructions. */ SME_F16F16_F8F16_INSNC ("fadd", 0xc1a41c00, 0xffff9c38, sme_misc, OP2 (SME_ZA_array_off3_0, SME_Znx2), OP_SVE_HH, F_OD (2), 0),