[binutils-gdb] aarch64: Remove disassembly restriction on OP_MOV_Z_Zi

https://sourceware.org/git/gitweb.cgi?p=binutils-gdb.git;h=49ff47a01981a832284a59ba5e51612a32839bbb

commit 49ff47a01981a832284a59ba5e51612a32839bbb
Author: Alice Carlotti <[email protected]>
Date:   Fri May 15 03:52:30 2026 +0100

    aarch64: Remove disassembly restriction on OP_MOV_Z_Zi
    
    Disassembly for the OP_MOV_Z_Zi opcode artificially rejected a zero
    index value, to indicate that the preferred disassembly uses a different
    alias.  This is more naturally indicated by specifying the other alias
    as a higher priority.
    
    Update the alias priority, and remove the zero check and the now-unused
    OP_MOV_Z_Zi enum value.

Diff:
---
 include/opcode/aarch64.h | 1 -
 opcodes/aarch64-asm-2.c  | 2 +-
 opcodes/aarch64-asm.c    | 2 --
 opcodes/aarch64-dis-2.c  | 8 ++++----
 opcodes/aarch64-dis.c    | 5 -----
 opcodes/aarch64-opc-2.c  | 1 -
 opcodes/aarch64-tbl.h    | 4 ++--
 7 files changed, 7 insertions(+), 16 deletions(-)

diff --git a/include/opcode/aarch64.h b/include/opcode/aarch64.h
index 9851f4ad248..81bdf337786 100644
--- a/include/opcode/aarch64.h
+++ b/include/opcode/aarch64.h
@@ -1323,7 +1323,6 @@ enum aarch64_op
   OP_MOV_Z_P_Z,
   OP_MOV_Z_V,
   OP_MOV_Z_Z,
-  OP_MOV_Z_Zi,
   OP_MOVM_P_P_P,
   OP_MOVS_P_P,
   OP_MOVZS_P_P_P,
diff --git a/opcodes/aarch64-asm-2.c b/opcodes/aarch64-asm-2.c
index eed062eebe0..351fbdece4f 100644
--- a/opcodes/aarch64-asm-2.c
+++ b/opcodes/aarch64-asm-2.c
@@ -630,8 +630,8 @@ aarch64_find_real_opcode (const aarch64_opcode *opcode)
     case A64_OPID_05203800_dup_SVE_Zd_Rn_SP:
       value = A64_OPID_05203800_dup_SVE_Zd_Rn_SP;
       break;
-    case A64_OPID_05202000_mov_SVE_Zd_SVE_Zn_INDEX:
     case A64_OPID_05202000_mov_SVE_Zd_SVE_VZn:
+    case A64_OPID_05202000_mov_SVE_Zd_SVE_Zn_INDEX:
     case A64_OPID_05202000_dup_SVE_Zd_SVE_Zn_INDEX:
       value = A64_OPID_05202000_dup_SVE_Zd_SVE_Zn_INDEX;
       break;
diff --git a/opcodes/aarch64-asm.c b/opcodes/aarch64-asm.c
index 305ac2981ce..ef1e093ed94 100644
--- a/opcodes/aarch64-asm.c
+++ b/opcodes/aarch64-asm.c
@@ -1968,8 +1968,6 @@ do_misc_encoding (aarch64_inst *inst)
       value = extract_field (FLD_SVE_Zn, inst->value, 0);
       insert_field (FLD_SVE_Zm_16, &inst->value, value, 0);
       break;
-    case OP_MOV_Z_Zi:
-      break;
     case OP_MOVM_P_P_P:
       /* Copy Pd to Pm.  */
       value = extract_field (FLD_SVE_Pd, inst->value, 0);
diff --git a/opcodes/aarch64-dis-2.c b/opcodes/aarch64-dis-2.c
index 33cb384b4a5..7c1bf81802e 100644
--- a/opcodes/aarch64-dis-2.c
+++ b/opcodes/aarch64-dis-2.c
@@ -36944,7 +36944,7 @@ aarch64_find_alias_opcode (const aarch64_opcode *opcode)
       value = A64_OPID_05203800_mov_SVE_Zd_Rn_SP;
       break;
     case A64_OPID_05202000_dup_SVE_Zd_SVE_Zn_INDEX:
-      value = A64_OPID_05202000_mov_SVE_Zd_SVE_Zn_INDEX;
+      value = A64_OPID_05202000_mov_SVE_Zd_SVE_VZn;
       break;
     case A64_OPID_2538c000_dup_SVE_Zd_SVE_ASIMM:
       value = A64_OPID_2538c000_fmov_SVE_Zd_FPIMM0;
@@ -37635,10 +37635,10 @@ aarch64_find_next_alias_opcode (const aarch64_opcode *opcode)
     case A64_OPID_05203800_mov_SVE_Zd_Rn_SP:
       value = A64_OPID_05203800_dup_SVE_Zd_Rn_SP;
       break;
-    case A64_OPID_05202000_mov_SVE_Zd_SVE_Zn_INDEX:
-      value = A64_OPID_05202000_mov_SVE_Zd_SVE_VZn;
-      break;
     case A64_OPID_05202000_mov_SVE_Zd_SVE_VZn:
+      value = A64_OPID_05202000_mov_SVE_Zd_SVE_Zn_INDEX;
+      break;
+    case A64_OPID_05202000_mov_SVE_Zd_SVE_Zn_INDEX:
       value = A64_OPID_05202000_dup_SVE_Zd_SVE_Zn_INDEX;
       break;
     case A64_OPID_2538c000_fmov_SVE_Zd_FPIMM0:
diff --git a/opcodes/aarch64-dis.c b/opcodes/aarch64-dis.c
index d73975fe783..5c27e74871e 100644
--- a/opcodes/aarch64-dis.c
+++ b/opcodes/aarch64-dis.c
@@ -2728,11 +2728,6 @@ do_misc_decoding (aarch64_inst *inst)
       return (extract_field (FLD_SVE_Zn, inst->value, 0)
 	      == extract_field (FLD_SVE_Zm_16, inst->value, 0));
 
-    case OP_MOV_Z_Zi:
-      /* Index must be nonzero.  */
-      value = extract_fields (inst->value, 0, 2, FLD_SVE_tszh, FLD_imm5);
-      return value > 0 && value != (value & -value);
-
     case OP_MOVM_P_P_P:
       return (extract_field (FLD_SVE_Pd, inst->value, 0)
 	      == extract_field (FLD_SVE_Pm, inst->value, 0));
diff --git a/opcodes/aarch64-opc-2.c b/opcodes/aarch64-opc-2.c
index d2da039c6e5..7e48d7114b0 100644
--- a/opcodes/aarch64-opc-2.c
+++ b/opcodes/aarch64-opc-2.c
@@ -460,7 +460,6 @@ static const enum aarch64_opcode_idx op_enum_table [] =
   A64_OPID_0520c000_mov_SVE_Zd_SVE_Pg4_10_SVE_Zn,
   A64_OPID_05202000_mov_SVE_Zd_SVE_VZn,
   A64_OPID_04603000_mov_SVE_Zd_SVE_Zn,
-  A64_OPID_05202000_mov_SVE_Zd_SVE_Zn_INDEX,
   A64_OPID_25004210_mov_SVE_Pd_SVE_Pg4_10_SVE_Pn,
   A64_OPID_25c04000_movs_SVE_Pd_SVE_Pn,
   A64_OPID_25404000_movs_SVE_Pd_SVE_Pg4_10_SVE_Pn,
diff --git a/opcodes/aarch64-tbl.h b/opcodes/aarch64-tbl.h
index 54734292b18..026432a5e25 100644
--- a/opcodes/aarch64-tbl.h
+++ b/opcodes/aarch64-tbl.h
@@ -5262,11 +5262,11 @@ const struct aarch64_opcode aarch64_opcode_table[] =
   _SVE_INSN ("fmov", 0x2539c000, 0xff3fe000, sve_size_hsd, 0, OP2 (SVE_Zd, SVE_FPIMM8), OP_SVE_VU_HSD, F_ALIAS, 0),
   _SVE_INSNC ("fmov", 0x0510c000, 0xff30e000, sve_size_hsd, 0, OP3 (SVE_Zd, SVE_Pg4_16, SVE_FPIMM8), OP_SVE_VMU_HSD, F_ALIAS, C_SCAN_MOVPRFX, 0),
   _SVE_INSN ("mov", 0x04603000, 0xffe0fc00, sve_misc, OP_MOV_Z_Z, OP2 (SVE_Zd, SVE_Zn), OP_SVE_DD, F_ALIAS | F_MISC, 0),
-  _SVE_INSN ("mov", 0x05202000, 0xff20fc00, sve_index, OP_MOV_Z_V, OP2 (SVE_Zd, SVE_VZn), OP_SVE_VV_BHSDQ, F_ALIAS | F_MISC, 0),
+  _SVE_INSN ("mov", 0x05202000, 0xff20fc00, sve_index, OP_MOV_Z_V, OP2 (SVE_Zd, SVE_VZn), OP_SVE_VV_BHSDQ, F_ALIAS | F_P1 | F_MISC, 0),
   _SVE_INSN ("mov", 0x05203800, 0xff3ffc00, sve_size_bhsd, 0, OP2 (SVE_Zd, Rn_SP), OP_SVE_VR_BHSD, F_ALIAS, 0),
   _SVE_INSN ("mov", 0x25804000, 0xfff0c210, sve_misc, OP_MOV_P_P, OP2 (SVE_Pd, SVE_Pn), OP_SVE_BB, F_ALIAS | F_MISC, 0),
   _SVE_INSN ("mov", 0x25804000, 0xfff0c210, sve_misc, OP_MOV_PN_PN, OP2 (SVE_PNd, SVE_PNn), OP_SVE_BB, F_ALIAS | F_PSEUDO | F_MISC, 0),
-  _SVE_INSN ("mov", 0x05202000, 0xff20fc00, sve_index, OP_MOV_Z_Zi, OP2 (SVE_Zd, SVE_Zn_INDEX), OP_SVE_VV_BHSDQ, F_ALIAS | F_MISC, 0),
+  _SVE_INSN ("mov", 0x05202000, 0xff20fc00, sve_index, 0, OP2 (SVE_Zd, SVE_Zn_INDEX), OP_SVE_VV_BHSDQ, F_ALIAS, 0),
   _SVE_INSN ("mov", 0x05c00000, 0xfffc0000, sve_limm, 0, OP2 (SVE_Zd, SVE_LIMM_MOV), OP_SVE_VU_BHSD, F_ALIAS, 0),
   _SVE_INSN ("mov", 0x2538c000, 0xff3fc000, sve_size_bhsd, 0, OP2 (SVE_Zd, SVE_ASIMM), OP_SVE_VU_BHSD, F_ALIAS, 0),
   _SVE_INSNC ("mov", 0x05208000, 0xff3fe000, sve_size_bhsd, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Vn), OP_SVE_VMV_BHSD, F_ALIAS, C_SCAN_MOVPRFX, 0),