[binutils-gdb] aarch64: Update FEAT_TPS and FEAT_TPSP system registers
Alice Carlotti via Binutils-cvs <[email protected]> Fri, 10 Jul 2026 15:18:20 +0000 (GMT)
| Newsgroups | gmane.comp.gnu.binutils.cvs |
|---|---|
| Message-ID | <[email protected]> |
https://sourceware.org/git/gitweb.cgi?p=binutils-gdb.git;h=ffca19ab8e9cf5f57a6ea81a108d9113de9e8336 commit ffca19ab8e9cf5f57a6ea81a108d9113de9e8336 Author: Alice Carlotti <[email protected]> Date: Fri Jul 10 15:51:50 2026 +0100 aarch64: Update FEAT_TPS and FEAT_TPSP system registers The specification has been changed to use individual tpcr* registers, instead of the original tpmin*/tpmax* pairs. Diff: --- gas/testsuite/gas/aarch64/sysreg/sysreg-12.d | 48 ++++++++++------------------ gas/testsuite/gas/aarch64/sysreg/sysreg-12.s | 24 +++++--------- opcodes/aarch64-sys-regs.def | 24 +++++--------- 3 files changed, 32 insertions(+), 64 deletions(-) diff --git a/gas/testsuite/gas/aarch64/sysreg/sysreg-12.d b/gas/testsuite/gas/aarch64/sysreg/sysreg-12.d index 595a6ae020f..a08ec9a3768 100644 --- a/gas/testsuite/gas/aarch64/sysreg/sysreg-12.d +++ b/gas/testsuite/gas/aarch64/sysreg/sysreg-12.d @@ -6,35 +6,19 @@ [^:]+: 0+ <.*>: -.*: d51b22a0 msr tpmax0_el0, x0 -.*: d53b22a0 mrs x0, tpmax0_el0 -.*: d51822a0 msr tpmax0_el1, x0 -.*: d53822a0 mrs x0, tpmax0_el1 -.*: d51d22a0 msr tpmax0_el12, x0 -.*: d53d22a0 mrs x0, tpmax0_el12 -.*: d51c22a0 msr tpmax0_el2, x0 -.*: d53c22a0 mrs x0, tpmax0_el2 -.*: d51b22e0 msr tpmax1_el0, x0 -.*: d53b22e0 mrs x0, tpmax1_el0 -.*: d51822e0 msr tpmax1_el1, x0 -.*: d53822e0 mrs x0, tpmax1_el1 -.*: d51d22e0 msr tpmax1_el12, x0 -.*: d53d22e0 mrs x0, tpmax1_el12 -.*: d51c22e0 msr tpmax1_el2, x0 -.*: d53c22e0 mrs x0, tpmax1_el2 -.*: d51b2280 msr tpmin0_el0, x0 -.*: d53b2280 mrs x0, tpmin0_el0 -.*: d5182280 msr tpmin0_el1, x0 -.*: d5382280 mrs x0, tpmin0_el1 -.*: d51d2280 msr tpmin0_el12, x0 -.*: d53d2280 mrs x0, tpmin0_el12 -.*: d51c2280 msr tpmin0_el2, x0 -.*: d53c2280 mrs x0, tpmin0_el2 -.*: d51b22c0 msr tpmin1_el0, x0 -.*: d53b22c0 mrs x0, tpmin1_el0 -.*: d51822c0 msr tpmin1_el1, x0 -.*: d53822c0 mrs x0, tpmin1_el1 -.*: d51d22c0 msr tpmin1_el12, x0 -.*: d53d22c0 mrs x0, tpmin1_el12 -.*: d51c22c0 msr tpmin1_el2, x0 -.*: d53c22c0 mrs x0, tpmin1_el2 +.*: d51b2280 msr tpcr0_el0, x0 +.*: d53b2280 mrs x0, tpcr0_el0 +.*: d5182280 msr tpcr0_el1, x0 +.*: d5382280 mrs x0, tpcr0_el1 +.*: d51d2280 msr tpcr0_el12, x0 +.*: d53d2280 mrs x0, tpcr0_el12 +.*: d51c2280 msr tpcr0_el2, x0 +.*: d53c2280 mrs x0, tpcr0_el2 +.*: d51b22a0 msr tpcr1_el0, x0 +.*: d53b22a0 mrs x0, tpcr1_el0 +.*: d51822a0 msr tpcr1_el1, x0 +.*: d53822a0 mrs x0, tpcr1_el1 +.*: d51d22a0 msr tpcr1_el12, x0 +.*: d53d22a0 mrs x0, tpcr1_el12 +.*: d51c22a0 msr tpcr1_el2, x0 +.*: d53c22a0 mrs x0, tpcr1_el2 diff --git a/gas/testsuite/gas/aarch64/sysreg/sysreg-12.s b/gas/testsuite/gas/aarch64/sysreg/sysreg-12.s index 02a55fc788d..50da4989cbc 100644 --- a/gas/testsuite/gas/aarch64/sysreg/sysreg-12.s +++ b/gas/testsuite/gas/aarch64/sysreg/sysreg-12.s @@ -1,18 +1,10 @@ .include "sysreg-test-utils.inc" - rw_sys_reg tpmax0_el0 - rw_sys_reg tpmax0_el1 - rw_sys_reg tpmax0_el12 - rw_sys_reg tpmax0_el2 - rw_sys_reg tpmax1_el0 - rw_sys_reg tpmax1_el1 - rw_sys_reg tpmax1_el12 - rw_sys_reg tpmax1_el2 - rw_sys_reg tpmin0_el0 - rw_sys_reg tpmin0_el1 - rw_sys_reg tpmin0_el12 - rw_sys_reg tpmin0_el2 - rw_sys_reg tpmin1_el0 - rw_sys_reg tpmin1_el1 - rw_sys_reg tpmin1_el12 - rw_sys_reg tpmin1_el2 + rw_sys_reg tpcr0_el0 + rw_sys_reg tpcr0_el1 + rw_sys_reg tpcr0_el12 + rw_sys_reg tpcr0_el2 + rw_sys_reg tpcr1_el0 + rw_sys_reg tpcr1_el1 + rw_sys_reg tpcr1_el12 + rw_sys_reg tpcr1_el2 diff --git a/opcodes/aarch64-sys-regs.def b/opcodes/aarch64-sys-regs.def index 1efbc3f3de5..f6f2bc7eb92 100644 --- a/opcodes/aarch64-sys-regs.def +++ b/opcodes/aarch64-sys-regs.def @@ -1357,6 +1357,14 @@ SYSREG ("tindex_el2", CPENC (3,4,4,0,3), 0, AARCH64_FEATURE (POE2)) SYSREG ("tindex_el3", CPENC (3,6,4,0,3), 0, AARCH64_FEATURE (POE2)) SYSREG ("tlbididr_el1", CPENC (3,0,10,4,6), F_REG_READ, AARCH64_FEATURE (TLBID)) + SYSREG ("tpcr0_el0", CPENC (3,3,2,2,4), 0, AARCH64_NO_FEATURES) + SYSREG ("tpcr0_el1", CPENC (3,0,2,2,4), 0, AARCH64_NO_FEATURES) + SYSREG ("tpcr0_el12", CPENC (3,5,2,2,4), 0, AARCH64_NO_FEATURES) + SYSREG ("tpcr0_el2", CPENC (3,4,2,2,4), 0, AARCH64_NO_FEATURES) + SYSREG ("tpcr1_el0", CPENC (3,3,2,2,5), 0, AARCH64_NO_FEATURES) + SYSREG ("tpcr1_el1", CPENC (3,0,2,2,5), 0, AARCH64_NO_FEATURES) + SYSREG ("tpcr1_el12", CPENC (3,5,2,2,5), 0, AARCH64_NO_FEATURES) + SYSREG ("tpcr1_el2", CPENC (3,4,2,2,5), 0, AARCH64_NO_FEATURES) SYSREG ("tpidr2_el0", CPENC (3,3,13,0,5), 0, AARCH64_FEATURE (SME)) SYSREG ("tpidr3_el0", CPENC (3,3,13,0,0), 0, AARCH64_FEATURE (POE2)) SYSREG ("tpidr3_el1", CPENC (3,0,13,0,0), 0, AARCH64_FEATURE (POE2)) @@ -1368,22 +1376,6 @@ SYSREG ("tpidr_el2", CPENC (3,4,13,0,2), 0, AARCH64_NO_FEATURES) SYSREG ("tpidr_el3", CPENC (3,6,13,0,2), 0, AARCH64_NO_FEATURES) SYSREG ("tpidrro_el0", CPENC (3,3,13,0,3), 0, AARCH64_NO_FEATURES) - SYSREG ("tpmax0_el0", CPENC (3,3,2,2,5), 0, AARCH64_NO_FEATURES) - SYSREG ("tpmax0_el1", CPENC (3,0,2,2,5), 0, AARCH64_NO_FEATURES) - SYSREG ("tpmax0_el12", CPENC (3,5,2,2,5), 0, AARCH64_NO_FEATURES) - SYSREG ("tpmax0_el2", CPENC (3,4,2,2,5), 0, AARCH64_NO_FEATURES) - SYSREG ("tpmax1_el0", CPENC (3,3,2,2,7), 0, AARCH64_NO_FEATURES) - SYSREG ("tpmax1_el1", CPENC (3,0,2,2,7), 0, AARCH64_NO_FEATURES) - SYSREG ("tpmax1_el12", CPENC (3,5,2,2,7), 0, AARCH64_NO_FEATURES) - SYSREG ("tpmax1_el2", CPENC (3,4,2,2,7), 0, AARCH64_NO_FEATURES) - SYSREG ("tpmin0_el0", CPENC (3,3,2,2,4), 0, AARCH64_NO_FEATURES) - SYSREG ("tpmin0_el1", CPENC (3,0,2,2,4), 0, AARCH64_NO_FEATURES) - SYSREG ("tpmin0_el12", CPENC (3,5,2,2,4), 0, AARCH64_NO_FEATURES) - SYSREG ("tpmin0_el2", CPENC (3,4,2,2,4), 0, AARCH64_NO_FEATURES) - SYSREG ("tpmin1_el0", CPENC (3,3,2,2,6), 0, AARCH64_NO_FEATURES) - SYSREG ("tpmin1_el1", CPENC (3,0,2,2,6), 0, AARCH64_NO_FEATURES) - SYSREG ("tpmin1_el12", CPENC (3,5,2,2,6), 0, AARCH64_NO_FEATURES) - SYSREG ("tpmin1_el2", CPENC (3,4,2,2,6), 0, AARCH64_NO_FEATURES) SYSREG ("trbbaser_el1", CPENC (3,0,9,11,2), 0, AARCH64_FEATURE (V9A)) /* TRBE */ SYSREG ("trbidr_el1", CPENC (3,0,9,11,7), F_REG_READ, AARCH64_FEATURE (V9A)) /* TRBE */ SYSREG ("trblimitr_el1", CPENC (3,0,9,11,0), 0, AARCH64_FEATURE (V9A)) /* TRBE */