[binutils-gdb] RISC-V: add dedicated vector arithmetic .insn forms
Jan Beulich via Binutils-cvs <[email protected]> Fri, 24 Jul 2026 06:21:30 +0000 (GMT)
| Newsgroups | gmane.comp.gnu.binutils.cvs |
|---|---|
| Message-ID | <[email protected]> |
https://sourceware.org/git/gitweb.cgi?p=3Dbinutils-gdb.git;h=3D47c4332d04be= e3baaca5f6872e127112b5c2da88 commit 47c4332d04bee3baaca5f6872e127112b5c2da88 Author: Jan Beulich <[email protected]> Date: Fri Jul 24 08:14:29 2026 +0200 RISC-V: add dedicated vector arithmetic .insn forms =20 As .insn documentation states, using the available .insn forms can be a little challenging. For OP_V and OP_VE, help the situation by providing= a few more dedicated forms. =20 Reviewed-by: Jiawei <[email protected]> Diff: --- gas/config/tc-riscv.c | 5 +++ gas/testsuite/gas/riscv/insn-dwarf.d | 62 ++++++++++++++++++++++----------= ---- gas/testsuite/gas/riscv/insn-na.d | 14 ++++++++ gas/testsuite/gas/riscv/insn.d | 14 ++++++++ gas/testsuite/gas/riscv/insn.s | 18 +++++++++++ include/opcode/riscv.h | 3 ++ opcodes/riscv-opc.c | 11 +++++++ 7 files changed, 103 insertions(+), 24 deletions(-) diff --git a/gas/config/tc-riscv.c b/gas/config/tc-riscv.c index 0f3283cbb96..946bc4a0227 100644 --- a/gas/config/tc-riscv.c +++ b/gas/config/tc-riscv.c @@ -1633,6 +1633,7 @@ validate_riscv_insn (const struct riscv_opcode *opc, = int length) switch (*++oparg) { case '7': USE_BITS (OP_MASK_FUNCT7, OP_SH_FUNCT7); break; + case '6': USE_BITS (OP_MASK_FUNCT6, OP_SH_FUNCT6); break; case '3': USE_BITS (OP_MASK_FUNCT3, OP_SH_FUNCT3); break; case '2': USE_BITS (OP_MASK_FUNCT2, OP_SH_FUNCT2); break; default: @@ -3868,6 +3869,10 @@ riscv_ip (char *str, struct riscv_cl_insn *ip, expre= ssionS *imm_expr, INSERT_OPERAND (FUNCT7, *ip, imm_expr->X_add_number); break; =20 + case 6: + INSERT_OPERAND (FUNCT6, *ip, imm_expr->X_add_number); + break; + case 3: INSERT_OPERAND (FUNCT3, *ip, imm_expr->X_add_number); break; diff --git a/gas/testsuite/gas/riscv/insn-dwarf.d b/gas/testsuite/gas/riscv= /insn-dwarf.d index d6c6e6e095e..16a058c50c5 100644 --- a/gas/testsuite/gas/riscv/insn-dwarf.d +++ b/gas/testsuite/gas/riscv/insn-dwarf.d @@ -60,28 +60,42 @@ insn.s +53 +0x9a.* insn.s +54 +0x9e.* insn.s +55 +0xa2.* insn.s +57 +0xa6.* -insn.s +59 +0xaa.* -insn.s +60 +0xac.* -insn.s +61 +0xb0.* -insn.s +62 +0xb6.* -insn.s +63 +0xbe.* -insn.s +64 +0xc8.* -insn.s +65 +0xd4.* -insn.s +66 +0xea.* -insn.s +67 +0xec.* -insn.s +68 +0xf0.* -insn.s +69 +0xf6.* -insn.s +70 +0xfe.* -insn.s +71 +0x108.* -insn.s +72 +0x114.* -insn.s +74 +0x12a.* -insn.s +75 +0x134.* -insn.s +76 +0x13e.* -insn.s +77 +0x154.* -insn.s +78 +0x16a.* -insn.s +79 +0x180.* -insn.s +80 +0x196.* -insn.s +81 +0x1ac.* -insn.s +83 +0x1c2.* -insn.s +- +0x1c6 +insn.s +61 +0xaa.* +insn.s +62 +0xae.* +insn.s +63 +0xb2.* +insn.s +64 +0xb6.* +insn.s +65 +0xba.* +insn.s +66 +0xbe.* +insn.s +67 +0xc2.* +insn.s +68 +0xc6.* +insn.s +69 +0xca.* +insn.s +70 +0xce.* +insn.s +71 +0xd2.* +insn.s +72 +0xd6.* +insn.s +73 +0xda.* +insn.s +74 +0xde.* +insn.s +77 +0xe2.* +insn.s +78 +0xe4.* +insn.s +79 +0xe8.* +insn.s +80 +0xee.* +insn.s +81 +0xf6.* +insn.s +82 +0x100.* +insn.s +83 +0x10c.* +insn.s +84 +0x122.* +insn.s +85 +0x124.* +insn.s +86 +0x128.* +insn.s +87 +0x12e.* +insn.s +88 +0x136.* +insn.s +89 +0x140.* +insn.s +90 +0x14c.* +insn.s +92 +0x162.* +insn.s +93 +0x16c.* +insn.s +94 +0x176.* +insn.s +95 +0x18c.* +insn.s +96 +0x1a2.* +insn.s +97 +0x1b8.* +insn.s +98 +0x1ce.* +insn.s +99 +0x1e4.* +insn.s +101 +0x1fa.* +insn.s +- +0x1fe #pass diff --git a/gas/testsuite/gas/riscv/insn-na.d b/gas/testsuite/gas/riscv/in= sn-na.d index 47d12974af9..6646ddcffdc 100644 --- a/gas/testsuite/gas/riscv/insn-na.d +++ b/gas/testsuite/gas/riscv/insn-na.d @@ -59,6 +59,20 @@ Disassembly of section .text: [^:]+:[ ]+00c58533[ ]+add[ ]+a0,a1,a2 [^:]+:[ ]+00c58533[ ]+add[ ]+a0,a1,a2 [^:]+:[ ]+022180d7[ ]+vadd\.vv[ ]+v1,v2,v3 +[^:]+:[ ]+2c2081d7[ ]+vxor\.vv[ ]+v3,v2,v1,v0\.t +[^:]+:[ ]+182091d7[ ]+vfmax\.vv[ ]+v3,v2,v1,v0\.t +[^:]+:[ ]+fc1111d7[ ]+vfwnmsac\.vv[ ]+v3,v2,v1,v0\.t +[^:]+:[ ]+422010d7[ ]+vfmv\.f\.s[ ]+ft1,v2 +[^:]+:[ ]+7a20a1d7[ ]+vmnor\.mm[ ]+v3,v2,v1 +[^:]+:[ ]+422020d7[ ]+vmv\.x\.s[ ]+ra,v2 +[^:]+:[ ]+8220a1f7[ ]+vsm3me\.vv[ ]+v3,v2,v1 +[^:]+:[ ]+2c20b1d7[ ]+vxor\.vi[ ]+v3,v2,1,v0\.t +[^:]+:[ ]+2c20c1d7[ ]+vxor\.vx[ ]+v3,v2,ra,v0\.t +[^:]+:[ ]+1820d1d7[ ]+vfmax\.vf[ ]+v3,v2,ft1,v0\.t +[^:]+:[ ]+fc1151d7[ ]+vfwnmsac\.vf[ ]+v3,ft2,v1,v0\.t +[^:]+:[ ]+420150d7[ ]+vfmv\.s\.f[ ]+v1,ft2 +[^:]+:[ ]+bc1161d7[ ]+vnmsac\.vx[ ]+v3,sp,v1,v0\.t +[^:]+:[ ]+420160d7[ ]+vmv\.s\.x[ ]+v1,sp [^:]+:[ ]+0001[ ]+c\.addi[ ]+zero,0 [^:]+:[ ]+00000013[ ]+addi[ ]+zero,zero,0 [^:]+:[ ]+001f 0000 0000[ ].* diff --git a/gas/testsuite/gas/riscv/insn.d b/gas/testsuite/gas/riscv/insn.d index 7ffb4e254ce..a06350e60dd 100644 --- a/gas/testsuite/gas/riscv/insn.d +++ b/gas/testsuite/gas/riscv/insn.d @@ -70,6 +70,20 @@ Disassembly of section .text: [^:]+:[ ]+00c58533[ ]+add[ ]+a0,a1,a2 [^:]+:[ ]+00c58533[ ]+add[ ]+a0,a1,a2 [^:]+:[ ]+022180d7[ ]+vadd\.vv[ ]+v1,v2,v3 +[^:]+:[ ]+2c2081d7[ ]+vxor\.vv[ ]+v3,v2,v1,v0\.t +[^:]+:[ ]+182091d7[ ]+vfmax\.vv[ ]+v3,v2,v1,v0\.t +[^:]+:[ ]+fc1111d7[ ]+vfwnmsac\.vv[ ]+v3,v2,v1,v0\.t +[^:]+:[ ]+422010d7[ ]+vfmv\.f\.s[ ]+ft1,v2 +[^:]+:[ ]+7a20a1d7[ ]+vmnor\.mm[ ]+v3,v2,v1 +[^:]+:[ ]+422020d7[ ]+vmv\.x\.s[ ]+ra,v2 +[^:]+:[ ]+8220a1f7[ ]+vsm3me\.vv[ ]+v3,v2,v1 +[^:]+:[ ]+2c20b1d7[ ]+vxor\.vi[ ]+v3,v2,1,v0\.t +[^:]+:[ ]+2c20c1d7[ ]+vxor\.vx[ ]+v3,v2,ra,v0\.t +[^:]+:[ ]+1820d1d7[ ]+vfmax\.vf[ ]+v3,v2,ft1,v0\.t +[^:]+:[ ]+fc1151d7[ ]+vfwnmsac\.vf[ ]+v3,ft2,v1,v0\.t +[^:]+:[ ]+420150d7[ ]+vfmv\.s\.f[ ]+v1,ft2 +[^:]+:[ ]+bc1161d7[ ]+vnmsac\.vx[ ]+v3,sp,v1,v0\.t +[^:]+:[ ]+420160d7[ ]+vmv\.s\.x[ ]+v1,sp [^:]+:[ ]+0001[ ]+nop [^:]+:[ ]+00000013[ ]+nop [^:]+:[ ]+001f 0000 0000[ ].* diff --git a/gas/testsuite/gas/riscv/insn.s b/gas/testsuite/gas/riscv/insn.s index 4f72d5be8f5..322db8bfcf4 100644 --- a/gas/testsuite/gas/riscv/insn.s +++ b/gas/testsuite/gas/riscv/insn.s @@ -56,6 +56,24 @@ target: =20 .insn r OP_V, 0, 1, x1, x3, x2 =20 + .option push + .option arch, +v,+zvksh # the latter only for disassembly + .insn ivv OP_V, 0x0b, v3, v2, v1, v0.t + .insn fvv OP_V, 0x06, v3, v2, v1, v0.t + .insn fvv OP_V, 0x3f, v3, v1, v2, v0.t + .insn fvv OP_V, 0x10, f1, v2, v0 # last operand is opcode + .insn mvv OP_V, 0x1e, v3, v2, v1 + .insn mvv OP_V, 0x10, x1, v2, v0 # last operand is opcode + .insn mvv OP_VE, 0x20, v3, v2, v1 + .insn ivi OP_V, 0x0b, v3, v2, 1, v0.t + .insn ivx OP_V, 0x0b, v3, v2, x1, v0.t + .insn fvf OP_V, 0x06, v3, v2, f1, v0.t + .insn fvf OP_V, 0x3f, v3, v1, f2, v0.t + .insn fvf OP_V, 0x10, v1, v0, f2 # middle operand is opcode + .insn mvx OP_V, 0x2f, v3, v1, x2, v0.t + .insn mvx OP_V, 0x10, v1, v0, x2 # middle operand is opcode + .option pop + .insn 0x0001 .insn 0x00000013 .insn 0x0000001f diff --git a/include/opcode/riscv.h b/include/opcode/riscv.h index f500b877ca6..e79c17ea60a 100644 --- a/include/opcode/riscv.h +++ b/include/opcode/riscv.h @@ -354,6 +354,9 @@ static inline unsigned int riscv_insn_length (insn_t in= sn) =20 /* RVV fields. */ =20 +#define OP_MASK_FUNCT6 0x3fU +#define OP_SH_FUNCT6 26 + #define OP_MASK_VD 0x1f #define OP_SH_VD 7 #define OP_MASK_VS1 0x1f diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c index d7342075f4e..e5bca266878 100644 --- a/opcodes/riscv-opc.c +++ b/opcodes/riscv-opc.c @@ -3760,6 +3760,17 @@ const struct riscv_opcode riscv_insn_types[] =3D {"j", 0, INSN_CLASS_I, "O7,d,a", 0, 0, NULL, 0 }, {"j", 0, INSN_CLASS_F, "O7,D,a", 0, 0, NULL, 0 }, =20 +{"ivv", 0, INSN_CLASS_V, "O7,F6,Vd,Vt,VsVm", 0x0000, 0x7000, NUL= L, 0 }, +{"fvv", 0, INSN_CLASS_ZVEF, "O7,F6,Vd,Vt,VsVm", 0x1000, 0x7000, NUL= L, 0 }, +{"fvv", 0, INSN_CLASS_ZVEF, "O7,F6,D,Vt,VsVm", 0x1000, 0x7000, NUL= L, 0 }, +{"mvv", 0, INSN_CLASS_V, "O7,F6,Vd,Vt,VsVm", 0x2000, 0x7000, NUL= L, 0 }, +{"mvv", 0, INSN_CLASS_V, "O7,F6,d,Vt,VsVm", 0x2000, 0x7000, NUL= L, 0 }, +{"ivi", 0, INSN_CLASS_V, "O7,F6,Vd,Vt,ViVm", 0x3000, 0x7000, NUL= L, 0 }, +{"ivx", 0, INSN_CLASS_V, "O7,F6,Vd,Vt,sVm", 0x4000, 0x7000, NUL= L, 0 }, +{"fvf", 0, INSN_CLASS_ZVEF, "O7,F6,Vd,Vt,SVm", 0x5000, 0x7000, NUL= L, 0 }, +{"mvx", 0, INSN_CLASS_V, "O7,F6,Vd,Vt,sVm", 0x6000, 0x7000, NUL= L, 0 }, +{"mvx", 0, INSN_CLASS_V, "O7,F6,d,Vt,sVm", 0x6000, 0x7000, NUL= L, 0 }, + {"cr", 0, INSN_CLASS_ZCA, "O2,CF4,d,CV", 0, 0, NULL, 0 }, {"cr", 0, INSN_CLASS_ZCF, "O2,CF4,D,CV", 0, 0, NULL, 0 }, {"cr", 0, INSN_CLASS_ZCF, "O2,CF4,d,CT", 0, 0, NULL, 0 },