[binutils-gdb] bfd/RISC-V: Zvfbfwma implies Zvfbfmin

https://sourceware.org/git/gitweb.cgi?p=3Dbinutils-gdb.git;h=3D6427be862c76=
d8f82ceffd2fff3cfa6705d0d93a

commit 6427be862c76d8f82ceffd2fff3cfa6705d0d93a
Author: Jan Beulich <[email protected]>
Date:   Fri Jul 24 08:19:27 2026 +0200

    bfd/RISC-V: Zvfbfwma implies Zvfbfmin
   =20
    This is pretty clear from the spec.

Diff:
---
 bfd/elfxx-riscv.c               | 2 +-
 gas/testsuite/gas/riscv/imply.d | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c
index c3cb4197ba8..4f13976bb7e 100644
--- a/bfd/elfxx-riscv.c
+++ b/bfd/elfxx-riscv.c
@@ -1237,7 +1237,7 @@ static const struct riscv_implicit_subset riscv_impli=
cit_subsets[] =3D
   {"zvabd", "+zve32x", check_implicit_always},
   {"zvfh", "+zvfhmin,+zfhmin", check_implicit_always},
   {"zvfhmin", "+zve32f", check_implicit_always},
-  {"zvfbfwma", "+zve32f,+zfbfmin", check_implicit_always},
+  {"zvfbfwma", "+zfbfmin,+zvfbfmin", check_implicit_always},
   {"zvfbfmin", "+zve32f", check_implicit_always},
   {"zvfbdota32f", "+zve32f", check_implicit_always},
   {"zvfqwbdota8f", "+zve32f", check_implicit_always},
diff --git a/gas/testsuite/gas/riscv/imply.d b/gas/testsuite/gas/riscv/impl=
y.d
index 9fd6102a056..2de5f249600 100644
--- a/gas/testsuite/gas/riscv/imply.d
+++ b/gas/testsuite/gas/riscv/imply.d
@@ -27,7 +27,7 @@ SYMBOL TABLE:
 [0-9a-f]+ l       .text	0+000 \$xrv32i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p=
0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0
 [0-9a-f]+ l       .text	0+000 \$xrv32i2p1_f2p2_zicsr2p0_zfhmin1p0_zve32f1p=
0_zve32x1p0_zvfh1p0_zvfhmin1p0_zvl32b1p0
 [0-9a-f]+ l       .text	0+000 \$xrv32i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p=
0_zvfhmin1p0_zvl32b1p0
-[0-9a-f]+ l       .text	0+000 \$xrv32i2p1_f2p2_zicsr2p0_zfbfmin1p0_zfhmin1=
p0_zve32f1p0_zve32x1p0_zvfbfwma1p0_zvl32b1p0
+[0-9a-f]+ l       .text	0+000 \$xrv32i2p1_f2p2_zicsr2p0_zfbfmin1p0_zfhmin1=
p0_zve32f1p0_zve32x1p0_zvfbfmin1p0_zvfbfwma1p0_zvl32b1p0
 [0-9a-f]+ l       .text	0+000 \$xrv32i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p=
0_zvfbfmin1p0_zvl32b1p0
 [0-9a-f]+ l       .text	0+000 \$xrv32i2p1_f2p2_d2p2_zicsr2p0_zve32f1p0_zve=
32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl32b1p0_zvl64b1p0
 [0-9a-f]+ l       .text	0+000 \$xrv32i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p=
0_zve64f1p0_zve64x1p0_zvl32b1p0_zvl64b1p0