[binutils-gdb] x86: simplify expressions checking register operand properties

https://sourceware.org/git/gitweb.cgi?p=3Dbinutils-gdb.git;h=3D0ff3761daecc=
09c79784674ff78ebb51844390e0

commit 0ff3761daecc09c79784674ff78ebb51844390e0
Author: Jan Beulich <[email protected]>
Date:   Fri Jul 24 08:23:23 2026 +0200

    x86: simplify expressions checking register operand properties
   =20
    While parsing operands, i.types[] is set alongside i.op[].regs->reg_typ=
e.
    Therefore we can avoid a level of indirection by preferring the former
    over the latter when checking operand properties.

Diff:
---
 gas/config/tc-i386.c | 72 ++++++++++++++++++++++++++----------------------=
----
 1 file changed, 36 insertions(+), 36 deletions(-)

diff --git a/gas/config/tc-i386.c b/gas/config/tc-i386.c
index 7ace19e4a9e..2853f0c76e7 100644
--- a/gas/config/tc-i386.c
+++ b/gas/config/tc-i386.c
@@ -5050,7 +5050,7 @@ optimize_encoding (void)
        */
       if (flag_code =3D=3D CODE_64BIT && i.prefix[ADDR_PREFIX])
 	{
-	  if (!i.op[1].regs->reg_type.bitfield.word)
+	  if (!i.types[1].bitfield.word)
 	    i.tm.opcode_modifier.size =3D SIZE32;
 	  i.prefix[ADDR_PREFIX] =3D 0;
 	}
@@ -5065,15 +5065,15 @@ optimize_encoding (void)
 	      /* Don't transform a relocation to a 16-bit one.  */
 	      if (i.op[0].disps
 		  && i.op[0].disps->X_op !=3D O_constant
-		  && i.op[1].regs->reg_type.bitfield.word)
+		  && i.types[1].bitfield.word)
 		return;
=20
-	      if (!i.op[1].regs->reg_type.bitfield.qword
+	      if (!i.types[1].bitfield.qword
 		  || i.tm.opcode_modifier.size =3D=3D SIZE32)
 		{
 		  i.tm.base_opcode =3D 0xb8;
 		  i.tm.opcode_modifier.modrm =3D 0;
-		  if (!i.op[1].regs->reg_type.bitfield.word)
+		  if (!i.types[1].bitfield.word)
 		    i.types[0].bitfield.imm32 =3D 1;
 		  else
 		    {
@@ -5097,28 +5097,28 @@ optimize_encoding (void)
 		   && i.op[0].disps->X_op !=3D O_constant
 		   && ((!i.prefix[ADDR_PREFIX])
 		       !=3D (flag_code =3D=3D CODE_32BIT
-			   ? i.op[1].regs->reg_type.bitfield.dword
-			   : i.op[1].regs->reg_type.bitfield.word)))
+			   ? i.types[1].bitfield.dword
+			   : i.types[1].bitfield.word)))
 	    return;
 	  /* In 16-bit mode converting LEA with 16-bit addressing and a 32-bit
 	     destination is going to grow encoding size.  */
 	  else if (flag_code =3D=3D CODE_16BIT
 		   && (optimize <=3D 1 || optimize_for_space)
 		   && !i.prefix[ADDR_PREFIX]
-		   && i.op[1].regs->reg_type.bitfield.dword)
+		   && i.types[1].bitfield.dword)
 	    return;
 	  else
 	    {
 	      i.tm.base_opcode =3D 0xb8;
 	      i.tm.opcode_modifier.modrm =3D 0;
-	      if (i.op[1].regs->reg_type.bitfield.dword)
+	      if (i.types[1].bitfield.dword)
 		i.types[0].bitfield.imm32 =3D 1;
 	      else
 		i.types[0].bitfield.imm16 =3D 1;
=20
 	      if (i.op[0].disps
 		  && i.op[0].disps->X_op =3D=3D O_constant
-		  && i.op[1].regs->reg_type.bitfield.dword
+		  && i.types[1].bitfield.dword
 		  /* NB: Add () to !i.prefix[ADDR_PREFIX] to silence
 		     GCC 5. */
 		  && (!i.prefix[ADDR_PREFIX]) !=3D (flag_code =3D=3D CODE_32BIT))
@@ -5156,7 +5156,7 @@ optimize_encoding (void)
 	    return;
=20
 	  if (addr_reg->reg_type.bitfield.word
-	      && i.op[1].regs->reg_type.bitfield.dword)
+	      && i.types[1].bitfield.dword)
 	    {
 	      if (flag_code !=3D CODE_32BIT)
 		return;
@@ -5167,7 +5167,7 @@ optimize_encoding (void)
 	    i.tm.base_opcode =3D 0x8b;
=20
 	  if (addr_reg->reg_type.bitfield.dword
-	      && i.op[1].regs->reg_type.bitfield.qword)
+	      && i.types[1].bitfield.qword)
 	    i.tm.opcode_modifier.size =3D SIZE32;
=20
 	  i.op[0].regs =3D addr_reg;
@@ -5828,7 +5828,7 @@ optimize_encoding (void)
 	   && i.operands =3D=3D i.reg_operands
 	   && i.tm.opcode_modifier.vex
 	   && !(i.op[0].regs->reg_flags & RegRex)
-	   && i.op[1].regs->reg_type.bitfield.xmmword
+	   && i.types[1].bitfield.xmmword
 	   && pp.encoding !=3D encoding_vex3)
     {
       /* Optimize: -Os:
@@ -6894,7 +6894,7 @@ x86_check_tls_relocation (enum bfd_reloc_code_real r_=
type)
 	return x86_tls_error_no_base_reg;
       if (i.base_reg->reg_type.bitfield.instance !=3D RegB)
 	return x86_tls_error_ebx;
-      if (!i.op[1].regs->reg_type.bitfield.dword)
+      if (!i.types[1].bitfield.dword)
 	return x86_tls_error_dest_32bit_reg_size;
       break;
=20
@@ -6907,9 +6907,9 @@ x86_check_tls_relocation (enum bfd_reloc_code_real r_=
type)
        */
       if (i.tm.mnem_off !=3D MN_lea)
 	return x86_tls_error_insn;
-      if (i.op[1].regs->reg_type.bitfield.instance !=3D Accum)
+      if (i.types[1].bitfield.instance !=3D Accum)
 	return x86_tls_error_dest_eax;
-      if (!i.op[1].regs->reg_type.bitfield.dword)
+      if (!i.types[1].bitfield.dword)
 	return x86_tls_error_dest_32bit_reg_size;
       if (i.index_reg)
 	{
@@ -6944,9 +6944,9 @@ x86_check_tls_relocation (enum bfd_reloc_code_real r_=
type)
 	return x86_tls_error_no_base_reg;
       if (i.base_reg->reg_type.bitfield.instance =3D=3D Accum)
 	return x86_tls_error_eax;
-      if (i.op[1].regs->reg_type.bitfield.instance !=3D Accum)
+      if (i.types[1].bitfield.instance !=3D Accum)
 	return x86_tls_error_dest_eax;
-      if (!i.op[1].regs->reg_type.bitfield.dword)
+      if (!i.types[1].bitfield.dword)
 	return x86_tls_error_dest_32bit_reg_size;
       break;
=20
@@ -6971,11 +6971,11 @@ x86_check_tls_relocation (enum bfd_reloc_code_real =
r_type)
 	return x86_tls_error_rip;
       if (x86_elf_abi =3D=3D X86_64_ABI)
 	{
-	  if (!i.op[1].regs->reg_type.bitfield.qword)
+	  if (!i.types[1].bitfield.qword)
 	    return x86_tls_error_dest_64bit_reg_size;
 	}
-      else if (!i.op[1].regs->reg_type.bitfield.dword
-	       && !i.op[1].regs->reg_type.bitfield.qword)
+      else if (!i.types[1].bitfield.dword
+	       && !i.types[1].bitfield.qword)
 	return x86_tls_error_dest_32bit_or_64bit_reg_size;
 	  break;
=20
@@ -6996,7 +6996,7 @@ x86_check_tls_relocation (enum bfd_reloc_code_real r_=
type)
       if (i.base_reg->reg_num !=3D RegIP
 	  || !i.base_reg->reg_type.bitfield.qword)
 	return x86_tls_error_rip;
-      if (!i.op[1].regs->reg_type.bitfield.qword
+      if (!i.types[1].bitfield.qword
 	  || i.op[1].regs->reg_num !=3D EDI_REG_NUM
 	  || i.op[1].regs->reg_flags)
 	return x86_tls_error_dest_rdi;
@@ -7035,7 +7035,7 @@ x86_check_tls_relocation (enum bfd_reloc_code_real r_=
type)
 	return x86_tls_error_sib;
       if (!i.base_reg->reg_type.bitfield.dword)
 	return x86_tls_error_base_reg_size;
-      if (!i.op[1].regs->reg_type.bitfield.dword)
+      if (!i.types[1].bitfield.dword)
 	return x86_tls_error_dest_32bit_reg_size;
       break;
=20
@@ -7054,7 +7054,7 @@ x86_check_tls_relocation (enum bfd_reloc_code_real r_=
type)
 	return x86_tls_error_opcode;
       if (i.base_reg || i.index_reg)
 	return x86_tls_error_require_no_base_index_reg;
-      if (!i.op[1].regs->reg_type.bitfield.dword)
+      if (!i.types[1].bitfield.dword)
 	return x86_tls_error_dest_32bit_reg_size;
       break;
=20
@@ -7081,11 +7081,11 @@ x86_check_tls_relocation (enum bfd_reloc_code_real =
r_type)
 	return x86_tls_error_rip;
       if (x86_elf_abi =3D=3D X86_64_ABI)
 	{
-	  if (!i.op[i.operands - 1].regs->reg_type.bitfield.qword)
+	  if (!i.types[i.operands - 1].bitfield.qword)
 	    return x86_tls_error_dest_64bit_reg_size;
 	}
-      else if (!i.op[i.operands - 1].regs->reg_type.bitfield.dword
-	       && !i.op[i.operands - 1].regs->reg_type.bitfield.qword)
+      else if (!i.types[i.operands - 1].bitfield.dword
+	       && !i.types[i.operands - 1].bitfield.qword)
 	return x86_tls_error_dest_32bit_or_64bit_reg_size;
       break;
=20
@@ -9983,7 +9983,7 @@ match_template (char mnem_suffix)
 			 legacy-encoded and when no REX prefix is required.  */
 		      || (!check_EgprOperands (t + 1)
 			  && !check_Rex_required ()
-			  && !i.op[i.operands - 1].regs->reg_type.bitfield.qword)))
+			  && !i.types[i.operands - 1].bitfield.qword)))
 		{
 		  if (i.operands > 2 && match_dest_op =3D=3D i.operands - 3)
 		    {
@@ -10595,7 +10595,7 @@ process_suffix (const insn_template *t)
 	  /* The address size override prefix changes the size of the
 	     first operand.  */
 	  if (flag_code =3D=3D CODE_64BIT
-	      && i.op[0].regs->reg_type.bitfield.word)
+	      && i.types[0].bitfield.word)
 	    {
 	      as_bad (_("16-bit addressing unavailable for `%s'"),
 		      insn_name (&i.tm));
@@ -10603,8 +10603,8 @@ process_suffix (const insn_template *t)
 	    }
=20
 	  if ((flag_code =3D=3D CODE_32BIT
-	       ? i.op[0].regs->reg_type.bitfield.word
-	       : i.op[0].regs->reg_type.bitfield.dword)
+	       ? i.types[0].bitfield.word
+	       : i.types[0].bitfield.dword)
 	      && !add_prefix (ADDR_PREFIX_OPCODE))
 	    return 0;
 	}
@@ -10623,8 +10623,8 @@ process_suffix (const insn_template *t)
 	      && i.operands =3D=3D 2
 	      && i.types[1].bitfield.class =3D=3D Reg
 	      && (flag_code =3D=3D CODE_32BIT
-		  ? i.op[1].regs->reg_type.bitfield.word
-		  : i.op[1].regs->reg_type.bitfield.dword)
+		  ? i.types[1].bitfield.word
+		  : i.types[1].bitfield.dword)
 	      && ((i.base_reg =3D=3D NULL && i.index_reg =3D=3D NULL)
 #ifdef OBJ_ELF
 		  || (x86_elf_abi =3D=3D X86_64_X32_ABI
@@ -10652,15 +10652,15 @@ process_suffix (const insn_template *t)
 	      switch (need)
 		{
 		case need_word:
-		  if (i.op[op].regs->reg_type.bitfield.word)
+		  if (i.types[op].bitfield.word)
 		    continue;
 		  break;
 		case need_dword:
-		  if (i.op[op].regs->reg_type.bitfield.dword)
+		  if (i.types[op].bitfield.dword)
 		    continue;
 		  break;
 		case need_qword:
-		  if (i.op[op].regs->reg_type.bitfield.qword)
+		  if (i.types[op].bitfield.qword)
 		    continue;
 		  break;
 		}
@@ -15606,7 +15606,7 @@ i386_att_operand (char *operand_string)
 	 Only another immediate or a GPR may precede it.  */
       if (i.mem_operands || i.reg_operands + i.imm_operands > 1
 	  || (i.reg_operands =3D=3D 1
-	      && i.op[0].regs->reg_type.bitfield.class !=3D Reg))
+	      && i.types[0].bitfield.class !=3D Reg))
 	{
 	  as_bad (_("`%s': misplaced `%s'"),
 		  insn_name (current_templates.start), operand_string);