[PATCH v0 2/4] LoongArch: Do not emit relocation if addsy and subsy are in the same frag
mengqinggang <[email protected]>
| Newsgroups | gmane.comp.gnu.binutils |
|---|---|
| Message-ID | <[email protected]> |
Let relaxed instructions and alignment nops in a single frag.
Do not emit relocation if addsy and subsy are in the same frag.
---
gas/config/tc-loongarch.c | 127 ++++----
gas/testsuite/gas/elf/ehopt0.d | 3 -
gas/testsuite/gas/loongarch/no_thin_add_sub.d | 30 +-
gas/testsuite/gas/loongarch/no_thin_add_sub.s | 1 +
.../gas/loongarch/relax_debug_line.d | 9 +-
gas/testsuite/gas/loongarch/relocs_32.d | 175 +++++------
gas/testsuite/gas/loongarch/relocs_32.s | 11 +-
gas/testsuite/gas/loongarch/relocs_64.d | 291 +++++++++---------
gas/testsuite/gas/loongarch/relocs_64.s | 3 +
.../gas/loongarch/thin_add_sub_relax.d | 20 +-
.../gas/loongarch/thin_add_sub_relax.s | 2 +
ld/testsuite/ld-elf/compressed1d.d | 3 -
12 files changed, 344 insertions(+), 331 deletions(-)
diff --git a/gas/config/tc-loongarch.c b/gas/config/tc-loongarch.c
index d067318ce24..de862f07a6c 100644
--- a/gas/config/tc-loongarch.c
+++ b/gas/config/tc-loongarch.c
@@ -82,6 +82,9 @@ struct loongarch_cl_insn
The macros or instructions expanded from macros do not output register
deprecated warning. */
unsigned int expand_from_macro;
+
+ /* Whether the instruction is linker-relaxable. */
+ bool linker_relax;
};
#ifndef DEFAULT_ARCH
@@ -816,6 +819,7 @@ loongarch_args_parser_can_match_arg_helper (char esc_ch1, char esc_ch2,
ip->reloc_info[ip->reloc_num].type = BFD_RELOC_LARCH_RELAX;
ip->reloc_info[ip->reloc_num].value = const_0;
ip->reloc_num++;
+ ip->linker_relax = true;
}
else
ip->match_now = 0;
@@ -889,6 +893,7 @@ loongarch_args_parser_can_match_arg_helper (char esc_ch1, char esc_ch2,
ip->reloc_info[ip->reloc_num].type = BFD_RELOC_LARCH_RELAX;
ip->reloc_info[ip->reloc_num].value = const_0;
ip->reloc_num++;
+ ip->linker_relax = true;
}
/* Only one register macros (used in normal code model)
@@ -896,8 +901,7 @@ loongarch_args_parser_can_match_arg_helper (char esc_ch1, char esc_ch2,
LARCH_opts.ase_labs and LARCH_opts.ase_gabs are used
to generate the code model of absolute addresses, and
we do not relax this code model. */
- if (LARCH_opts.relax && (ip->expand_from_macro & 1)
- && !(LARCH_opts.ase_labs | LARCH_opts.ase_gabs)
+ if (LARCH_opts.relax
&& (BFD_RELOC_LARCH_PCALA_HI20 == reloc_type
|| BFD_RELOC_LARCH_PCALA_LO12 == reloc_type
|| BFD_RELOC_LARCH_GOT_PC_HI20 == reloc_type
@@ -917,9 +921,19 @@ loongarch_args_parser_can_match_arg_helper (char esc_ch1, char esc_ch2,
|| BFD_RELOC_LARCH_TLS_IE_PCADD_HI20 == reloc_type
|| BFD_RELOC_LARCH_TLS_IE_PCADD_LO12 == reloc_type))
{
- ip->reloc_info[ip->reloc_num].type = BFD_RELOC_LARCH_RELAX;
- ip->reloc_info[ip->reloc_num].value = const_0;
- ip->reloc_num++;
+ /* R_LARCH_RELAX can be emitted by .reloc, so always set
+ link_relax for instructions.
+ For example:
+ .reloc .,R_LARCH_RELAX
+ pcalau12i $r12,%ie_pc_hi20(.LANCHOR0) */
+ ip->linker_relax = true;
+ if ((ip->expand_from_macro & 1)
+ && !(LARCH_opts.ase_labs | LARCH_opts.ase_gabs))
+ {
+ ip->reloc_info[ip->reloc_num].type = BFD_RELOC_LARCH_RELAX;
+ ip->reloc_info[ip->reloc_num].value = const_0;
+ ip->reloc_num++;
+ }
}
break;
}
@@ -1179,7 +1193,14 @@ move_insn (struct loongarch_cl_insn *insn, fragS *frag, long where)
static void
append_fixed_insn (struct loongarch_cl_insn *insn)
{
- /* Ensure the jirl is emitted to the same frag as the pcaddu18i. */
+ /* Start a new frag only used for relaxable instrucntions. */
+ if (LARCH_opts.relax && insn->linker_relax)
+ {
+ frag_wane (frag_now);
+ frag_new (0);
+ }
+
+ /* Ensure pcaddu18i/pcaddu12i + jirl in the same frag. */
if (insn->reloc_info[0].type == BFD_RELOC_LARCH_CALL36
|| insn->reloc_info[0].type == BFD_RELOC_LARCH_CALL30)
frag_grow (8);
@@ -1187,19 +1208,45 @@ append_fixed_insn (struct loongarch_cl_insn *insn)
char *f = frag_more (insn->insn_length);
move_insn (insn, frag_now, f - frag_now->fr_literal);
- if (call_reloc)
+ /* We need to start a new frag after any instruction that can be
+ optimized away or compressed by the linker during relaxation, to prevent
+ the assembler from computing static offsets across such an instruction.
+
+ This is necessary to get correct .eh_frame FDE DW_CFA_advance_loc info.
+ If one cfi_insn_data's two symbols are not in the same frag, it will
+ generate ADD and SUB relocations pairs to calculate DW_CFA_advance_loc.
+ (gas/dw2gencfi.c: output_cfi_insn:
+ if (symbol_get_frag (to) == symbol_get_frag (from)))
+
+ Since the relocations of the normal code model and the extreme code model
+ of the old LE instruction sequence are the same, it is impossible to
+ distinguish which code model it is based on relocation alone, so the
+ extreme code model has to be relaxed. */
+
+ /* End the frag to ensure it only used for relaxable instructions. */
+ if (LARCH_opts.relax && insn->linker_relax
+ && insn->reloc_info[0].type != BFD_RELOC_LARCH_CALL36
+ && insn->reloc_info[0].type != BFD_RELOC_LARCH_CALL30)
+ {
+ frag_wane (frag_now);
+ frag_new (0);
+ }
+
+ /* To ensure pcaddu18i/pcaddu12i + jirl in the same frag.
+ End the frag after the jirl instruction. */
+ if (LARCH_opts.relax && call_reloc)
{
if (strcmp (insn->name, "jirl") == 0)
{
- /* See comment at end of append_fixp_and_insn. */
frag_wane (frag_now);
frag_new (0);
}
call_reloc = 0;
}
- if (insn->reloc_info[0].type == BFD_RELOC_LARCH_CALL36
- || insn->reloc_info[0].type == BFD_RELOC_LARCH_CALL30)
+ if (LARCH_opts.relax
+ && (insn->reloc_info[0].type == BFD_RELOC_LARCH_CALL36
+ || insn->reloc_info[0].type == BFD_RELOC_LARCH_CALL30))
call_reloc = 1;
}
@@ -1269,43 +1316,6 @@ append_fixp_and_insn (struct loongarch_cl_insn *ip)
as_fatal (_("Internal error: not support relax now"));
else
append_fixed_insn (ip);
-
- /* We need to start a new frag after any instruction that can be
- optimized away or compressed by the linker during relaxation, to prevent
- the assembler from computing static offsets across such an instruction.
-
- This is necessary to get correct .eh_frame FDE DW_CFA_advance_loc info.
- If one cfi_insn_data's two symbols are not in the same frag, it will
- generate ADD and SUB relocations pairs to calculate DW_CFA_advance_loc.
- (gas/dw2gencfi.c: output_cfi_insn:
- if (symbol_get_frag (to) == symbol_get_frag (from)))
-
- For macro instructions, only the first instruction expanded from macro
- need to start a new frag.
- Since the relocations of the normal code model and the extreme code model
- of the old LE instruction sequence are the same, it is impossible to
- distinguish which code model it is based on relocation alone, so the
- extreme code model has to be relaxed. */
- if (LARCH_opts.relax
- && (BFD_RELOC_LARCH_PCALA_HI20 == reloc_info[0].type
- || BFD_RELOC_LARCH_GOT_PC_HI20 == reloc_info[0].type
- || BFD_RELOC_LARCH_TLS_LE_HI20_R == reloc_info[0].type
- || BFD_RELOC_LARCH_TLS_LE_ADD_R == reloc_info[0].type
- || BFD_RELOC_LARCH_TLS_LD_PC_HI20 == reloc_info[0].type
- || BFD_RELOC_LARCH_TLS_GD_PC_HI20 == reloc_info[0].type
- || BFD_RELOC_LARCH_TLS_DESC_PC_HI20 == reloc_info[0].type
- || BFD_RELOC_LARCH_TLS_IE_PC_HI20 == reloc_info[0].type
- || BFD_RELOC_LARCH_TLS_LE_HI20 == reloc_info[0].type
- || BFD_RELOC_LARCH_TLS_LE_LO12 == reloc_info[0].type
- || BFD_RELOC_LARCH_TLS_LE64_LO20 == reloc_info[0].type
- || BFD_RELOC_LARCH_TLS_LE64_HI12 == reloc_info[0].type
- || BFD_RELOC_LARCH_GOT_PCADD_HI20 == reloc_info[0].type
- || BFD_RELOC_LARCH_TLS_IE_PCADD_HI20 == reloc_info[0].type
- || BFD_RELOC_LARCH_TLS_DESC_PCADD_HI20 == reloc_info[0].type))
- {
- frag_wane (frag_now);
- frag_new (0);
- }
}
/* Ask helper for returning a malloced c_str or NULL. */
@@ -1588,11 +1598,18 @@ loongarch_force_relocation_sub_local (fixS *fixp, segT sec ATTRIBUTE_UNUSED)
|| (S_GET_SEGMENT (fixp->fx_subsy)->flags & SEC_CODE) == 0));
}
-/* Postpone text-section label subtraction calculation until linking, since
- linker relaxations might change the deltas. */
+/* Postpone text-section label subtraction calculation until linking,
+ since linker relaxations might change the deltas. */
bool
loongarch_force_relocation_sub_same(fixS *fixp ATTRIBUTE_UNUSED, segT sec)
{
+ fragS *add_frag = symbol_get_frag (fixp->fx_addsy);
+ fragS *sub_frag = symbol_get_frag (fixp->fx_subsy);
+
+ /* Not emit relocation if addsy and subsy are in the same frag. */
+ if (add_frag == sub_frag)
+ return false;
+
return LARCH_opts.relax && (sec->flags & SEC_CODE) != 0;
}
@@ -2117,6 +2134,10 @@ loongarch_frag_align_code (int n, int max)
if (align_bytes <= 4)
return true;
+ /* Start a new frag only used for alignment. */
+ frag_wane (frag_now);
+ frag_new (0);
+
/* If max <= 0, ignore max.
If max >= worst_case_bytes, max has no effect.
Similar to gas/write.c relax_segment function rs_align_code case:
@@ -2160,9 +2181,11 @@ loongarch_frag_align_code (int n, int max)
/* Default write NOP for aligned bytes. */
loongarch_make_nops (nops, worst_case_bytes);
- /* We need to start a new frag after the alignment which may be removed by
- the linker, to prevent the assembler from computing static offsets.
- This is necessary to get correct EH info. */
+ /* We need to start a new frag after the alignment which may be
+ removed by the linker, to prevent the assembler from computing
+ static offsets. This is necessary to get correct EH info.
+
+ End the frag to ensure it is only used for alignment. */
frag_wane (frag_now);
frag_new (0);
diff --git a/gas/testsuite/gas/elf/ehopt0.d b/gas/testsuite/gas/elf/ehopt0.d
index 64c5fb5ddc4..a13c4f26e33 100644
--- a/gas/testsuite/gas/elf/ehopt0.d
+++ b/gas/testsuite/gas/elf/ehopt0.d
@@ -1,8 +1,5 @@
#objdump: -s -j .eh_frame
#name: elf ehopt0
-# The loongarch target do not evaluate .eh_frame fde cfa advance loc at assembly time.
-# Because loongarch use add/sub reloc evaluate cfa advance loc, so gas should write 0 to cfa advance loc address.
-#xfail: loongarch*-*
.*: +file format .*
diff --git a/gas/testsuite/gas/loongarch/no_thin_add_sub.d b/gas/testsuite/gas/loongarch/no_thin_add_sub.d
index 614aca71d66..625b8ac97c7 100644
--- a/gas/testsuite/gas/loongarch/no_thin_add_sub.d
+++ b/gas/testsuite/gas/loongarch/no_thin_add_sub.d
@@ -1,24 +1,20 @@
-#as:
+#as: -mrelax
#objdump: -Dr
-.*:[ ]+file format .*
+#...
+.*<.L1>:
+#...
+.*R_LARCH_ADD32[ ]+.L3
+.*R_LARCH_SUB32[ ]+.L1
+.*R_LARCH_ADD32[ ]+.L3
+.*R_LARCH_SUB32[ ]+.L1
-
-Disassembly of section .text:
-
-00000000.* <.L1>:
-[ ]+...
-[ ]+0:[ ]+R_LARCH_ADD32[ ]+.L3
-[ ]+0:[ ]+R_LARCH_SUB32[ ]+.L1
-[ ]+4:[ ]+R_LARCH_ADD32[ ]+.L3
-[ ]+4:[ ]+R_LARCH_SUB32[ ]+.L1
-
-0*00000008[ ]+<.L2>:
+.*<.L2>:
[ ]+...
-[ ]+8:[ ]+R_LARCH_ADD64[ ]+.L3
-[ ]+8:[ ]+R_LARCH_SUB64[ ]+.L2
-[ ]+10:[ ]+R_LARCH_ADD64[ ]+.L3
-[ ]+10:[ ]+R_LARCH_SUB64[ ]+.L2
+.*:[ ]+R_LARCH_ADD64[ ]+.L3
+.*:[ ]+R_LARCH_SUB64[ ]+.L2
+.*:[ ]+R_LARCH_ADD64[ ]+.L3
+.*:[ ]+R_LARCH_SUB64[ ]+.L2
Disassembly[ ]+of[ ]+section[ ]+sx:
diff --git a/gas/testsuite/gas/loongarch/no_thin_add_sub.s b/gas/testsuite/gas/loongarch/no_thin_add_sub.s
index c680168956f..e84da86ea0a 100644
--- a/gas/testsuite/gas/loongarch/no_thin_add_sub.s
+++ b/gas/testsuite/gas/loongarch/no_thin_add_sub.s
@@ -1,5 +1,6 @@
.section .text
.L1:
+ call .text
# add32+sub32
.4byte .L3-.L1
.4byte .L3-.L1
diff --git a/gas/testsuite/gas/loongarch/relax_debug_line.d b/gas/testsuite/gas/loongarch/relax_debug_line.d
index c17813c20ed..7ff44789a99 100644
--- a/gas/testsuite/gas/loongarch/relax_debug_line.d
+++ b/gas/testsuite/gas/loongarch/relax_debug_line.d
@@ -1,12 +1,9 @@
-#as: --gdwarf-5
+#as: --gdwarf-5 -mrelax
#readelf: -r --wide
-#skip: loongarch32-*-*
-Relocation section '\.rela\.debug_line' at offset .* contains 5 entries:
+Relocation section '\.rela\.debug_line' at offset .* contains 3 entries:
#...
0+22.*R_LARCH_32[ \t]+[0-9]+.*
0+2c.*R_LARCH_32[ \t]+[0-9]+.*
-0+36.*R_LARCH_64[ \t]+[0-9]+.*
-0+42.*R_LARCH_ADD16[ \t]+[0-9]+.*
-0+42.*R_LARCH_SUB16[ \t]+[0-9]+.*
+0+36.*R_LARCH_(32|64)[ \t]+[0-9]+.*
#pass
diff --git a/gas/testsuite/gas/loongarch/relocs_32.d b/gas/testsuite/gas/loongarch/relocs_32.d
index c88aef5c4d8..58059513877 100644
--- a/gas/testsuite/gas/loongarch/relocs_32.d
+++ b/gas/testsuite/gas/loongarch/relocs_32.d
@@ -2,124 +2,117 @@
#objdump: -dr
#skip: loongarch64-*-*
-.*:[ ]+file format .*
-
-
-Disassembly of section .text:
-
-0+ <.*>:
- 0: 4c0050a4 jirl \$a0, \$a1, 80
- 0: R_LARCH_B16 .L1
- 4: 50004c00 b 76 # 50 <.L1>
- 4: R_LARCH_B26 .L1
- 8: 14000004 lu12i.w \$a0, 0
- 8: R_LARCH_ABS_HI20 .L1
- c: 038000a4 ori \$a0, \$a1, 0x0
- c: R_LARCH_ABS_LO12 .L1
- 10: 1a000004 pcalau12i \$a0, 0
- 10: R_LARCH_PCALA_HI20 .L1
- 14: 02800085 addi.w \$a1, \$a0, 0
- 14: R_LARCH_PCALA_LO12 .L1
- 18: 1a000004 pcalau12i \$a0, 0
- 18: R_LARCH_GOT_PC_HI20 .L1
- 1c: 28800085 ld.w \$a1, \$a0, 0
- 1c: R_LARCH_GOT_PC_LO12 .L1
- 20: 14000004 lu12i.w \$a0, 0
- 20: R_LARCH_GOT_HI20 .L1
- 24: 03800084 ori \$a0, \$a0, 0x0
- 24: R_LARCH_GOT_LO12 .L1
- 28: 14000004 lu12i.w \$a0, 0
- 28: R_LARCH_TLS_LE_HI20 TLSL1
- 28: R_LARCH_RELAX \*ABS\*
- 2c: 03800085 ori \$a1, \$a0, 0x0
- 2c: R_LARCH_TLS_LE_LO12 TLSL1
- 2c: R_LARCH_RELAX \*ABS\*
- 30: 1a000004 pcalau12i \$a0, 0
- 30: R_LARCH_TLS_IE_PC_HI20 TLSL1
- 34: 02c00005 li.d \$a1, 0
- 34: R_LARCH_TLS_IE_PC_LO12 TLSL1
+#...
+ 0: 1c000001 pcaddu12i \$ra, 0
+ 0: R_LARCH_CALL30 .L1
+ 0: R_LARCH_RELAX \*ABS\*
+ 4: 4c000021 jirl \$ra, \$ra, 0
+ 8: 1c000001 pcaddu12i \$ra, 0
+ 8: R_LARCH_CALL30 .L1
+ 8: R_LARCH_RELAX \*ABS\*
+ c: 4c000020 ret
+ 10: 4ffff0a4 jirl \$a0, \$a1, -16
+ 10: R_LARCH_B16 .L1
+ 14: 53ffefff b -20 # 0 <.L1>
+ 14: R_LARCH_B26 .L1
+ 18: 14000004 lu12i.w \$a0, 0
+ 18: R_LARCH_ABS_HI20 .L1
+ 1c: 038000a4 ori \$a0, \$a1, 0x0
+ 1c: R_LARCH_ABS_LO12 .L1
+ 20: 1a000004 pcalau12i \$a0, 0
+ 20: R_LARCH_PCALA_HI20 .L1
+ 24: 02800085 addi.w \$a1, \$a0, 0
+ 24: R_LARCH_PCALA_LO12 .L1
+ 28: 1a000004 pcalau12i \$a0, 0
+ 28: R_LARCH_GOT_PC_HI20 .L1
+ 2c: 28800085 ld.w \$a1, \$a0, 0
+ 2c: R_LARCH_GOT_PC_LO12 .L1
+ 30: 14000004 lu12i.w \$a0, 0
+ 30: R_LARCH_GOT_HI20 .L1
+ 34: 03800084 ori \$a0, \$a0, 0x0
+ 34: R_LARCH_GOT_LO12 .L1
38: 14000004 lu12i.w \$a0, 0
- 38: R_LARCH_TLS_IE_HI20 TLSL1
- 3c: 03800084 ori \$a0, \$a0, 0x0
- 3c: R_LARCH_TLS_IE_LO12 TLSL1
+ 38: R_LARCH_TLS_LE_HI20 TLSL1
+ 38: R_LARCH_RELAX \*ABS\*
+ 3c: 03800085 ori \$a1, \$a0, 0x0
+ 3c: R_LARCH_TLS_LE_LO12 TLSL1
+ 3c: R_LARCH_RELAX \*ABS\*
40: 1a000004 pcalau12i \$a0, 0
- 40: R_LARCH_TLS_LD_PC_HI20 TLSL1
- 44: 14000004 lu12i.w \$a0, 0
- 44: R_LARCH_TLS_LD_HI20 TLSL1
- 48: 1a000004 pcalau12i \$a0, 0
- 48: R_LARCH_TLS_GD_PC_HI20 TLSL1
- 4c: 14000004 lu12i.w \$a0, 0
- 4c: R_LARCH_TLS_GD_HI20 TLSL1
-
-0+50 <.L1>:
- 50: 00000000 .word 0x00000000
- 50: R_LARCH_32_PCREL .L2
+ 40: R_LARCH_TLS_IE_PC_HI20 TLSL1
+ 44: 02c00005 li.d \$a1, 0
+ 44: R_LARCH_TLS_IE_PC_LO12 TLSL1
+ 48: 14000004 lu12i.w \$a0, 0
+ 48: R_LARCH_TLS_IE_HI20 TLSL1
+ 4c: 03800084 ori \$a0, \$a0, 0x0
+ 4c: R_LARCH_TLS_IE_LO12 TLSL1
+ 50: 1a000004 pcalau12i \$a0, 0
+ 50: R_LARCH_TLS_LD_PC_HI20 TLSL1
+ 54: 14000004 lu12i.w \$a0, 0
+ 54: R_LARCH_TLS_LD_HI20 TLSL1
+ 58: 1a000004 pcalau12i \$a0, 0
+ 58: R_LARCH_TLS_GD_PC_HI20 TLSL1
+ 5c: 14000004 lu12i.w \$a0, 0
+ 5c: R_LARCH_TLS_GD_HI20 TLSL1
+ 60: 00000000 .word 0x00000000
+ 60: R_LARCH_ADD32 .L2
+ 60: R_LARCH_SUB32 .L1
-0+54 <.L2>:
- 54: 03400000 nop
- 58: 03400000 nop
- 58: R_LARCH_ALIGN .*
- 5c: 03400000 nop
- 60: 03400000 nop
- 64: 1800000c pcaddi \$t0, 0
- 64: R_LARCH_PCREL20_S2 .L1
- 68: 1a000004 pcalau12i \$a0, 0
- 68: R_LARCH_TLS_DESC_PC_HI20 TLSL1
- 6c: 028000a5 addi.w \$a1, \$a1, 0
- 6c: R_LARCH_TLS_DESC_PC_LO12 TLSL1
- 70: 14000004 lu12i.w \$a0, 0
- 70: R_LARCH_TLS_DESC_HI20 TLSL1
- 74: 03800084 ori \$a0, \$a0, 0x0
- 74: R_LARCH_TLS_DESC_LO12 TLSL1
- 78: 28800081 ld.w \$ra, \$a0, 0
- 78: R_LARCH_TLS_DESC_LD TLSL1
- 7c: 4c000021 jirl \$ra, \$ra, 0
- 7c: R_LARCH_TLS_DESC_CALL TLSL1
-0+80 <NEW>:
- 80: 1c000001 pcaddu12i \$ra, 0
- 80: R_LARCH_CALL30 \.L1
- 80: R_LARCH_RELAX \*ABS\*
- 84: 4c000021 jirl \$ra, \$ra, 0
- 88: 1c000001 pcaddu12i \$ra, 0
- 88: R_LARCH_CALL30 \.L1
- 88: R_LARCH_RELAX \*ABS\*
- 8c: 4c000020 ret
+00000064 <.L2>:
+ 64: 03400000 nop
+ 68: 03400000 nop
+ 68: R_LARCH_ALIGN \*ABS\*\+0xc
+ 6c: 03400000 nop
+ 70: 03400000 nop
+ 74: 1800000c pcaddi \$t0, 0
+ 74: R_LARCH_PCREL20_S2 .L1
+ 78: 1a000004 pcalau12i \$a0, 0
+ 78: R_LARCH_TLS_DESC_PC_HI20 TLSL1
+ 7c: 028000a5 addi.w \$a1, \$a1, 0
+ 7c: R_LARCH_TLS_DESC_PC_LO12 TLSL1
+ 80: 14000004 lu12i.w \$a0, 0
+ 80: R_LARCH_TLS_DESC_HI20 TLSL1
+ 84: 03800084 ori \$a0, \$a0, 0x0
+ 84: R_LARCH_TLS_DESC_LO12 TLSL1
+ 88: 28800081 ld.w \$ra, \$a0, 0
+ 88: R_LARCH_TLS_DESC_LD TLSL1
+ 8c: 4c000021 jirl \$ra, \$ra, 0
+ 8c: R_LARCH_TLS_DESC_CALL TLSL1
-0+90 <\.Lpcadd_hi0>:
+00000090 <.Lpcadd_hi0>:
90: 1c000004 pcaddu12i \$a0, 0
90: R_LARCH_PCADD_HI20 s
94: 02800084 addi.w \$a0, \$a0, 0
- 94: R_LARCH_PCADD_LO12 \.Lpcadd_hi0
+ 94: R_LARCH_PCADD_LO12 .Lpcadd_hi0
-0+98 <\.Lpcadd_hi1>:
+00000098 <.Lpcadd_hi1>:
98: 1c000004 pcaddu12i \$a0, 0
98: R_LARCH_GOT_PCADD_HI20 s
9c: 28800084 ld.w \$a0, \$a0, 0
- 9c: R_LARCH_GOT_PCADD_LO12 \.Lpcadd_hi1
+ 9c: R_LARCH_GOT_PCADD_LO12 .Lpcadd_hi1
-0+a0 <\.Lpcadd_hi2>:
+000000a0 <.Lpcadd_hi2>:
a0: 1c000004 pcaddu12i \$a0, 0
a0: R_LARCH_TLS_IE_PCADD_HI20 TLSL1
a4: 28800084 ld.w \$a0, \$a0, 0
- a4: R_LARCH_TLS_IE_PCADD_LO12 \.Lpcadd_hi2
+ a4: R_LARCH_TLS_IE_PCADD_LO12 .Lpcadd_hi2
-0+a8 <\.Lpcadd_hi3>:
+000000a8 <.Lpcadd_hi3>:
a8: 1c000004 pcaddu12i \$a0, 0
a8: R_LARCH_TLS_LD_PCADD_HI20 TLSL1
ac: 02800084 addi.w \$a0, \$a0, 0
- ac: R_LARCH_TLS_LD_PCADD_LO12 \.Lpcadd_hi3
+ ac: R_LARCH_TLS_LD_PCADD_LO12 .Lpcadd_hi3
-0+b0 <\.Lpcadd_hi4>:
+000000b0 <.Lpcadd_hi4>:
b0: 1c000004 pcaddu12i \$a0, 0
b0: R_LARCH_TLS_GD_PCADD_HI20 TLSL1
b4: 02800084 addi.w \$a0, \$a0, 0
- b4: R_LARCH_TLS_GD_PCADD_LO12 \.Lpcadd_hi4
+ b4: R_LARCH_TLS_GD_PCADD_LO12 .Lpcadd_hi4
-0+b8 <\.Lpcadd_hi5>:
+000000b8 <.Lpcadd_hi5>:
b8: 1c000004 pcaddu12i \$a0, 0
b8: R_LARCH_TLS_DESC_PCADD_HI20 TLS1
bc: 02800084 addi.w \$a0, \$a0, 0
- bc: R_LARCH_TLS_DESC_PCADD_LO12 \.Lpcadd_hi5
+ bc: R_LARCH_TLS_DESC_PCADD_LO12 .Lpcadd_hi5
c0: 28800081 ld.w \$ra, \$a0, 0
c0: R_LARCH_TLS_DESC_LD TLS1
c4: 4c000021 jirl \$ra, \$ra, 0
diff --git a/gas/testsuite/gas/loongarch/relocs_32.s b/gas/testsuite/gas/loongarch/relocs_32.s
index 8a6074d018a..65675a16e5a 100644
--- a/gas/testsuite/gas/loongarch/relocs_32.s
+++ b/gas/testsuite/gas/loongarch/relocs_32.s
@@ -1,3 +1,8 @@
+.L1:
+/* LA32S/R medium call. */
+call30 .L1
+tail30 $r1, .L1
+
/* b16. */
jirl $r4,$r5,%b16(.L1)
@@ -39,7 +44,6 @@ pcalau12i $r4,%gd_pc_hi20(TLSL1)
lu12i.w $r4,%gd_hi20(TLSL1)
/* Test insn relocs. */
-.L1:
/* 32-bit PC relative. */
.4byte .L2-.L1
.L2:
@@ -60,11 +64,6 @@ ori $r4,$r4,%desc_lo12(TLSL1)
ld.w $r1,$r4,%desc_ld(TLSL1)
jirl $r1,$r1,%desc_call(TLSL1)
-NEW:
-/* LA32S/R medium call. */
-call30 .L1
-tail30 $r1, .L1
-
/* LA32R PCREL. */
.Lpcadd_hi0:
pcaddu12i $r4, %pcadd_hi20(s)
diff --git a/gas/testsuite/gas/loongarch/relocs_64.d b/gas/testsuite/gas/loongarch/relocs_64.d
index ce5216a2b73..a12849126e2 100644
--- a/gas/testsuite/gas/loongarch/relocs_64.d
+++ b/gas/testsuite/gas/loongarch/relocs_64.d
@@ -1,148 +1,153 @@
-#as:
+#as: -mrelax
#objdump: -dr
-#skip: loongarch32-*-*
-.*:[ ]+file format .*
+#...
+[ ]+0:[ ]+4c008ca4[ ]+jirl[ ]+\$a0,[ ]+\$a1,[ ]+140
+[ ]+0:[ ]+R_LARCH_B16[ ]+.L1
+[ ]+4:[ ]+40008880[ ]+beqz[ ]+\$a0,[ ]+136[ ]+#[ ]+8c[ ]+<.L1>
+[ ]+4:[ ]+R_LARCH_B21[ ]+.L1
+[ ]+8:[ ]+50008400[ ]+b[ ]+132[ ]+#[ ]+8c[ ]+<.L1>
+[ ]+8:[ ]+R_LARCH_B26[ ]+.L1
+[ ]+c:[ ]+14000004[ ]+lu12i.w[ ]+\$a0,[ ]+0
+[ ]+c:[ ]+R_LARCH_ABS_HI20[ ]+.L1
+[ ]+10:[ ]+038000a4[ ]+ori[ ]+\$a0,[ ]+\$a1,[ ]+0x0
+[ ]+10:[ ]+R_LARCH_ABS_LO12[ ]+.L1
+[ ]+14:[ ]+16000004[ ]+lu32i.d[ ]+\$a0,[ ]+0
+[ ]+14:[ ]+R_LARCH_ABS64_LO20[ ]+.L1
+[ ]+18:[ ]+03000085[ ]+lu52i.d[ ]+\$a1,[ ]+\$a0,[ ]+0
+[ ]+18:[ ]+R_LARCH_ABS64_HI12[ ]+.L1
+[ ]+1c:[ ]+1a000004[ ]+pcalau12i[ ]+\$a0,[ ]+0
+[ ]+1c:[ ]+R_LARCH_PCALA_HI20[ ]+.L1
+[ ]+20:[ ]+02c00085[ ]+addi.d[ ]+\$a1,[ ]+\$a0,[ ]+0
+[ ]+20:[ ]+R_LARCH_PCALA_LO12[ ]+.L1
+[ ]+24:[ ]+16000004[ ]+lu32i.d[ ]+\$a0,[ ]+0
+[ ]+24:[ ]+R_LARCH_PCALA64_LO20[ ]+.L1
+[ ]+28:[ ]+03000085[ ]+lu52i.d[ ]+\$a1,[ ]+\$a0,[ ]+0
+[ ]+28:[ ]+R_LARCH_PCALA64_HI12[ ]+.L1
+[ ]+2c:[ ]+1a000004[ ]+pcalau12i[ ]+\$a0,[ ]+0
+[ ]+2c:[ ]+R_LARCH_GOT_PC_HI20[ ]+.L1
+[ ]+30:[ ]+28c00085[ ]+ld.d[ ]+\$a1,[ ]+\$a0,[ ]+0
+[ ]+30:[ ]+R_LARCH_GOT_PC_LO12[ ]+.L1
+[ ]+34:[ ]+16000004[ ]+lu32i.d[ ]+\$a0,[ ]+0
+[ ]+34:[ ]+R_LARCH_GOT64_PC_LO20[ ]+.L1
+[ ]+38:[ ]+03000085[ ]+lu52i.d[ ]+\$a1,[ ]+\$a0,[ ]+0
+[ ]+38:[ ]+R_LARCH_GOT64_PC_HI12[ ]+.L1
+[ ]+3c:[ ]+14000004[ ]+lu12i.w[ ]+\$a0,[ ]+0
+[ ]+3c:[ ]+R_LARCH_GOT_HI20[ ]+.L1
+[ ]+40:[ ]+03800084[ ]+ori[ ]+\$a0,[ ]+\$a0,[ ]+0x0
+[ ]+40:[ ]+R_LARCH_GOT_LO12[ ]+.L1
+[ ]+44:[ ]+16000004[ ]+lu32i.d[ ]+\$a0,[ ]+0
+[ ]+44:[ ]+R_LARCH_GOT64_LO20[ ]+.L1
+[ ]+48:[ ]+03000085[ ]+lu52i.d[ ]+\$a1,[ ]+\$a0,[ ]+0
+[ ]+48:[ ]+R_LARCH_GOT64_HI12[ ]+.L1
+[ ]+4c:[ ]+14000004[ ]+lu12i.w[ ]+\$a0,[ ]+0
+[ ]+4c:[ ]+R_LARCH_TLS_LE_HI20[ ]+TLSL1
+[ ]+4c:[ ]+R_LARCH_RELAX[ ]+\*ABS\*
+[ ]+50:[ ]+03800085[ ]+ori[ ]+\$a1,[ ]+\$a0,[ ]+0x0
+[ ]+50:[ ]+R_LARCH_TLS_LE_LO12[ ]+TLSL1
+[ ]+50:[ ]+R_LARCH_RELAX[ ]+\*ABS\*
+[ ]+54:[ ]+16000004[ ]+lu32i.d[ ]+\$a0,[ ]+0
+[ ]+54:[ ]+R_LARCH_TLS_LE64_LO20[ ]+TLSL1
+[ ]+54:[ ]+R_LARCH_RELAX[ ]+\*ABS\*
+[ ]+58:[ ]+03000085[ ]+lu52i.d[ ]+\$a1,[ ]+\$a0,[ ]+0
+[ ]+58:[ ]+R_LARCH_TLS_LE64_HI12[ ]+TLSL1
+[ ]+58:[ ]+R_LARCH_RELAX[ ]+\*ABS\*
+[ ]+5c:[ ]+1a000004[ ]+pcalau12i[ ]+\$a0,[ ]+0
+[ ]+5c:[ ]+R_LARCH_TLS_IE_PC_HI20[ ]+TLSL1
+[ ]+60:[ ]+02c00005[ ]+li.d[ ]+\$a1,[ ]+0
+[ ]+60:[ ]+R_LARCH_TLS_IE_PC_LO12[ ]+TLSL1
+[ ]+64:[ ]+16000005[ ]+lu32i.d[ ]+\$a1,[ ]+0
+[ ]+64:[ ]+R_LARCH_TLS_IE64_PC_LO20[ ]+TLSL1
+[ ]+68:[ ]+030000a5[ ]+lu52i.d[ ]+\$a1,[ ]+\$a1,[ ]+0
+[ ]+68:[ ]+R_LARCH_TLS_IE64_PC_HI12[ ]+TLSL1
+[ ]+6c:[ ]+14000004[ ]+lu12i.w[ ]+\$a0,[ ]+0
+[ ]+6c:[ ]+R_LARCH_TLS_IE_HI20[ ]+TLSL1
+[ ]+70:[ ]+03800084[ ]+ori[ ]+\$a0,[ ]+\$a0,[ ]+0x0
+[ ]+70:[ ]+R_LARCH_TLS_IE_LO12[ ]+TLSL1
+[ ]+74:[ ]+16000004[ ]+lu32i.d[ ]+\$a0,[ ]+0
+[ ]+74:[ ]+R_LARCH_TLS_IE64_LO20[ ]+TLSL1
+[ ]+78:[ ]+03000084[ ]+lu52i.d[ ]+\$a0,[ ]+\$a0,[ ]+0
+[ ]+78:[ ]+R_LARCH_TLS_IE64_HI12[ ]+TLSL1
+[ ]+7c:[ ]+1a000004[ ]+pcalau12i[ ]+\$a0,[ ]+0
+[ ]+7c:[ ]+R_LARCH_TLS_LD_PC_HI20[ ]+TLSL1
+[ ]+80:[ ]+14000004[ ]+lu12i.w[ ]+\$a0,[ ]+0
+[ ]+80:[ ]+R_LARCH_TLS_LD_HI20[ ]+TLSL1
+[ ]+84:[ ]+1a000004[ ]+pcalau12i[ ]+\$a0,[ ]+0
+[ ]+84:[ ]+R_LARCH_TLS_GD_PC_HI20[ ]+TLSL1
+[ ]+88:[ ]+14000004[ ]+lu12i.w[ ]+\$a0,[ ]+0
+[ ]+88:[ ]+R_LARCH_TLS_GD_HI20[ ]+TLSL1
+.*<.L1>:
+[ ]+8c:[ ]+1e000001[ ]+pcaddu18i[ ]+\$ra,[ ]+0
+[ ]+8c:[ ]+R_LARCH_CALL36[ ]+.L1
+[ ]+8c:[ ]+R_LARCH_RELAX[ ]+\*ABS\*
+[ ]+90:[ ]+4c000021[ ]+jirl[ ]+\$ra,[ ]+\$ra,[ ]+0
+[ ]+94:[ ]+00000000[ ]+.word[ ]+0x00000000
+[ ]+94:[ ]+R_LARCH_ADD32[ ]+.L2
+[ ]+94:[ ]+R_LARCH_SUB32[ ]+.L1
-Disassembly of section .text:
-
-[ ]*0000000000000000 <.L1-0x8c>:
-[ ]+0:[ ]+4c008ca4[ ]+jirl[ ]+\$a0, \$a1, 140
-[ ]+0: R_LARCH_B16[ ]+.L1
-[ ]+4:[ ]+40008880[ ]+beqz[ ]+\$a0, 136[ ]+# 8c <.L1>
-[ ]+4: R_LARCH_B21[ ]+.L1
-[ ]+8:[ ]+50008400[ ]+b[ ]+132[ ]+# 8c <.L1>
-[ ]+8: R_LARCH_B26[ ]+.L1
-[ ]+c:[ ]+14000004[ ]+lu12i.w[ ]+\$a0, 0
-[ ]+c: R_LARCH_ABS_HI20[ ]+.L1
-[ ]+10:[ ]+038000a4[ ]+ori[ ]+\$a0, \$a1, 0x0
-[ ]+10: R_LARCH_ABS_LO12[ ]+.L1
-[ ]+14:[ ]+16000004[ ]+lu32i.d[ ]+\$a0, 0
-[ ]+14: R_LARCH_ABS64_LO20[ ]+.L1
-[ ]+18:[ ]+03000085[ ]+lu52i.d[ ]+\$a1, \$a0, 0
-[ ]+18: R_LARCH_ABS64_HI12[ ]+.L1
-[ ]+1c:[ ]+1a000004[ ]+pcalau12i[ ]+\$a0, 0
-[ ]+1c: R_LARCH_PCALA_HI20[ ]+.L1
-[ ]+20:[ ]+02c00085[ ]+addi.d[ ]+\$a1, \$a0, 0
-[ ]+20: R_LARCH_PCALA_LO12[ ]+.L1
-[ ]+24:[ ]+16000004[ ]+lu32i.d[ ]+\$a0, 0
-[ ]+24: R_LARCH_PCALA64_LO20[ ]+.L1
-[ ]+28:[ ]+03000085[ ]+lu52i.d[ ]+\$a1, \$a0, 0
-[ ]+28: R_LARCH_PCALA64_HI12[ ]+.L1
-[ ]+2c:[ ]+1a000004[ ]+pcalau12i[ ]+\$a0, 0
-[ ]+2c: R_LARCH_GOT_PC_HI20[ ]+.L1
-[ ]+30:[ ]+28c00085[ ]+ld.d[ ]+\$a1, \$a0, 0
-[ ]+30: R_LARCH_GOT_PC_LO12[ ]+.L1
-[ ]+34:[ ]+16000004[ ]+lu32i.d[ ]+\$a0, 0
-[ ]+34: R_LARCH_GOT64_PC_LO20[ ]+.L1
-[ ]+38:[ ]+03000085[ ]+lu52i.d[ ]+\$a1, \$a0, 0
-[ ]+38: R_LARCH_GOT64_PC_HI12[ ]+.L1
-[ ]+3c:[ ]+14000004[ ]+lu12i.w[ ]+\$a0, 0
-[ ]+3c: R_LARCH_GOT_HI20[ ]+.L1
-[ ]+40:[ ]+03800084[ ]+ori[ ]+\$a0, \$a0, 0x0
-[ ]+40: R_LARCH_GOT_LO12[ ]+.L1
-[ ]+44:[ ]+16000004[ ]+lu32i.d[ ]+\$a0, 0
-[ ]+44: R_LARCH_GOT64_LO20[ ]+.L1
-[ ]+48:[ ]+03000085[ ]+lu52i.d[ ]+\$a1, \$a0, 0
-[ ]+48: R_LARCH_GOT64_HI12[ ]+.L1
-[ ]+4c:[ ]+14000004[ ]+lu12i.w[ ]+\$a0, 0
-[ ]+4c: R_LARCH_TLS_LE_HI20[ ]+TLSL1
-[ ]+4c: R_LARCH_RELAX[ ]+\*ABS\*
-[ ]+50:[ ]+03800085[ ]+ori[ ]+\$a1, \$a0, 0x0
-[ ]+50: R_LARCH_TLS_LE_LO12[ ]+TLSL1
-[ ]+50: R_LARCH_RELAX[ ]+\*ABS\*
-[ ]+54:[ ]+16000004[ ]+lu32i.d[ ]+\$a0, 0
-[ ]+54: R_LARCH_TLS_LE64_LO20[ ]+TLSL1
-[ ]+54: R_LARCH_RELAX[ ]+\*ABS\*
-[ ]+58:[ ]+03000085[ ]+lu52i.d[ ]+\$a1, \$a0, 0
-[ ]+58: R_LARCH_TLS_LE64_HI12[ ]+TLSL1
-[ ]+58: R_LARCH_RELAX[ ]+\*ABS\*
-[ ]+5c:[ ]+1a000004[ ]+pcalau12i[ ]+\$a0, 0
-[ ]+5c: R_LARCH_TLS_IE_PC_HI20[ ]+TLSL1
-[ ]+60:[ ]+02c00005[ ]+li.d[ ]+\$a1, 0
-[ ]+60: R_LARCH_TLS_IE_PC_LO12[ ]+TLSL1
-[ ]+64:[ ]+16000005[ ]+lu32i.d[ ]+\$a1, 0
-[ ]+64: R_LARCH_TLS_IE64_PC_LO20[ ]+TLSL1
-[ ]+68:[ ]+030000a5[ ]+lu52i.d[ ]+\$a1, \$a1, 0
-[ ]+68: R_LARCH_TLS_IE64_PC_HI12[ ]+TLSL1
-[ ]+6c:[ ]+14000004[ ]+lu12i.w[ ]+\$a0, 0
-[ ]+6c: R_LARCH_TLS_IE_HI20[ ]+TLSL1
-[ ]+70:[ ]+03800084[ ]+ori[ ]+\$a0, \$a0, 0x0
-[ ]+70: R_LARCH_TLS_IE_LO12[ ]+TLSL1
-[ ]+74:[ ]+16000004[ ]+lu32i.d[ ]+\$a0, 0
-[ ]+74: R_LARCH_TLS_IE64_LO20[ ]+TLSL1
-[ ]+78:[ ]+03000084[ ]+lu52i.d[ ]+\$a0, \$a0, 0
-[ ]+78: R_LARCH_TLS_IE64_HI12[ ]+TLSL1
-[ ]+7c:[ ]+1a000004[ ]+pcalau12i[ ]+\$a0, 0
-[ ]+7c: R_LARCH_TLS_LD_PC_HI20[ ]+TLSL1
-[ ]+80:[ ]+14000004[ ]+lu12i.w[ ]+\$a0, 0
-[ ]+80: R_LARCH_TLS_LD_HI20[ ]+TLSL1
-[ ]+84:[ ]+1a000004[ ]+pcalau12i[ ]+\$a0, 0
-[ ]+84: R_LARCH_TLS_GD_PC_HI20[ ]+TLSL1
-[ ]+88:[ ]+14000004[ ]+lu12i.w[ ]+\$a0, 0
-[ ]+88: R_LARCH_TLS_GD_HI20[ ]+TLSL1
-000000000000008c <.L1>:
-[ ]+8c:[ ]+00000000[ ]+.word[ ]+[ ]+0x00000000
-[ ]+8c: R_LARCH_ADD32[ ]+.L2
-[ ]+8c: R_LARCH_SUB32[ ]+.L1
-0000000000000090 <.L2>:
+.*<.L2>:
+[ ]+98:[ ]+1e000001[ ]+pcaddu18i[ ]+\$ra,[ ]+0
+[ ]+98:[ ]+R_LARCH_CALL36[ ]+.L1
+[ ]+98:[ ]+R_LARCH_RELAX[ ]+\*ABS\*
+[ ]+9c:[ ]+4c000021[ ]+jirl[ ]+\$ra,[ ]+\$ra,[ ]+0
[ ]+...
-[ ]+90: R_LARCH_ADD64[ ]+.L3
-[ ]+90: R_LARCH_SUB64[ ]+.L2
-0000000000000098 <.L3>:
-[ ]+98:[ ]+03400000[ ]+nop
-[ ]+9c:[ ]+03400000[ ]+nop
-[ ]+9c: R_LARCH_ALIGN[ ]+\*ABS\*\+0xc
-[ ]+a0:[ ]+03400000[ ]+nop
-[ ]+a4:[ ]+03400000[ ]+nop
-[ ]+a8:[ ]+1800000c[ ]+pcaddi[ ]+\$t0, 0
-[ ]+a8: R_LARCH_PCREL20_S2[ ]+.L1
-[ ]+ac:[ ]+1e000001[ ]+pcaddu18i[ ]+\$ra, 0
-[ ]+ac: R_LARCH_CALL36[ ]+a
-[ ]+ac: R_LARCH_RELAX[ ]+\*ABS\*
-[ ]+b0:[ ]+4c000021[ ]+jirl[ ]+\$ra, \$ra, 0
-[ ]+b4:[ ]+1a000004[ ]+pcalau12i[ ]+\$a0, 0
-[ ]+b4: R_LARCH_TLS_DESC_PC_HI20[ ]+TLSL1
-[ ]+b8:[ ]+02c000a5[ ]+addi.d[ ]+\$a1, \$a1, 0
-[ ]+b8: R_LARCH_TLS_DESC_PC_LO12[ ]+TLSL1
-[ ]+bc:[ ]+16000005[ ]+lu32i.d[ ]+\$a1, 0
-[ ]+bc: R_LARCH_TLS_DESC64_PC_LO20[ ]+TLSL1
-[ ]+c0:[ ]+030000a5[ ]+lu52i.d[ ]+\$a1, \$a1, 0
-[ ]+c0: R_LARCH_TLS_DESC64_PC_HI12[ ]+TLSL1
-[ ]+c4:[ ]+14000004[ ]+lu12i.w[ ]+\$a0, 0
-[ ]+c4: R_LARCH_TLS_DESC_HI20[ ]+TLSL1
-[ ]+c8:[ ]+03800084[ ]+ori[ ]+\$a0, \$a0, 0x0
-[ ]+c8: R_LARCH_TLS_DESC_LO12[ ]+TLSL1
-[ ]+cc:[ ]+16000004[ ]+lu32i.d[ ]+\$a0, 0
-[ ]+cc: R_LARCH_TLS_DESC64_LO20[ ]+TLSL1
-[ ]+d0:[ ]+03000084[ ]+lu52i.d[ ]+\$a0, \$a0, 0
-[ ]+d0: R_LARCH_TLS_DESC64_HI12[ ]+TLSL1
-[ ]+d4:[ ]+28c00081[ ]+ld.d[ ]+\$ra, \$a0, 0
-[ ]+d4: R_LARCH_TLS_DESC_LD[ ]+TLSL1
-[ ]+d8:[ ]+4c000021[ ]+jirl[ ]+\$ra, \$ra, 0
-[ ]+d8: R_LARCH_TLS_DESC_CALL[ ]+TLSL1
-[ ]+dc:[ ]+14000004[ ]+lu12i.w[ ]+\$a0, 0
-[ ]+dc: R_LARCH_TLS_LE_HI20_R[ ]+TLSL1
-[ ]+dc: R_LARCH_RELAX[ ]+\*ABS\*
-[ ]+e0:[ ]+001090a5[ ]+add.d[ ]+\$a1, \$a1, \$a0
-[ ]+e0: R_LARCH_TLS_LE_ADD_R[ ]+TLSL1
-[ ]+e0: R_LARCH_RELAX[ ]+\*ABS\*
-[ ]+e4:[ ]+29800085[ ]+st.w[ ]+\$a1, \$a0, 0
-[ ]+e4: R_LARCH_TLS_LE_LO12_R[ ]+TLSL1
-[ ]+e4: R_LARCH_RELAX[ ]+\*ABS\*
-[ ]+e8:[ ]+14000004[ ]+lu12i.w[ ]+\$a0, 0
-[ ]+e8: R_LARCH_TLS_LE_HI20_R[ ]+TLSL1
-[ ]+e8: R_LARCH_RELAX[ ]+\*ABS\*
-[ ]+ec:[ ]+001090a5[ ]+add.d[ ]+\$a1, \$a1, \$a0
-[ ]+ec: R_LARCH_TLS_LE_ADD_R[ ]+TLSL1
-[ ]+ec: R_LARCH_RELAX[ ]+\*ABS\*
-[ ]+f0:[ ]+29800085[ ]+st.w[ ]+\$a1, \$a0, 0
-[ ]+f0: R_LARCH_TLS_LE_LO12_R[ ]+TLSL1
-[ ]+f0: R_LARCH_RELAX[ ]+\*ABS\*
-[ ]+f4:[ ]+18000004[ ]+pcaddi[ ]+\$a0, 0
-[ ]+f4: R_LARCH_TLS_LD_PCREL20_S2[ ]+TLSL1
-[ ]+f8:[ ]+18000004[ ]+pcaddi[ ]+\$a0, 0
-[ ]+f8: R_LARCH_TLS_GD_PCREL20_S2[ ]+TLSL1
-[ ]+fc:[ ]+18000004[ ]+pcaddi[ ]+\$a0, 0
-[ ]+fc: R_LARCH_TLS_DESC_PCREL20_S2[ ]+TLSL1
+[ ]+a0:[ ]+R_LARCH_ADD64[ ]+.L3
+[ ]+a0:[ ]+R_LARCH_SUB64[ ]+.L2
+
+.*<.L3>:
+[ ]+a8:[ ]+03400000[ ]+nop
+[ ]+ac:[ ]+03400000[ ]+nop
+[ ]+ac:[ ]+R_LARCH_ALIGN[ ]+\*ABS\*\+0xc
+[ ]+b0:[ ]+03400000[ ]+nop
+[ ]+b4:[ ]+03400000[ ]+nop
+[ ]+b8:[ ]+1800000c[ ]+pcaddi[ ]+\$t0,[ ]+0
+[ ]+b8:[ ]+R_LARCH_PCREL20_S2[ ]+.L1
+[ ]+bc:[ ]+1e000001[ ]+pcaddu18i[ ]+\$ra,[ ]+0
+[ ]+bc:[ ]+R_LARCH_CALL36[ ]+a
+[ ]+bc:[ ]+R_LARCH_RELAX[ ]+\*ABS\*
+[ ]+c0:[ ]+4c000021[ ]+jirl[ ]+\$ra,[ ]+\$ra,[ ]+0
+[ ]+c4:[ ]+1a000004[ ]+pcalau12i[ ]+\$a0,[ ]+0
+[ ]+c4:[ ]+R_LARCH_TLS_DESC_PC_HI20[ ]+TLSL1
+[ ]+c8:[ ]+02c000a5[ ]+addi.d[ ]+\$a1,[ ]+\$a1,[ ]+0
+[ ]+c8:[ ]+R_LARCH_TLS_DESC_PC_LO12[ ]+TLSL1
+[ ]+cc:[ ]+16000005[ ]+lu32i.d[ ]+\$a1,[ ]+0
+[ ]+cc:[ ]+R_LARCH_TLS_DESC64_PC_LO20[ ]+TLSL1
+[ ]+d0:[ ]+030000a5[ ]+lu52i.d[ ]+\$a1,[ ]+\$a1,[ ]+0
+[ ]+d0:[ ]+R_LARCH_TLS_DESC64_PC_HI12[ ]+TLSL1
+[ ]+d4:[ ]+14000004[ ]+lu12i.w[ ]+\$a0,[ ]+0
+[ ]+d4:[ ]+R_LARCH_TLS_DESC_HI20[ ]+TLSL1
+[ ]+d8:[ ]+03800084[ ]+ori[ ]+\$a0,[ ]+\$a0,[ ]+0x0
+[ ]+d8:[ ]+R_LARCH_TLS_DESC_LO12[ ]+TLSL1
+[ ]+dc:[ ]+16000004[ ]+lu32i.d[ ]+\$a0,[ ]+0
+[ ]+dc:[ ]+R_LARCH_TLS_DESC64_LO20[ ]+TLSL1
+[ ]+e0:[ ]+03000084[ ]+lu52i.d[ ]+\$a0,[ ]+\$a0,[ ]+0
+[ ]+e0:[ ]+R_LARCH_TLS_DESC64_HI12[ ]+TLSL1
+[ ]+e4:[ ]+28c00081[ ]+ld.d[ ]+\$ra,[ ]+\$a0,[ ]+0
+[ ]+e4:[ ]+R_LARCH_TLS_DESC_LD[ ]+TLSL1
+[ ]+e8:[ ]+4c000021[ ]+jirl[ ]+\$ra,[ ]+\$ra,[ ]+0
+[ ]+e8:[ ]+R_LARCH_TLS_DESC_CALL[ ]+TLSL1
+[ ]+ec:[ ]+14000004[ ]+lu12i.w[ ]+\$a0,[ ]+0
+[ ]+ec:[ ]+R_LARCH_TLS_LE_HI20_R[ ]+TLSL1
+[ ]+ec:[ ]+R_LARCH_RELAX[ ]+\*ABS\*
+[ ]+f0:[ ]+001090a5[ ]+add.d[ ]+\$a1,[ ]+\$a1,[ ]+\$a0
+[ ]+f0:[ ]+R_LARCH_TLS_LE_ADD_R[ ]+TLSL1
+[ ]+f0:[ ]+R_LARCH_RELAX[ ]+\*ABS\*
+[ ]+f4:[ ]+29800085[ ]+st.w[ ]+\$a1,[ ]+\$a0,[ ]+0
+[ ]+f4:[ ]+R_LARCH_TLS_LE_LO12_R[ ]+TLSL1
+[ ]+f4:[ ]+R_LARCH_RELAX[ ]+\*ABS\*
+[ ]+f8:[ ]+14000004[ ]+lu12i.w[ ]+\$a0,[ ]+0
+[ ]+f8:[ ]+R_LARCH_TLS_LE_HI20_R[ ]+TLSL1
+[ ]+f8:[ ]+R_LARCH_RELAX[ ]+\*ABS\*
+[ ]+fc:[ ]+001090a5[ ]+add.d[ ]+\$a1,[ ]+\$a1,[ ]+\$a0
+[ ]+fc:[ ]+R_LARCH_TLS_LE_ADD_R[ ]+TLSL1
+[ ]+fc:[ ]+R_LARCH_RELAX[ ]+\*ABS\*
+[ ]+100:[ ]+29800085[ ]+st.w[ ]+\$a1,[ ]+\$a0,[ ]+0
+[ ]+100:[ ]+R_LARCH_TLS_LE_LO12_R[ ]+TLSL1
+[ ]+100:[ ]+R_LARCH_RELAX[ ]+\*ABS\*
+[ ]+104:[ ]+18000004[ ]+pcaddi[ ]+\$a0,[ ]+0
+[ ]+104:[ ]+R_LARCH_TLS_LD_PCREL20_S2[ ]+TLSL1
+[ ]+108:[ ]+18000004[ ]+pcaddi[ ]+\$a0,[ ]+0
+[ ]+108:[ ]+R_LARCH_TLS_GD_PCREL20_S2[ ]+TLSL1
+[ ]+10c:[ ]+18000004[ ]+pcaddi[ ]+\$a0,[ ]+0
+[ ]+10c:[ ]+R_LARCH_TLS_DESC_PCREL20_S2[ ]+TLSL1
diff --git a/gas/testsuite/gas/loongarch/relocs_64.s b/gas/testsuite/gas/loongarch/relocs_64.s
index 1d1548f5b68..d22c03ec4f9 100644
--- a/gas/testsuite/gas/loongarch/relocs_64.s
+++ b/gas/testsuite/gas/loongarch/relocs_64.s
@@ -1,3 +1,4 @@
+.text
/* b16. */
jirl $r4,$r5,%b16(.L1)
@@ -61,9 +62,11 @@ lu12i.w $r4,%gd_hi20(TLSL1)
/* Test insn relocs. */
.L1:
+call36 .L1
/* 32-bit PC relative. */
.4byte .L2-.L1
.L2:
+call36 .L1
/* 64-bit PC relative. */
.8byte .L3-.L2
diff --git a/gas/testsuite/gas/loongarch/thin_add_sub_relax.d b/gas/testsuite/gas/loongarch/thin_add_sub_relax.d
index 9455c3e66bf..92d9157b0d7 100644
--- a/gas/testsuite/gas/loongarch/thin_add_sub_relax.d
+++ b/gas/testsuite/gas/loongarch/thin_add_sub_relax.d
@@ -1,4 +1,4 @@
-#as: -mthin-add-sub
+#as: -mthin-add-sub -mrelax
#objdump: -Dr
.*:[ ]+file format .*
@@ -8,16 +8,16 @@ Disassembly of section .text:
00000000.* <.L1>:
[ ]+...
-[ ]+0:[ ]+R_LARCH_32_PCREL[ ]+.L3
-[ ]+4:[ ]+R_LARCH_ADD32[ ]+.L3
-[ ]+4:[ ]+R_LARCH_SUB32[ ]+.L1
-
-0*00000008[ ]+<.L2>:
+.*R_LARCH_32_PCREL[ ]+.L3
+.*R_LARCH_ADD32[ ]+.L3
+.*R_LARCH_SUB32[ ]+.L1
+#...
+.*<.L2>:
[ ]+...
-[ ]+8:[ ]+R_LARCH_64_PCREL[ ]+.L3
-[ ]+10:[ ]+R_LARCH_ADD64[ ]+.L3
-[ ]+10:[ ]+R_LARCH_SUB64[ ]+.L2
-
+.*R_LARCH_64_PCREL[ ]+.L3
+.*R_LARCH_ADD64[ ]+.L3
+.*R_LARCH_SUB64[ ]+.L2
+#...
Disassembly[ ]+of[ ]+section[ ]+sx:
0*00000000[ ]+<.L3>:
diff --git a/gas/testsuite/gas/loongarch/thin_add_sub_relax.s b/gas/testsuite/gas/loongarch/thin_add_sub_relax.s
index ded275fa72c..2cfd739ff62 100644
--- a/gas/testsuite/gas/loongarch/thin_add_sub_relax.s
+++ b/gas/testsuite/gas/loongarch/thin_add_sub_relax.s
@@ -4,11 +4,13 @@
.4byte .L3-.L1
# add32+sub32
.4byte .L3-.L1
+ call36 .L1
.L2:
# 64_pcrel
.8byte .L3-.L2
# add64+sub64
.8byte .L3-.L2
+ call36 .L1
.section sx
.L3:
diff --git a/ld/testsuite/ld-elf/compressed1d.d b/ld/testsuite/ld-elf/compressed1d.d
index b178695e23f..9d891c1933f 100644
--- a/ld/testsuite/ld-elf/compressed1d.d
+++ b/ld/testsuite/ld-elf/compressed1d.d
@@ -4,13 +4,10 @@
#readelf: -SW
#xfail: [uses_genelf]
#xfail: [riscv_little_endian]
-#xfail: loongarch*-*-*
# Not all ELF targets use the elf.em emulation...
# RISC-V has linker relaxations that delete code, so text label subtractions
# do not get resolved at assembly time, which results in a compressed section
# for little endian targets; but it is uncompressed for big endian targets.
-# LoongArch has linker relaxations that delete code, so text label subtractions
-# do not get resolved at assembly time, which results in a compressed section.
#failif
#...
--
2.34.1