[PATCH] RISC-V: Add support for XXTVarith and XXTVcoder extensions
Bohan Lei <[email protected]>
| Newsgroups | gmane.comp.gnu.binutils |
|---|---|
| Message-ID | <[email protected]> |
This patch adds support for XuanTie vendor-specific XXTVarith [1] and XXTVcoder [2] extensions. XXTVarith contains arithmetic instructions like vector interleave, Galois-field multiply-xor, and fast CRC folding operations. XXTVcoder contains similar instructions to those in Zvabd. The vendor prefix used in XXTVarith and XXTVcoder is "xt." [3]. [1] https://github.com/XUANTIE-RV/thead-extension-spec/blob/master/xxtvarith.adoc [2] https://github.com/XUANTIE-RV/thead-extension-spec/blob/master/xxtvcoder.adoc [3] https://github.com/riscv-non-isa/riscv-toolchain-conventions/blob/main/src/toolchain-conventions.adoc Co-Authored-By: Lifang Xia <[email protected]> bfd/ChangeLog: * elfxx-riscv.c (riscv_multi_subset_supports): Add implication info of XXTVarith and XXTVcoder. (riscv_multi_subset_supports_ext): Add XXTVarith and XXTVcoder. gas/ChangeLog: * testsuite/gas/riscv/x-xt-varith.d: New test. * testsuite/gas/riscv/x-xt-varith.s: New test. * testsuite/gas/riscv/x-xt-vcoder.d: New test. * testsuite/gas/riscv/x-xt-vcoder.s: New test. include/ChangeLog: * opcode/riscv-opc.h (MATCH_XT_VILE_VV): New macro. (MASK_XT_VILE_VV): Ditto. (MATCH_XT_VILO_VV): Ditto. (MASK_XT_VILO_VV): Ditto. (MATCH_XT_VGMULXOR_VV): Ditto. (MASK_XT_VGMULXOR_VV): Ditto. (MATCH_XT_VCRCFOLDR_VV): Ditto. (MASK_XT_VCRCFOLDR_VV): Ditto. (MATCH_XT_VCRCFOLDN_VV): Ditto. (MASK_XT_VCRCFOLDN_VV): Ditto. (MATCH_XT_VABD_VV): Ditto. (MASK_XT_VABD_VV): Ditto. (MATCH_XT_VABD_VX): Ditto. (MASK_XT_VABD_VX): Ditto. (MATCH_XT_VABD_VI): Ditto. (MASK_XT_VABD_VI): Ditto. (MATCH_XT_VABA_VV): Ditto. (MASK_XT_VABA_VV): Ditto. (MATCH_XT_VABA_VX): Ditto. (MASK_XT_VABA_VX): Ditto. (MATCH_XT_VABA_VI): Ditto. (MASK_XT_VABA_VI): Ditto. (MATCH_XT_VABDU_VV): Ditto. (MASK_XT_VABDU_VV): Ditto. (MATCH_XT_VABDU_VX): Ditto. (MASK_XT_VABDU_VX): Ditto. (MATCH_XT_VABDU_VI): Ditto. (MASK_XT_VABDU_VI): Ditto. (MATCH_XT_VABAU_VV): Ditto. (MASK_XT_VABAU_VV): Ditto. (MATCH_XT_VABAU_VX): Ditto. (MASK_XT_VABAU_VX): Ditto. (MATCH_XT_VABAU_VI): Ditto. (MASK_XT_VABAU_VI): Ditto. (MATCH_XT_VWABD_VV): Ditto. (MASK_XT_VWABD_VV): Ditto. (MATCH_XT_VWABD_VX): Ditto. (MASK_XT_VWABD_VX): Ditto. (MATCH_XT_VWABA_VV): Ditto. (MASK_XT_VWABA_VV): Ditto. (MATCH_XT_VWABA_VX): Ditto. (MASK_XT_VWABA_VX): Ditto. (MATCH_XT_VWABAU_VV): Ditto. (MASK_XT_VWABAU_VV): Ditto. (MATCH_XT_VWABAU_VX): Ditto. (MASK_XT_VWABAU_VX): Ditto. (MATCH_XT_VWABDU_VV): Ditto. (MASK_XT_VWABDU_VV): Ditto. (MATCH_XT_VWABDU_VX): Ditto. (MASK_XT_VWABDU_VX): Ditto. (MATCH_XT_VFABD_VV): Ditto. (MASK_XT_VFABD_VV): Ditto. (MATCH_XT_VFABD_VF): Ditto. (MASK_XT_VFABD_VF): Ditto. (MATCH_XT_VABSMAX_VV): Ditto. (MASK_XT_VABSMAX_VV): Ditto. * opcode/riscv.h (enum riscv_insn_class): Add classes for XXTVarith and XXTVcoder. opcodes/ChangeLog: * riscv-opc.c: Add XXTVarith and XXTVcoder instructions. Signed-off-by: Bohan Lei <[email protected]> --- bfd/elfxx-riscv.c | 13 ++++++ gas/testsuite/gas/riscv/march-help.l | 2 + gas/testsuite/gas/riscv/x-xt-varith.d | 13 ++++++ gas/testsuite/gas/riscv/x-xt-varith.s | 5 +++ gas/testsuite/gas/riscv/x-xt-vcoder.d | 32 +++++++++++++++ gas/testsuite/gas/riscv/x-xt-vcoder.s | 24 +++++++++++ include/opcode/riscv-opc.h | 58 +++++++++++++++++++++++++++ include/opcode/riscv.h | 2 + opcodes/riscv-opc.c | 32 +++++++++++++++ 9 files changed, 181 insertions(+) create mode 100644 gas/testsuite/gas/riscv/x-xt-varith.d create mode 100644 gas/testsuite/gas/riscv/x-xt-varith.s create mode 100644 gas/testsuite/gas/riscv/x-xt-vcoder.d create mode 100644 gas/testsuite/gas/riscv/x-xt-vcoder.s diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c index e1639cbc2cb..c05ac4629c7 100644 --- a/bfd/elfxx-riscv.c +++ b/bfd/elfxx-riscv.c @@ -1230,6 +1230,9 @@ static const struct riscv_implicit_subset riscv_implicit_subsets[] = {"xtheadvector", "+zicsr", check_implicit_always}, {"xtheadzvamo", "+zaamo", check_implicit_always}, + {"xxtvarith", "+v", check_implicit_always}, + {"xxtvcoder", "+v", check_implicit_always}, + {"xsmtvdot", "+zve32x", check_implicit_always}, {"xsmtvdotii", "+xsmtvdot", check_implicit_always}, @@ -1661,6 +1664,8 @@ static const struct riscv_supported_ext riscv_supported_vendor_x_ext[] = {"xtheadvector", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"xtheadvdot", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"xtheadzvamo", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, + {"xxtvarith", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, + {"xxtvcoder", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"xventanacondops", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"xsfvcp", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"xsfcease", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, @@ -3112,6 +3117,10 @@ riscv_multi_subset_supports (riscv_parse_subset_t *rps, return riscv_subset_supports (rps, "xtheadvector"); case INSN_CLASS_XTHEADVDOT: return riscv_subset_supports (rps, "xtheadvdot"); + case INSN_CLASS_XXTVARITH: + return riscv_subset_supports (rps, "xxtvarith"); + case INSN_CLASS_XXTVCODER: + return riscv_subset_supports (rps, "xxtvcoder"); case INSN_CLASS_XTHEADZVAMO: return riscv_subset_supports (rps, "xtheadzvamo"); case INSN_CLASS_XVENTANACONDOPS: @@ -3456,6 +3465,10 @@ riscv_multi_subset_supports_ext (riscv_parse_subset_t *rps, return "xtheadvector"; case INSN_CLASS_XTHEADVDOT: return "xtheadvdot"; + case INSN_CLASS_XXTVARITH: + return "xxtvarith"; + case INSN_CLASS_XXTVCODER: + return "xxtvcoder"; case INSN_CLASS_XTHEADZVAMO: return "xtheadzvamo"; case INSN_CLASS_XVENTANACONDOPS: diff --git a/gas/testsuite/gas/riscv/march-help.l b/gas/testsuite/gas/riscv/march-help.l index 142369b6b1d..5d5b361b237 100644 --- a/gas/testsuite/gas/riscv/march-help.l +++ b/gas/testsuite/gas/riscv/march-help.l @@ -189,6 +189,8 @@ All available -march extensions for RISC-V: xtheadvector 1.0 xtheadvdot 1.0 xtheadzvamo 1.0 + xxtvarith 1.0 + xxtvcoder 1.0 xventanacondops 1.0 xsfvcp 1.0 xsfcease 1.0 diff --git a/gas/testsuite/gas/riscv/x-xt-varith.d b/gas/testsuite/gas/riscv/x-xt-varith.d new file mode 100644 index 00000000000..3512d050f80 --- /dev/null +++ b/gas/testsuite/gas/riscv/x-xt-varith.d @@ -0,0 +1,13 @@ +#as: -march=rv64i_xxtvarith +#objdump: -dr + +.*:[ ]+file format .* + +Disassembly of section .text: + +0+000 <.text>: +[ ]+[0-9a-f]+:[ ]+da11600b[ ]+xt.vile.vv[ ]+v0,v1,v2 +[ ]+[0-9a-f]+:[ ]+f211600b[ ]+xt.vilo.vv[ ]+v0,v1,v2 +[ ]+[0-9a-f]+:[ ]+fa11600b[ ]+xt.vcrcfoldr.vv[ ]+v0,v1,v2 +[ ]+[0-9a-f]+:[ ]+fe11600b[ ]+xt.vcrcfoldn.vv[ ]+v0,v1,v2 +[ ]+[0-9a-f]+:[ ]+7a11600b[ ]+xt.vgmulxor.vv[ ]+v0,v1,v2 diff --git a/gas/testsuite/gas/riscv/x-xt-varith.s b/gas/testsuite/gas/riscv/x-xt-varith.s new file mode 100644 index 00000000000..33be84ea501 --- /dev/null +++ b/gas/testsuite/gas/riscv/x-xt-varith.s @@ -0,0 +1,5 @@ + xt.vile.vv v0, v1, v2 + xt.vilo.vv v0, v1, v2 + xt.vcrcfoldr.vv v0, v1, v2 + xt.vcrcfoldn.vv v0, v1, v2 + xt.vgmulxor.vv v0, v1, v2 diff --git a/gas/testsuite/gas/riscv/x-xt-vcoder.d b/gas/testsuite/gas/riscv/x-xt-vcoder.d new file mode 100644 index 00000000000..bfbee008b2d --- /dev/null +++ b/gas/testsuite/gas/riscv/x-xt-vcoder.d @@ -0,0 +1,32 @@ +#as: -march=rv64i_xxtvcoder +#objdump: -dr + +.*:[ ]+file format .* + +Disassembly of section .text: + +0+000 <.text>: +[ ]+[0-9a-f]+:[ ]+c211700b[ ]+xt.vabd.vv[ ]+v0,v1,v2 +[ ]+[0-9a-f]+:[ ]+c615700b[ ]+xt.vabd.vx[ ]+v0,v1,a0 +[ ]+[0-9a-f]+:[ ]+ca12f00b[ ]+xt.vabd.vi[ ]+v0,v1,5 +[ ]+[0-9a-f]+:[ ]+da11700b[ ]+xt.vaba.vv[ ]+v0,v1,v2 +[ ]+[0-9a-f]+:[ ]+de15700b[ ]+xt.vaba.vx[ ]+v0,v1,a0 +[ ]+[0-9a-f]+:[ ]+ce12700b[ ]+xt.vaba.vi[ ]+v0,v1,4 +[ ]+[0-9a-f]+:[ ]+a211600b[ ]+xt.vabdu.vv[ ]+v0,v1,v2 +[ ]+[0-9a-f]+:[ ]+a615600b[ ]+xt.vabdu.vx[ ]+v0,v1,a0 +[ ]+[0-9a-f]+:[ ]+aa12600b[ ]+xt.vabdu.vi[ ]+v0,v1,4 +[ ]+[0-9a-f]+:[ ]+b211600b[ ]+xt.vabau.vv[ ]+v0,v1,v2 +[ ]+[0-9a-f]+:[ ]+b615600b[ ]+xt.vabau.vx[ ]+v0,v1,a0 +[ ]+[0-9a-f]+:[ ]+ae12600b[ ]+xt.vabau.vi[ ]+v0,v1,4 +[ ]+[0-9a-f]+:[ ]+e211700b[ ]+xt.vwabd.vv[ ]+v0,v1,v2 +[ ]+[0-9a-f]+:[ ]+e616700b[ ]+xt.vwabd.vx[ ]+v0,v1,a2 +[ ]+[0-9a-f]+:[ ]+f211700b[ ]+xt.vwaba.vv[ ]+v0,v1,v2 +[ ]+[0-9a-f]+:[ ]+f616700b[ ]+xt.vwaba.vx[ ]+v0,v1,a2 +[ ]+[0-9a-f]+:[ ]+fa11700b[ ]+xt.vwabau.vv[ ]+v0,v1,v2 +[ ]+[0-9a-f]+:[ ]+fe16700b[ ]+xt.vwabau.vx[ ]+v0,v1,a2 +[ ]+[0-9a-f]+:[ ]+ea11700b[ ]+xt.vwabdu.vv[ ]+v0,v1,v2 +[ ]+[0-9a-f]+:[ ]+ee16700b[ ]+xt.vwabdu.vx[ ]+v0,v1,a2 +[ ]+[0-9a-f]+:[ ]+d211700b[ ]+xt.vfabd.vv[ ]+v0,v1,v2 +[ ]+[0-9a-f]+:[ ]+d616700b[ ]+xt.vfabd.vf[ ]+v0,v1,fa2 +[ ]+[0-9a-f]+:[ ]+6a21f08b[ ]+xt.vabsmax.vv[ ]+v1,v2,v3 +[ ]+[0-9a-f]+:[ ]+6821f08b[ ]+xt.vabsmax.vv[ ]+v1,v2,v3,v0.t diff --git a/gas/testsuite/gas/riscv/x-xt-vcoder.s b/gas/testsuite/gas/riscv/x-xt-vcoder.s new file mode 100644 index 00000000000..4f11a0ac8ec --- /dev/null +++ b/gas/testsuite/gas/riscv/x-xt-vcoder.s @@ -0,0 +1,24 @@ + xt.vabd.vv v0, v1, v2 + xt.vabd.vx v0, v1, a0 + xt.vabd.vi v0, v1, 5 + xt.vaba.vv v0, v1, v2 + xt.vaba.vx v0, v1, a0 + xt.vaba.vi v0, v1, 4 + xt.vabdu.vv v0, v1, v2 + xt.vabdu.vx v0, v1, a0 + xt.vabdu.vi v0, v1, 4 + xt.vabau.vv v0, v1, v2 + xt.vabau.vx v0, v1, a0 + xt.vabau.vi v0, v1, 4 + xt.vwabd.vv v0, v1, v2 + xt.vwabd.vx v0, v1, a2 + xt.vwaba.vv v0, v1, v2 + xt.vwaba.vx v0, v1, a2 + xt.vwabau.vv v0, v1, v2 + xt.vwabau.vx v0, v1, a2 + xt.vwabdu.vv v0, v1, v2 + xt.vwabdu.vx v0, v1, a2 + xt.vfabd.vv v0, v1, v2 + xt.vfabd.vf v0, v1, fa2 + xt.vabsmax.vv v1,v2,v3 + xt.vabsmax.vv v1,v2,v3,v0.t diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h index 6846655aeed..463ddabee4b 100644 --- a/include/opcode/riscv-opc.h +++ b/include/opcode/riscv-opc.h @@ -3798,6 +3798,64 @@ #define MASK_TH_VMAQASU_VX 0xfc00707f #define MATCH_TH_VMAQAUS_VX 0x9c00600b #define MASK_TH_VMAQAUS_VX 0xfc00707f +/* Vendor-specific (XuanTie) XXTVarith instructions. */ +#define MATCH_XT_VILE_VV 0xda00600b +#define MASK_XT_VILE_VV 0xfe00707f +#define MATCH_XT_VILO_VV 0xf200600b +#define MASK_XT_VILO_VV 0xfe00707f +#define MATCH_XT_VGMULXOR_VV 0x7a00600b +#define MASK_XT_VGMULXOR_VV 0xfe00707f +#define MATCH_XT_VCRCFOLDR_VV 0xfa00600b +#define MASK_XT_VCRCFOLDR_VV 0xfe00707f +#define MATCH_XT_VCRCFOLDN_VV 0xfe00600b +#define MASK_XT_VCRCFOLDN_VV 0xfe00707f +/* Vendor-specific (XuanTie) XXTVcoder instructions. */ +#define MATCH_XT_VABD_VV 0xc000700b +#define MASK_XT_VABD_VV 0xfc00707f +#define MATCH_XT_VABD_VX 0xc400700b +#define MASK_XT_VABD_VX 0xfc00707f +#define MATCH_XT_VABD_VI 0xc800700b +#define MASK_XT_VABD_VI 0xfc00707f +#define MATCH_XT_VABA_VV 0xd800700b +#define MASK_XT_VABA_VV 0xfc00707f +#define MATCH_XT_VABA_VX 0xdc00700b +#define MASK_XT_VABA_VX 0xfc00707f +#define MATCH_XT_VABA_VI 0xcc00700b +#define MASK_XT_VABA_VI 0xfc00707f +#define MATCH_XT_VABDU_VV 0xa000600b +#define MASK_XT_VABDU_VV 0xfc00707f +#define MATCH_XT_VABDU_VX 0xa400600b +#define MASK_XT_VABDU_VX 0xfc00707f +#define MATCH_XT_VABDU_VI 0xa800600b +#define MASK_XT_VABDU_VI 0xfc00707f +#define MATCH_XT_VABAU_VV 0xb000600b +#define MASK_XT_VABAU_VV 0xfc00707f +#define MATCH_XT_VABAU_VX 0xb400600b +#define MASK_XT_VABAU_VX 0xfc00707f +#define MATCH_XT_VABAU_VI 0xac00600b +#define MASK_XT_VABAU_VI 0xfc00707f +#define MATCH_XT_VWABD_VV 0xe000700b +#define MASK_XT_VWABD_VV 0xfc00707f +#define MATCH_XT_VWABD_VX 0xe400700b +#define MASK_XT_VWABD_VX 0xfc00707f +#define MATCH_XT_VWABA_VV 0xf000700b +#define MASK_XT_VWABA_VV 0xfc00707f +#define MATCH_XT_VWABA_VX 0xf400700b +#define MASK_XT_VWABA_VX 0xfc00707f +#define MATCH_XT_VWABAU_VV 0xf800700b +#define MASK_XT_VWABAU_VV 0xfc00707f +#define MATCH_XT_VWABAU_VX 0xfc00700b +#define MASK_XT_VWABAU_VX 0xfc00707f +#define MATCH_XT_VWABDU_VV 0xe800700b +#define MASK_XT_VWABDU_VV 0xfc00707f +#define MATCH_XT_VWABDU_VX 0xec00700b +#define MASK_XT_VWABDU_VX 0xfc00707f +#define MATCH_XT_VFABD_VV 0xd000700b +#define MASK_XT_VFABD_VV 0xfc00707f +#define MATCH_XT_VFABD_VF 0xd400700b +#define MASK_XT_VFABD_VF 0xfc00707f +#define MATCH_XT_VABSMAX_VV 0x6800700b +#define MASK_XT_VABSMAX_VV 0xfc00707f /* Vendor-specific (Ventana Microsystems) XVentanaCondOps instructions */ #define MATCH_VT_MASKC 0x607b #define MASK_VT_MASKC 0xfe00707f diff --git a/include/opcode/riscv.h b/include/opcode/riscv.h index f500b877ca6..18757a946e2 100644 --- a/include/opcode/riscv.h +++ b/include/opcode/riscv.h @@ -624,6 +624,8 @@ enum riscv_insn_class INSN_CLASS_XTHEADVECTOR, INSN_CLASS_XTHEADVDOT, INSN_CLASS_XTHEADZVAMO, + INSN_CLASS_XXTVARITH, + INSN_CLASS_XXTVCODER, INSN_CLASS_XVENTANACONDOPS, INSN_CLASS_XSFVCP, INSN_CLASS_XSFCEASE, diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c index cd1e2910307..60ac0def100 100644 --- a/opcodes/riscv-opc.c +++ b/opcodes/riscv-opc.c @@ -3570,6 +3570,38 @@ const struct riscv_opcode riscv_opcodes[] = {"th.vmaqasu.vx", 0, INSN_CLASS_XTHEADVDOT, "Vd,s,VtVm", MATCH_TH_VMAQASU_VX, MASK_TH_VMAQASU_VX, match_opcode, 0}, {"th.vmaqaus.vx", 0, INSN_CLASS_XTHEADVDOT, "Vd,s,VtVm", MATCH_TH_VMAQAUS_VX, MASK_TH_VMAQAUS_VX, match_opcode, 0}, +/* Vendor-specific (XuanTie) XXTVarith instructions. */ +{"xt.vile.vv", 0, INSN_CLASS_XXTVARITH, "Vd,Vt,Vs", MATCH_XT_VILE_VV, MASK_XT_VILE_VV, match_opcode, 0 }, +{"xt.vilo.vv", 0, INSN_CLASS_XXTVARITH, "Vd,Vt,Vs", MATCH_XT_VILO_VV, MASK_XT_VILO_VV, match_opcode, 0 }, +{"xt.vcrcfoldr.vv", 0, INSN_CLASS_XXTVARITH, "Vd,Vt,Vs", MATCH_XT_VCRCFOLDR_VV, MASK_XT_VCRCFOLDR_VV, match_opcode, 0 }, +{"xt.vcrcfoldn.vv", 0, INSN_CLASS_XXTVARITH, "Vd,Vt,Vs", MATCH_XT_VCRCFOLDN_VV, MASK_XT_VCRCFOLDN_VV, match_opcode, 0 }, +{"xt.vgmulxor.vv", 0, INSN_CLASS_XXTVARITH, "Vd,Vt,Vs", MATCH_XT_VGMULXOR_VV, MASK_XT_VGMULXOR_VV, match_opcode, 0 }, + +/* Vendor-specific (XuanTie) XXTVcoder instructions. */ +{"xt.vabd.vv", 0, INSN_CLASS_XXTVCODER, "Vd,Vt,VsVm", MATCH_XT_VABD_VV, MASK_XT_VABD_VV, match_opcode, 0 }, +{"xt.vabd.vx", 0, INSN_CLASS_XXTVCODER, "Vd,Vt,sVm", MATCH_XT_VABD_VX, MASK_XT_VABD_VX, match_opcode, 0 }, +{"xt.vabd.vi", 0, INSN_CLASS_XXTVCODER, "Vd,Vt,ViVm", MATCH_XT_VABD_VI, MASK_XT_VABD_VI, match_opcode, 0 }, +{"xt.vabdu.vv", 0, INSN_CLASS_XXTVCODER, "Vd,Vt,VsVm", MATCH_XT_VABDU_VV, MASK_XT_VABDU_VV, match_opcode, 0 }, +{"xt.vabdu.vx", 0, INSN_CLASS_XXTVCODER, "Vd,Vt,sVm", MATCH_XT_VABDU_VX, MASK_XT_VABDU_VX, match_opcode, 0 }, +{"xt.vabdu.vi", 0, INSN_CLASS_XXTVCODER, "Vd,Vt,VjVm", MATCH_XT_VABDU_VI, MASK_XT_VABDU_VI, match_opcode, 0 }, +{"xt.vaba.vv", 0, INSN_CLASS_XXTVCODER, "Vd,Vt,VsVm", MATCH_XT_VABA_VV, MASK_XT_VABA_VV, match_opcode, 0 }, +{"xt.vaba.vx", 0, INSN_CLASS_XXTVCODER, "Vd,Vt,sVm", MATCH_XT_VABA_VX, MASK_XT_VABA_VX, match_opcode, 0 }, +{"xt.vaba.vi", 0, INSN_CLASS_XXTVCODER, "Vd,Vt,ViVm", MATCH_XT_VABA_VI, MASK_XT_VABA_VI, match_opcode, 0 }, +{"xt.vabau.vv", 0, INSN_CLASS_XXTVCODER, "Vd,Vt,VsVm", MATCH_XT_VABAU_VV, MASK_XT_VABAU_VV, match_opcode, 0 }, +{"xt.vabau.vx", 0, INSN_CLASS_XXTVCODER, "Vd,Vt,sVm", MATCH_XT_VABAU_VX, MASK_XT_VABAU_VX, match_opcode, 0 }, +{"xt.vabau.vi", 0, INSN_CLASS_XXTVCODER, "Vd,Vt,VjVm", MATCH_XT_VABAU_VI, MASK_XT_VABAU_VI, match_opcode, 0 }, +{"xt.vwabd.vv", 0, INSN_CLASS_XXTVCODER, "Vd,Vt,VsVm", MATCH_XT_VWABD_VV, MASK_XT_VWABD_VV, match_opcode, 0 }, +{"xt.vwabd.vx", 0, INSN_CLASS_XXTVCODER, "Vd,Vt,sVm", MATCH_XT_VWABD_VX, MASK_XT_VWABD_VX, match_opcode, 0 }, +{"xt.vwaba.vv", 0, INSN_CLASS_XXTVCODER, "Vd,Vt,VsVm", MATCH_XT_VWABA_VV, MASK_XT_VWABA_VV, match_opcode, 0 }, +{"xt.vwaba.vx", 0, INSN_CLASS_XXTVCODER, "Vd,Vt,sVm", MATCH_XT_VWABA_VX, MASK_XT_VWABA_VX, match_opcode, 0 }, +{"xt.vwabau.vv", 0, INSN_CLASS_XXTVCODER, "Vd,Vt,VsVm", MATCH_XT_VWABAU_VV, MASK_XT_VWABAU_VV, match_opcode, 0 }, +{"xt.vwabau.vx", 0, INSN_CLASS_XXTVCODER, "Vd,Vt,sVm", MATCH_XT_VWABAU_VX, MASK_XT_VWABAU_VX, match_opcode, 0 }, +{"xt.vwabdu.vv", 0, INSN_CLASS_XXTVCODER, "Vd,Vt,VsVm", MATCH_XT_VWABDU_VV, MASK_XT_VWABDU_VV, match_opcode, 0 }, +{"xt.vwabdu.vx", 0, INSN_CLASS_XXTVCODER, "Vd,Vt,sVm", MATCH_XT_VWABDU_VX, MASK_XT_VWABDU_VX, match_opcode, 0 }, +{"xt.vfabd.vv", 0, INSN_CLASS_XXTVCODER, "Vd,Vt,VsVm", MATCH_XT_VFABD_VV, MASK_XT_VFABD_VV, match_opcode, 0 }, +{"xt.vfabd.vf", 0, INSN_CLASS_XXTVCODER, "Vd,Vt,SVm", MATCH_XT_VFABD_VF, MASK_XT_VFABD_VF, match_opcode, 0 }, +{"xt.vabsmax.vv", 0, INSN_CLASS_XXTVCODER, "Vd,Vt,VsVm", MATCH_XT_VABSMAX_VV, MASK_XT_VABSMAX_VV, match_opcode, 0 }, + /* Vendor-specific (Ventana Microsystems) XVentanaCondOps instructions */ {"vt.maskc", 64, INSN_CLASS_XVENTANACONDOPS, "d,s,t", MATCH_VT_MASKC, MASK_VT_MASKC, match_opcode, 0 }, {"vt.maskcn", 64, INSN_CLASS_XVENTANACONDOPS, "d,s,t", MATCH_VT_MASKCN, MASK_VT_MASKCN, match_opcode, 0 }, -- 2.46.0