Re: [PATCH] x86: accept LOCK on control register accesses only with ModR/M.reg == 0
Jan Beulich <[email protected]>
| Newsgroups | gmane.comp.gnu.binutils |
|---|---|
| Message-ID | <[email protected]> |
On 10.07.2026 08:20, Jan Beulich wrote: > Reportedly (e.g. [1]) the LOCK handling is special to %cr0 / %cr8 only. > Deal with it this way also in assembler and disassembler. > > For the assembler also introduce a separate feature indicator: Not all > 64-bit CPUs support this insn form; only most AMD (and presumably all > Hygon) ones do. Register names %cr9 ... %cr15 thus become invalid outside > of 64-bit mode altogether (unprefixed forms become ordinary symbol names), > while %cr8's availability outside of 64-bit mode now depends on the new > feature indicator. > > For the disassembler don't limit this handling to non-64-bit modes. Use > of LOCK is similarly permitted in 64-bit mode. Instead don't handle LOCK > this way when "intel64" was specified as an option. > > [1] https://lists.xen.org/archives/html/xen-devel/2026-07/msg00391.html Argh - the hunks below are also needed. I really don't understand why there still is this kind of needless duplication in ilp32/. When the expectations aren't different between the two modes, there really should be only one instance (that then needs modifying when a testcase is extended). Jan --- a/gas/testsuite/gas/i386/ilp32/x86-64-crx.d +++ b/gas/testsuite/gas/i386/ilp32/x86-64-crx.d @@ -1,21 +1,4 @@ #source: ../x86-64-crx.s #objdump: -dw #name: x86-64 (ILP32) control register related opcodes - -.*: +file format .* - -Disassembly of section .text: - -0+ <_start>: -[ ]*[0-9a-f]+: 44 0f 20 c0[ ]+movq?[ ]+?%cr8,%rax -[ ]*[0-9a-f]+: 44 0f 20 c7[ ]+movq?[ ]+?%cr8,%rdi -[ ]*[0-9a-f]+: 44 0f 22 c0[ ]+movq?[ ]+?%rax,%cr8 -[ ]*[0-9a-f]+: 44 0f 22 c7[ ]+movq?[ ]+?%rdi,%cr8 -[ ]*[0-9a-f]+: 44 0f 20 c0[ ]+movq?[ ]+?%cr8,%rax -[ ]*[0-9a-f]+: 44 0f 20 c7[ ]+movq?[ ]+?%cr8,%rdi -[ ]*[0-9a-f]+: 44 0f 22 c0[ ]+movq?[ ]+?%rax,%cr8 -[ ]*[0-9a-f]+: 44 0f 22 c7[ ]+movq?[ ]+?%rdi,%cr8 -[ ]*[0-9a-f]+: 44 0f 20 c0[ ]+movq?[ ]+?%cr8,%rax -[ ]*[0-9a-f]+: 44 0f 20 c7[ ]+movq?[ ]+?%cr8,%rdi -[ ]*[0-9a-f]+: 44 0f 22 c0[ ]+movq?[ ]+?%rax,%cr8 -[ ]*[0-9a-f]+: 44 0f 22 c7[ ]+movq?[ ]+?%rdi,%cr8 +#dump: ../x86-64-crx.d --- a/gas/testsuite/gas/i386/ilp32/x86-64-crx-suffix.d +++ b/gas/testsuite/gas/i386/ilp32/x86-64-crx-suffix.d @@ -1,21 +1,4 @@ #source: ../x86-64-crx.s #objdump: -dwMsuffix #name: x86-64 (ILP32) control register related opcodes (with suffixes) - -.*: +file format .* - -Disassembly of section .text: - -0+ <_start>: -[ ]*[0-9a-f]+: 44 0f 20 c0[ ]+movq[ ]+?%cr8,%rax -[ ]*[0-9a-f]+: 44 0f 20 c7[ ]+movq[ ]+?%cr8,%rdi -[ ]*[0-9a-f]+: 44 0f 22 c0[ ]+movq[ ]+?%rax,%cr8 -[ ]*[0-9a-f]+: 44 0f 22 c7[ ]+movq[ ]+?%rdi,%cr8 -[ ]*[0-9a-f]+: 44 0f 20 c0[ ]+movq[ ]+?%cr8,%rax -[ ]*[0-9a-f]+: 44 0f 20 c7[ ]+movq[ ]+?%cr8,%rdi -[ ]*[0-9a-f]+: 44 0f 22 c0[ ]+movq[ ]+?%rax,%cr8 -[ ]*[0-9a-f]+: 44 0f 22 c7[ ]+movq[ ]+?%rdi,%cr8 -[ ]*[0-9a-f]+: 44 0f 20 c0[ ]+movq[ ]+?%cr8,%rax -[ ]*[0-9a-f]+: 44 0f 20 c7[ ]+movq[ ]+?%cr8,%rdi -[ ]*[0-9a-f]+: 44 0f 22 c0[ ]+movq[ ]+?%rax,%cr8 -[ ]*[0-9a-f]+: 44 0f 22 c7[ ]+movq[ ]+?%rdi,%cr8 +#dump: ../x86-64-crx-suffix.d