[PATCH] aarch64: Remove cast from struct initializer
Alice Carlotti <[email protected]>
| Newsgroups | gmane.comp.gnu.binutils |
|---|---|
| Message-ID | <[email protected]> |
Here is a patch that removes the cast. I haven't tested whether it fixes the
compilation issue. I was hoping to reproduce the error on godbolt.org, but I
have been unsuccessful.
Can you let me know if this fixes the issue for you?
Thanks,
Alice
---
This hopefully fixes the error reported when compiling with GCC 4.9:
opcodes/aarch64-opc-2.c:29:3: error: initializer element is not constant
{AARCH64_OPND_CLASS_INT_REG, "Rd", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (0, 5)}, "an integer register"},
^
opcodes/aarch64-opc-2.c:29:3: error: (near initialization for ‘aarch64_operands[1].fields[0]’)
diff --git a/opcodes/aarch64-gen.c b/opcodes/aarch64-gen.c
index 3dd3e86f86007451e0a6fffa8f202034ef468ffe..2216e550c8c889972d62237a50379a2bbd861f9e 100644
--- a/opcodes/aarch64-gen.c
+++ b/opcodes/aarch64-gen.c
@@ -1078,9 +1078,9 @@ print_operand_table (void)
continue;
if (j != 0)
str += sprintf (str, ", ");
- str += sprintf (str, "AARCH64_FIELD%s (%d, %d)",
- field.is_const ? "_CONST" : "",
- field.num, field.width);
+ str += sprintf (str, "{%d, %d, %s}",
+ field.width, field.num,
+ field.is_const ? "true" : "false");
}
printf (" {AARCH64_OPND_CLASS_%s, \"%s\", %s, {%s}, \"%s\"},\n",
opnd->class, opnd->str, flags, fields, opnd->desc);
diff --git a/opcodes/aarch64-opc-2.c b/opcodes/aarch64-opc-2.c
index 7e48d7114b03ef244206762d219db32d2946c67c..1ffe9e807f16888c2a3a929bb911a07b88d32483 100644
--- a/opcodes/aarch64-opc-2.c
+++ b/opcodes/aarch64-opc-2.c
@@ -26,57 +26,57 @@
const struct aarch64_operand aarch64_operands[] =
{
{AARCH64_OPND_CLASS_NIL, "", 0, {}, "<none>"},
- {AARCH64_OPND_CLASS_INT_REG, "Rd", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (0, 5)}, "an integer register"},
- {AARCH64_OPND_CLASS_INT_REG, "Rn", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (5, 5)}, "an integer register"},
- {AARCH64_OPND_CLASS_INT_REG, "Rm", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (16, 5)}, "an integer register"},
- {AARCH64_OPND_CLASS_INT_REG, "Rt", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (0, 5)}, "an integer register"},
- {AARCH64_OPND_CLASS_INT_REG, "Rt2", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (10, 5)}, "an integer register"},
+ {AARCH64_OPND_CLASS_INT_REG, "Rd", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {{5, 0, false}}, "an integer register"},
+ {AARCH64_OPND_CLASS_INT_REG, "Rn", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {{5, 5, false}}, "an integer register"},
+ {AARCH64_OPND_CLASS_INT_REG, "Rm", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {{5, 16, false}}, "an integer register"},
+ {AARCH64_OPND_CLASS_INT_REG, "Rt", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {{5, 0, false}}, "an integer register"},
+ {AARCH64_OPND_CLASS_INT_REG, "Rt2", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {{5, 10, false}}, "an integer register"},
{AARCH64_OPND_CLASS_INT_REG, "X16", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {}, "X16"},
- {AARCH64_OPND_CLASS_INT_REG, "Rt_LS64", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (0, 5)}, "an integer register"},
- {AARCH64_OPND_CLASS_INT_REG, "Rt_SP", OPD_F_MAYBE_SP | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (0, 5)}, "an integer or stack pointer register"},
- {AARCH64_OPND_CLASS_INT_REG, "Rs", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (16, 5)}, "an integer register"},
- {AARCH64_OPND_CLASS_INT_REG, "Ra", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (10, 5)}, "an integer register"},
- {AARCH64_OPND_CLASS_INT_REG, "Rt_SYS", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (0, 5)}, "an integer register"},
- {AARCH64_OPND_CLASS_INT_REG, "Rd_SP", OPD_F_MAYBE_SP | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (0, 5)}, "an integer or stack pointer register"},
- {AARCH64_OPND_CLASS_INT_REG, "Rn_SP", OPD_F_MAYBE_SP | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (5, 5)}, "an integer or stack pointer register"},
- {AARCH64_OPND_CLASS_INT_REG, "Rm_SP", OPD_F_MAYBE_SP | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (16, 5)}, "an integer or stack pointer register"},
+ {AARCH64_OPND_CLASS_INT_REG, "Rt_LS64", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {{5, 0, false}}, "an integer register"},
+ {AARCH64_OPND_CLASS_INT_REG, "Rt_SP", OPD_F_MAYBE_SP | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {{5, 0, false}}, "an integer or stack pointer register"},
+ {AARCH64_OPND_CLASS_INT_REG, "Rs", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {{5, 16, false}}, "an integer register"},
+ {AARCH64_OPND_CLASS_INT_REG, "Ra", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {{5, 10, false}}, "an integer register"},
+ {AARCH64_OPND_CLASS_INT_REG, "Rt_SYS", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {{5, 0, false}}, "an integer register"},
+ {AARCH64_OPND_CLASS_INT_REG, "Rd_SP", OPD_F_MAYBE_SP | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {{5, 0, false}}, "an integer or stack pointer register"},
+ {AARCH64_OPND_CLASS_INT_REG, "Rn_SP", OPD_F_MAYBE_SP | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {{5, 5, false}}, "an integer or stack pointer register"},
+ {AARCH64_OPND_CLASS_INT_REG, "Rm_SP", OPD_F_MAYBE_SP | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {{5, 16, false}}, "an integer or stack pointer register"},
{AARCH64_OPND_CLASS_INT_REG, "PAIRREG", OPD_F_HAS_EXTRACTOR, {}, "the second reg of a pair"},
{AARCH64_OPND_CLASS_INT_REG, "PAIRREG_OR_XZR", OPD_F_HAS_EXTRACTOR, {}, "the second reg of a pair"},
{AARCH64_OPND_CLASS_MODIFIED_REG, "Rm_EXT", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {}, "an integer register with optional extension"},
{AARCH64_OPND_CLASS_MODIFIED_REG, "Rm_SFT", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {}, "an integer register with optional shift"},
{AARCH64_OPND_CLASS_MODIFIED_REG, "Rm_LSL", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {}, "an integer register with optional LSL shift"},
- {AARCH64_OPND_CLASS_FP_REG, "Fd", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (0, 5)}, "a floating-point register"},
- {AARCH64_OPND_CLASS_FP_REG, "Fn", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (5, 5)}, "a floating-point register"},
- {AARCH64_OPND_CLASS_FP_REG, "Fm", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (16, 5)}, "a floating-point register"},
- {AARCH64_OPND_CLASS_FP_REG, "Fa", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (10, 5)}, "a floating-point register"},
- {AARCH64_OPND_CLASS_FP_REG, "Ft", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (0, 5)}, "a floating-point register"},
- {AARCH64_OPND_CLASS_FP_REG, "Ft2", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (10, 5)}, "a floating-point register"},
- {AARCH64_OPND_CLASS_SISD_REG, "Sd", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (0, 5)}, "a SIMD scalar register"},
- {AARCH64_OPND_CLASS_SISD_REG, "Sn", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (5, 5)}, "a SIMD scalar register"},
- {AARCH64_OPND_CLASS_SISD_REG, "Sm", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (16, 5)}, "a SIMD scalar register"},
- {AARCH64_OPND_CLASS_SIMD_REG, "Va", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (10, 5)}, "a SIMD vector register"},
- {AARCH64_OPND_CLASS_SIMD_REG, "Vd", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (0, 5)}, "a SIMD vector register"},
- {AARCH64_OPND_CLASS_SIMD_REG, "Vn", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (5, 5)}, "a SIMD vector register"},
- {AARCH64_OPND_CLASS_SIMD_REG, "Vm", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (16, 5)}, "a SIMD vector register"},
- {AARCH64_OPND_CLASS_FP_REG, "VdD1", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (0, 5)}, "the top half of a 128-bit FP/SIMD register"},
- {AARCH64_OPND_CLASS_FP_REG, "VnD1", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (5, 5)}, "the top half of a 128-bit FP/SIMD register"},
- {AARCH64_OPND_CLASS_SIMD_ELEMENT, "Ed", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (0, 5)}, "a SIMD vector element"},
- {AARCH64_OPND_CLASS_SIMD_ELEMENT, "En", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (5, 5)}, "a SIMD vector element"},
- {AARCH64_OPND_CLASS_SIMD_ELEMENT, "Em", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (16, 5)}, "a SIMD vector element"},
- {AARCH64_OPND_CLASS_SIMD_ELEMENT, "Em16", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (16, 5)}, "a SIMD vector element limited to V0-V15"},
- {AARCH64_OPND_CLASS_SIMD_ELEMENT, "Em8", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (16, 5)}, "a SIMD vector element limited to V0-V7"},
- {AARCH64_OPND_CLASS_SIMD_ELEMENT, "Em_INDEX1_14", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (14, 1), AARCH64_FIELD (16, 5)}, "a SIMD vector without a type qualifier encoding a bit index"},
- {AARCH64_OPND_CLASS_SIMD_ELEMENT, "Em_INDEX2_13", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (13, 2), AARCH64_FIELD (16, 5)}, "a SIMD vector without a type qualifier encoding a bit index"},
- {AARCH64_OPND_CLASS_SIMD_ELEMENT, "Em_INDEX3_12", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (12, 3), AARCH64_FIELD (16, 5)}, "a SIMD vector without a type qualifier encoding a bit index"},
- {AARCH64_OPND_CLASS_SIMD_REGLIST, "LVn", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (5, 5)}, "a SIMD vector register list"},
+ {AARCH64_OPND_CLASS_FP_REG, "Fd", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {{5, 0, false}}, "a floating-point register"},
+ {AARCH64_OPND_CLASS_FP_REG, "Fn", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {{5, 5, false}}, "a floating-point register"},
+ {AARCH64_OPND_CLASS_FP_REG, "Fm", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {{5, 16, false}}, "a floating-point register"},
+ {AARCH64_OPND_CLASS_FP_REG, "Fa", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {{5, 10, false}}, "a floating-point register"},
+ {AARCH64_OPND_CLASS_FP_REG, "Ft", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {{5, 0, false}}, "a floating-point register"},
+ {AARCH64_OPND_CLASS_FP_REG, "Ft2", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {{5, 10, false}}, "a floating-point register"},
+ {AARCH64_OPND_CLASS_SISD_REG, "Sd", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {{5, 0, false}}, "a SIMD scalar register"},
+ {AARCH64_OPND_CLASS_SISD_REG, "Sn", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {{5, 5, false}}, "a SIMD scalar register"},
+ {AARCH64_OPND_CLASS_SISD_REG, "Sm", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {{5, 16, false}}, "a SIMD scalar register"},
+ {AARCH64_OPND_CLASS_SIMD_REG, "Va", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {{5, 10, false}}, "a SIMD vector register"},
+ {AARCH64_OPND_CLASS_SIMD_REG, "Vd", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {{5, 0, false}}, "a SIMD vector register"},
+ {AARCH64_OPND_CLASS_SIMD_REG, "Vn", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {{5, 5, false}}, "a SIMD vector register"},
+ {AARCH64_OPND_CLASS_SIMD_REG, "Vm", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {{5, 16, false}}, "a SIMD vector register"},
+ {AARCH64_OPND_CLASS_FP_REG, "VdD1", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {{5, 0, false}}, "the top half of a 128-bit FP/SIMD register"},
+ {AARCH64_OPND_CLASS_FP_REG, "VnD1", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {{5, 5, false}}, "the top half of a 128-bit FP/SIMD register"},
+ {AARCH64_OPND_CLASS_SIMD_ELEMENT, "Ed", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {{5, 0, false}}, "a SIMD vector element"},
+ {AARCH64_OPND_CLASS_SIMD_ELEMENT, "En", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {{5, 5, false}}, "a SIMD vector element"},
+ {AARCH64_OPND_CLASS_SIMD_ELEMENT, "Em", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {{5, 16, false}}, "a SIMD vector element"},
+ {AARCH64_OPND_CLASS_SIMD_ELEMENT, "Em16", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {{5, 16, false}}, "a SIMD vector element limited to V0-V15"},
+ {AARCH64_OPND_CLASS_SIMD_ELEMENT, "Em8", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {{5, 16, false}}, "a SIMD vector element limited to V0-V7"},
+ {AARCH64_OPND_CLASS_SIMD_ELEMENT, "Em_INDEX1_14", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {{1, 14, false}, {5, 16, false}}, "a SIMD vector without a type qualifier encoding a bit index"},
+ {AARCH64_OPND_CLASS_SIMD_ELEMENT, "Em_INDEX2_13", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {{2, 13, false}, {5, 16, false}}, "a SIMD vector without a type qualifier encoding a bit index"},
+ {AARCH64_OPND_CLASS_SIMD_ELEMENT, "Em_INDEX3_12", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {{3, 12, false}, {5, 16, false}}, "a SIMD vector without a type qualifier encoding a bit index"},
+ {AARCH64_OPND_CLASS_SIMD_REGLIST, "LVn", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {{5, 5, false}}, "a SIMD vector register list"},
{AARCH64_OPND_CLASS_SIMD_REGLIST, "LVt", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {}, "a SIMD vector register list"},
{AARCH64_OPND_CLASS_SIMD_REGLIST, "LVt_AL", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {}, "a SIMD vector register list"},
- {AARCH64_OPND_CLASS_SIMD_REGLIST, "LVn_LUT", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (5, 5)}, "a SIMD vector register list"},
+ {AARCH64_OPND_CLASS_SIMD_REGLIST, "LVn_LUT", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {{5, 5, false}}, "a SIMD vector register list"},
{AARCH64_OPND_CLASS_SIMD_REGLIST, "LEt", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {}, "a SIMD vector element list"},
- {AARCH64_OPND_CLASS_IMMEDIATE, "CRn", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (12, 4)}, "a 4-bit opcode field named for historical reasons C0 - C15"},
- {AARCH64_OPND_CLASS_IMMEDIATE, "CRm", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (8, 4)}, "a 4-bit opcode field named for historical reasons C0 - C15"},
- {AARCH64_OPND_CLASS_IMMEDIATE, "IDX", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (11, 4)}, "an immediate as the index of the least significant byte"},
- {AARCH64_OPND_CLASS_IMMEDIATE, "MASK", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (0, 4)}, "an immediate as the index of the least significant byte"},
+ {AARCH64_OPND_CLASS_IMMEDIATE, "CRn", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {{4, 12, false}}, "a 4-bit opcode field named for historical reasons C0 - C15"},
+ {AARCH64_OPND_CLASS_IMMEDIATE, "CRm", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {{4, 8, false}}, "a 4-bit opcode field named for historical reasons C0 - C15"},
+ {AARCH64_OPND_CLASS_IMMEDIATE, "IDX", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {{4, 11, false}}, "an immediate as the index of the least significant byte"},
+ {AARCH64_OPND_CLASS_IMMEDIATE, "MASK", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {{4, 0, false}}, "an immediate as the index of the least significant byte"},
{AARCH64_OPND_CLASS_IMMEDIATE, "IMM_VLSL", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {}, "a left shift amount for an AdvSIMD register"},
{AARCH64_OPND_CLASS_IMMEDIATE, "IMM_VLSR", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {}, "a right shift amount for an AdvSIMD register"},
{AARCH64_OPND_CLASS_IMMEDIATE, "SIMD_IMM", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {}, "an immediate"},
@@ -85,54 +85,54 @@ const struct aarch64_operand aarch64_operands[] =
{AARCH64_OPND_CLASS_IMMEDIATE, "SHLL_IMM", OPD_F_HAS_EXTRACTOR, {}, "an immediate shift amount of 8, 16 or 32"},
{AARCH64_OPND_CLASS_IMMEDIATE, "IMM0", 0, {}, "0"},
{AARCH64_OPND_CLASS_IMMEDIATE, "FPIMM0", 0, {}, "0.0"},
- {AARCH64_OPND_CLASS_IMMEDIATE, "FPIMM", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (13, 8)}, "an 8-bit floating-point constant"},
- {AARCH64_OPND_CLASS_IMMEDIATE, "IMMR", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (16, 6)}, "the right rotate amount"},
- {AARCH64_OPND_CLASS_IMMEDIATE, "IMMS", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (10, 6)}, "the leftmost bit number to be moved from the source"},
- {AARCH64_OPND_CLASS_IMMEDIATE, "WIDTH", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (10, 6)}, "the width of the bit-field"},
- {AARCH64_OPND_CLASS_IMMEDIATE, "IMM", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (10, 6)}, "an immediate"},
- {AARCH64_OPND_CLASS_IMMEDIATE, "IMM_2", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (15, 6)}, "an immediate"},
- {AARCH64_OPND_CLASS_IMMEDIATE, "IMMP1_2", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (15, 6)}, "an immediate plus 1"},
- {AARCH64_OPND_CLASS_IMMEDIATE, "IMMS1_2", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (15, 6)}, "an immediate minus 1"},
- {AARCH64_OPND_CLASS_IMMEDIATE, "UIMM3_OP1", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (16, 3)}, "a 3-bit unsigned immediate"},
- {AARCH64_OPND_CLASS_IMMEDIATE, "UIMM3_OP2", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (5, 3)}, "a 3-bit unsigned immediate"},
- {AARCH64_OPND_CLASS_IMMEDIATE, "UIMM4", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (8, 4)}, "a 4-bit unsigned immediate"},
- {AARCH64_OPND_CLASS_IMMEDIATE, "UIMM4_ADDG", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (10, 4)}, "a 4-bit unsigned Logical Address Tag modifier"},
- {AARCH64_OPND_CLASS_IMMEDIATE, "UIMM7", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (8, 4), AARCH64_FIELD (5, 3)}, "a 7-bit unsigned immediate"},
- {AARCH64_OPND_CLASS_IMMEDIATE, "UIMM10", OPD_F_SHIFT_BY_4 | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (16, 6)}, "a 10-bit unsigned multiple of 16"},
- {AARCH64_OPND_CLASS_IMMEDIATE, "BIT_NUM", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (31, 1), AARCH64_FIELD (19, 5)}, "the bit number to be tested"},
- {AARCH64_OPND_CLASS_IMMEDIATE, "EXCEPTION", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (5, 16)}, "a 16-bit unsigned immediate"},
- {AARCH64_OPND_CLASS_IMMEDIATE, "UNDEFINED", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (0, 16)}, "a 16-bit unsigned immediate"},
- {AARCH64_OPND_CLASS_IMMEDIATE, "CCMP_IMM", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (16, 5)}, "a 5-bit unsigned immediate"},
- {AARCH64_OPND_CLASS_IMMEDIATE, "SIMM5", OPD_F_SEXT | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (16, 5)}, "a 5-bit signed immediate"},
- {AARCH64_OPND_CLASS_IMMEDIATE, "NOT_BALANCED_10", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (10, 1)}, "an optional not balanced indicator (NB)"},
- {AARCH64_OPND_CLASS_IMMEDIATE, "NOT_BALANCED_17", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (17, 1)}, "an optional not balanced indicator (NB)"},
- {AARCH64_OPND_CLASS_IMMEDIATE, "NZCV", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (0, 4)}, "a flag bit specifier giving an alternative value for each flag"},
- {AARCH64_OPND_CLASS_IMMEDIATE, "LIMM", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (22, 1), AARCH64_FIELD (16, 6), AARCH64_FIELD (10, 6)}, "Logical immediate"},
- {AARCH64_OPND_CLASS_IMMEDIATE, "AIMM", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (22, 2), AARCH64_FIELD (10, 12)}, "a 12-bit unsigned immediate with optional left shift of 12 bits"},
- {AARCH64_OPND_CLASS_IMMEDIATE, "HALF", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (5, 16)}, "a 16-bit immediate with optional left shift"},
- {AARCH64_OPND_CLASS_IMMEDIATE, "FBITS", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (10, 6)}, "the number of bits after the binary point in the fixed-point value"},
+ {AARCH64_OPND_CLASS_IMMEDIATE, "FPIMM", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {{8, 13, false}}, "an 8-bit floating-point constant"},
+ {AARCH64_OPND_CLASS_IMMEDIATE, "IMMR", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {{6, 16, false}}, "the right rotate amount"},
+ {AARCH64_OPND_CLASS_IMMEDIATE, "IMMS", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {{6, 10, false}}, "the leftmost bit number to be moved from the source"},
+ {AARCH64_OPND_CLASS_IMMEDIATE, "WIDTH", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {{6, 10, false}}, "the width of the bit-field"},
+ {AARCH64_OPND_CLASS_IMMEDIATE, "IMM", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {{6, 10, false}}, "an immediate"},
+ {AARCH64_OPND_CLASS_IMMEDIATE, "IMM_2", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {{6, 15, false}}, "an immediate"},
+ {AARCH64_OPND_CLASS_IMMEDIATE, "IMMP1_2", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {{6, 15, false}}, "an immediate plus 1"},
+ {AARCH64_OPND_CLASS_IMMEDIATE, "IMMS1_2", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {{6, 15, false}}, "an immediate minus 1"},
+ {AARCH64_OPND_CLASS_IMMEDIATE, "UIMM3_OP1", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {{3, 16, false}}, "a 3-bit unsigned immediate"},
+ {AARCH64_OPND_CLASS_IMMEDIATE, "UIMM3_OP2", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {{3, 5, false}}, "a 3-bit unsigned immediate"},
+ {AARCH64_OPND_CLASS_IMMEDIATE, "UIMM4", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {{4, 8, false}}, "a 4-bit unsigned immediate"},
+ {AARCH64_OPND_CLASS_IMMEDIATE, "UIMM4_ADDG", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {{4, 10, false}}, "a 4-bit unsigned Logical Address Tag modifier"},
+ {AARCH64_OPND_CLASS_IMMEDIATE, "UIMM7", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {{4, 8, false}, {3, 5, false}}, "a 7-bit unsigned immediate"},
+ {AARCH64_OPND_CLASS_IMMEDIATE, "UIMM10", OPD_F_SHIFT_BY_4 | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {{6, 16, false}}, "a 10-bit unsigned multiple of 16"},
+ {AARCH64_OPND_CLASS_IMMEDIATE, "BIT_NUM", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {{1, 31, false}, {5, 19, false}}, "the bit number to be tested"},
+ {AARCH64_OPND_CLASS_IMMEDIATE, "EXCEPTION", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {{16, 5, false}}, "a 16-bit unsigned immediate"},
+ {AARCH64_OPND_CLASS_IMMEDIATE, "UNDEFINED", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {{16, 0, false}}, "a 16-bit unsigned immediate"},
+ {AARCH64_OPND_CLASS_IMMEDIATE, "CCMP_IMM", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {{5, 16, false}}, "a 5-bit unsigned immediate"},
+ {AARCH64_OPND_CLASS_IMMEDIATE, "SIMM5", OPD_F_SEXT | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {{5, 16, false}}, "a 5-bit signed immediate"},
+ {AARCH64_OPND_CLASS_IMMEDIATE, "NOT_BALANCED_10", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {{1, 10, false}}, "an optional not balanced indicator (NB)"},
+ {AARCH64_OPND_CLASS_IMMEDIATE, "NOT_BALANCED_17", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {{1, 17, false}}, "an optional not balanced indicator (NB)"},
+ {AARCH64_OPND_CLASS_IMMEDIATE, "NZCV", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {{4, 0, false}}, "a flag bit specifier giving an alternative value for each flag"},
+ {AARCH64_OPND_CLASS_IMMEDIATE, "LIMM", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {{1, 22, false}, {6, 16, false}, {6, 10, false}}, "Logical immediate"},
+ {AARCH64_OPND_CLASS_IMMEDIATE, "AIMM", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {{2, 22, false}, {12, 10, false}}, "a 12-bit unsigned immediate with optional left shift of 12 bits"},
+ {AARCH64_OPND_CLASS_IMMEDIATE, "HALF", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {{16, 5, false}}, "a 16-bit immediate with optional left shift"},
+ {AARCH64_OPND_CLASS_IMMEDIATE, "FBITS", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {{6, 10, false}}, "the number of bits after the binary point in the fixed-point value"},
{AARCH64_OPND_CLASS_IMMEDIATE, "IMM_MOV", 0, {}, "an immediate"},
- {AARCH64_OPND_CLASS_IMMEDIATE, "IMM_ROT1", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (11, 2)}, "a 2-bit rotation specifier for complex arithmetic operations"},
- {AARCH64_OPND_CLASS_IMMEDIATE, "IMM_ROT2", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (13, 2)}, "a 2-bit rotation specifier for complex arithmetic operations"},
- {AARCH64_OPND_CLASS_IMMEDIATE, "IMM_ROT3", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (12, 1)}, "a 1-bit rotation specifier for complex arithmetic operations"},
+ {AARCH64_OPND_CLASS_IMMEDIATE, "IMM_ROT1", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {{2, 11, false}}, "a 2-bit rotation specifier for complex arithmetic operations"},
+ {AARCH64_OPND_CLASS_IMMEDIATE, "IMM_ROT2", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {{2, 13, false}}, "a 2-bit rotation specifier for complex arithmetic operations"},
+ {AARCH64_OPND_CLASS_IMMEDIATE, "IMM_ROT3", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {{1, 12, false}}, "a 1-bit rotation specifier for complex arithmetic operations"},
{AARCH64_OPND_CLASS_COND, "COND", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {}, "a condition"},
{AARCH64_OPND_CLASS_COND, "COND1", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {}, "one of the standard conditions, excluding AL and NV."},
- {AARCH64_OPND_CLASS_ADDRESS, "ADDR_ADRP", OPD_F_SEXT | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (5, 19), AARCH64_FIELD (29, 2)}, "21-bit PC-relative address of a 4KB page"},
- {AARCH64_OPND_CLASS_ADDRESS, "ADDR_PCREL9", OPD_F_SEXT | OPD_F_SHIFT_BY_2 | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (5, 9)}, "9-bit PC-relative address"},
- {AARCH64_OPND_CLASS_ADDRESS, "ADDR_PCREL14", OPD_F_SEXT | OPD_F_SHIFT_BY_2 | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (5, 14)}, "14-bit PC-relative address"},
- {AARCH64_OPND_CLASS_ADDRESS, "ADDR_PCREL19", OPD_F_SEXT | OPD_F_SHIFT_BY_2 | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (5, 19)}, "19-bit PC-relative address"},
- {AARCH64_OPND_CLASS_ADDRESS, "ADDR_PCREL21", OPD_F_SEXT | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (5, 19), AARCH64_FIELD (29, 2)}, "21-bit PC-relative address"},
- {AARCH64_OPND_CLASS_ADDRESS, "ADDR_PCREL26", OPD_F_SEXT | OPD_F_SHIFT_BY_2 | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (0, 26)}, "26-bit PC-relative address"},
+ {AARCH64_OPND_CLASS_ADDRESS, "ADDR_ADRP", OPD_F_SEXT | OPD_F_HAS_EXTRACTOR, {{19, 5, false}, {2, 29, false}}, "21-bit PC-relative address of a 4KB page"},
+ {AARCH64_OPND_CLASS_ADDRESS, "ADDR_PCREL9", OPD_F_SEXT | OPD_F_SHIFT_BY_2 | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {{9, 5, false}}, "9-bit PC-relative address"},
+ {AARCH64_OPND_CLASS_ADDRESS, "ADDR_PCREL14", OPD_F_SEXT | OPD_F_SHIFT_BY_2 | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {{14, 5, false}}, "14-bit PC-relative address"},
+ {AARCH64_OPND_CLASS_ADDRESS, "ADDR_PCREL19", OPD_F_SEXT | OPD_F_SHIFT_BY_2 | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {{19, 5, false}}, "19-bit PC-relative address"},
+ {AARCH64_OPND_CLASS_ADDRESS, "ADDR_PCREL21", OPD_F_SEXT | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {{19, 5, false}, {2, 29, false}}, "21-bit PC-relative address"},
+ {AARCH64_OPND_CLASS_ADDRESS, "ADDR_PCREL26", OPD_F_SEXT | OPD_F_SHIFT_BY_2 | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {{26, 0, false}}, "26-bit PC-relative address"},
{AARCH64_OPND_CLASS_ADDRESS, "ADDR_SIMPLE", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {}, "an address with base register (no offset)"},
{AARCH64_OPND_CLASS_ADDRESS, "ADDR_REGOFF", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {}, "an address with register offset"},
- {AARCH64_OPND_CLASS_ADDRESS, "ADDR_SIMM7", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (15, 7), AARCH64_FIELD (24, 1)}, "an address with 7-bit signed immediate offset"},
- {AARCH64_OPND_CLASS_ADDRESS, "ADDR_SIMM9", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (12, 9), AARCH64_FIELD (11, 1)}, "an address with 9-bit signed immediate offset"},
- {AARCH64_OPND_CLASS_ADDRESS, "ADDR_SIMM10", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (5, 5), AARCH64_FIELD (22, 1), AARCH64_FIELD (12, 9), AARCH64_FIELD (11, 1)}, "an address with an optional 10-bit scaled, signed immediate offset"},
- {AARCH64_OPND_CLASS_ADDRESS, "ADDR_SIMM11", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (15, 7), AARCH64_FIELD (24, 1)}, "an address with 11-bit signed immediate (multiple of 16) offset"},
- {AARCH64_OPND_CLASS_ADDRESS, "ADDR_UIMM12", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (5, 5), AARCH64_FIELD (10, 12)}, "an address with scaled, unsigned immediate offset"},
- {AARCH64_OPND_CLASS_ADDRESS, "ADDR_SIMM13", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (12, 9), AARCH64_FIELD (11, 1)}, "an address with 13-bit signed immediate (multiple of 16) offset"},
+ {AARCH64_OPND_CLASS_ADDRESS, "ADDR_SIMM7", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {{7, 15, false}, {1, 24, false}}, "an address with 7-bit signed immediate offset"},
+ {AARCH64_OPND_CLASS_ADDRESS, "ADDR_SIMM9", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {{9, 12, false}, {1, 11, false}}, "an address with 9-bit signed immediate offset"},
+ {AARCH64_OPND_CLASS_ADDRESS, "ADDR_SIMM10", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {{5, 5, false}, {1, 22, false}, {9, 12, false}, {1, 11, false}}, "an address with an optional 10-bit scaled, signed immediate offset"},
+ {AARCH64_OPND_CLASS_ADDRESS, "ADDR_SIMM11", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {{7, 15, false}, {1, 24, false}}, "an address with 11-bit signed immediate (multiple of 16) offset"},
+ {AARCH64_OPND_CLASS_ADDRESS, "ADDR_UIMM12", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {{5, 5, false}, {12, 10, false}}, "an address with scaled, unsigned immediate offset"},
+ {AARCH64_OPND_CLASS_ADDRESS, "ADDR_SIMM13", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {{9, 12, false}, {1, 11, false}}, "an address with 13-bit signed immediate (multiple of 16) offset"},
{AARCH64_OPND_CLASS_ADDRESS, "SIMD_ADDR_SIMPLE", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {}, "an address with base register (no offset)"},
- {AARCH64_OPND_CLASS_ADDRESS, "ADDR_OFFSET", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (5, 5), AARCH64_FIELD (12, 9), AARCH64_FIELD (11, 1)}, "an address with an optional 8-bit signed immediate offset"},
+ {AARCH64_OPND_CLASS_ADDRESS, "ADDR_OFFSET", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {{5, 5, false}, {9, 12, false}, {1, 11, false}}, "an address with an optional 8-bit signed immediate offset"},
{AARCH64_OPND_CLASS_ADDRESS, "SIMD_ADDR_POST", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {}, "a post-indexed address with immediate or register increment"},
{AARCH64_OPND_CLASS_SYSTEM, "SYSREG", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {}, "a system register"},
{AARCH64_OPND_CLASS_SYSTEM, "SYSREG128", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {}, "a 128-bit system register"},
@@ -148,232 +148,232 @@ const struct aarch64_operand aarch64_operands[] =
{AARCH64_OPND_CLASS_SYSTEM, "BARRIER_DSB_NXS", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {}, "the DSB nXS option qualifier name SY, ISH, NSH, OSH or an optional 5-bit unsigned immediate"},
{AARCH64_OPND_CLASS_SYSTEM, "BARRIER_ISB", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {}, "the ISB option name SY or an optional 4-bit unsigned immediate"},
{AARCH64_OPND_CLASS_SYSTEM, "PRFOP", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {}, "a prefetch operation specifier"},
- {AARCH64_OPND_CLASS_SYSTEM, "RPRFMOP", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (15, 1), AARCH64_FIELD (12, 2), AARCH64_FIELD (0, 3)}, "a range prefetch operation specifier"},
+ {AARCH64_OPND_CLASS_SYSTEM, "RPRFMOP", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {{1, 15, false}, {2, 12, false}, {3, 0, false}}, "a range prefetch operation specifier"},
{AARCH64_OPND_CLASS_SYSTEM, "BARRIER_PSB", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {}, "the PSB/TSB option name CSYNC"},
{AARCH64_OPND_CLASS_SYSTEM, "BARRIER_GCSB", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {}, "the GCSB option name DSYNC"},
{AARCH64_OPND_CLASS_SYSTEM, "BTI_TARGET", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {}, "BTI targets r/j/c/jc"},
{AARCH64_OPND_CLASS_SYSTEM, "STSHH_POLICY", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {}, "an STSHH policy (keep/strm)"},
{AARCH64_OPND_CLASS_SYSTEM, "SHUH_PHINT", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {}, "an optional priority hint (ph)"},
- {AARCH64_OPND_CLASS_SYSTEM, "BRBOP", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (5, 1)}, "Branch Record Buffer operation operand"},
- {AARCH64_OPND_CLASS_INT_REG, "Rt_IN_SYS_ALIASES", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (0, 5)}, "Rt register with defaults for SYS aliases"},
- {AARCH64_OPND_CLASS_INT_REG, "LSE128_Rt", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (0, 5)}, "an integer register"},
- {AARCH64_OPND_CLASS_INT_REG, "LSE128_Rt2", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (16, 5)}, "an integer register"},
- {AARCH64_OPND_CLASS_ADDRESS, "SVE_ADDR_RI_S4x16", 4 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (5, 5)}, "an address with a 4-bit signed offset, multiplied by 16"},
- {AARCH64_OPND_CLASS_ADDRESS, "SVE_ADDR_RI_S4x32", 5 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (5, 5)}, "an address with a 4-bit signed offset, multiplied by 32"},
- {AARCH64_OPND_CLASS_ADDRESS, "SVE_ADDR_RI_S4xVL", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (5, 5)}, "an address with a 4-bit signed offset, multiplied by VL"},
- {AARCH64_OPND_CLASS_ADDRESS, "SVE_ADDR_RI_S4x2xVL", 1 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (5, 5)}, "an address with a 4-bit signed offset, multiplied by 2*VL"},
- {AARCH64_OPND_CLASS_ADDRESS, "SVE_ADDR_RI_S4x3xVL", 2 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (5, 5)}, "an address with a 4-bit signed offset, multiplied by 3*VL"},
- {AARCH64_OPND_CLASS_ADDRESS, "SVE_ADDR_RI_S4x4xVL", 3 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (5, 5)}, "an address with a 4-bit signed offset, multiplied by 4*VL"},
- {AARCH64_OPND_CLASS_ADDRESS, "SVE_ADDR_RI_S6xVL", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (5, 5)}, "an address with a 6-bit signed offset, multiplied by VL"},
- {AARCH64_OPND_CLASS_ADDRESS, "SVE_ADDR_RI_S9xVL", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (5, 5)}, "an address with a 9-bit signed offset, multiplied by VL"},
- {AARCH64_OPND_CLASS_ADDRESS, "SVE_ADDR_RI_U6", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (5, 5)}, "an address with a 6-bit unsigned offset"},
- {AARCH64_OPND_CLASS_ADDRESS, "SVE_ADDR_RI_U6x2", 1 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (5, 5)}, "an address with a 6-bit unsigned offset, multiplied by 2"},
- {AARCH64_OPND_CLASS_ADDRESS, "SVE_ADDR_RI_U6x4", 2 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (5, 5)}, "an address with a 6-bit unsigned offset, multiplied by 4"},
- {AARCH64_OPND_CLASS_ADDRESS, "SVE_ADDR_RI_U6x8", 3 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (5, 5)}, "an address with a 6-bit unsigned offset, multiplied by 8"},
- {AARCH64_OPND_CLASS_ADDRESS, "SVE_ADDR_RR", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (5, 5), AARCH64_FIELD (16, 5)}, "an address with a scalar register offset"},
- {AARCH64_OPND_CLASS_ADDRESS, "SVE_ADDR_RR_LSL1", 1 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (5, 5), AARCH64_FIELD (16, 5)}, "an address with a scalar register offset"},
- {AARCH64_OPND_CLASS_ADDRESS, "SVE_ADDR_RR_LSL2", 2 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (5, 5), AARCH64_FIELD (16, 5)}, "an address with a scalar register offset"},
- {AARCH64_OPND_CLASS_ADDRESS, "SVE_ADDR_RR_LSL3", 3 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (5, 5), AARCH64_FIELD (16, 5)}, "an address with a scalar register offset"},
- {AARCH64_OPND_CLASS_ADDRESS, "SVE_ADDR_RR_LSL4", 4 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (5, 5), AARCH64_FIELD (16, 5)}, "an address with a scalar register offset"},
- {AARCH64_OPND_CLASS_ADDRESS, "SVE_ADDR_RM", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (5, 5), AARCH64_FIELD (16, 5)}, "an address with a scalar register offset"},
- {AARCH64_OPND_CLASS_ADDRESS, "SVE_ADDR_RM_LSL1", 1 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (5, 5), AARCH64_FIELD (16, 5)}, "an address with a scalar register offset"},
- {AARCH64_OPND_CLASS_ADDRESS, "SVE_ADDR_RM_LSL2", 2 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (5, 5), AARCH64_FIELD (16, 5)}, "an address with a scalar register offset"},
- {AARCH64_OPND_CLASS_ADDRESS, "SVE_ADDR_RM_LSL3", 3 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (5, 5), AARCH64_FIELD (16, 5)}, "an address with a scalar register offset"},
- {AARCH64_OPND_CLASS_ADDRESS, "SVE_ADDR_RM_LSL4", 4 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (5, 5), AARCH64_FIELD (16, 5)}, "an address with a scalar register offset"},
- {AARCH64_OPND_CLASS_ADDRESS, "SVE_ADDR_RX", (0 << OPD_F_OD_LSB) | OPD_F_NO_ZR | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (5, 5), AARCH64_FIELD (16, 5)}, "an address with a scalar register offset"},
- {AARCH64_OPND_CLASS_ADDRESS, "SVE_ADDR_RX_LSL1", (1 << OPD_F_OD_LSB) | OPD_F_NO_ZR | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (5, 5), AARCH64_FIELD (16, 5)}, "an address with a scalar register offset"},
- {AARCH64_OPND_CLASS_ADDRESS, "SVE_ADDR_RX_LSL2", (2 << OPD_F_OD_LSB) | OPD_F_NO_ZR | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (5, 5), AARCH64_FIELD (16, 5)}, "an address with a scalar register offset"},
- {AARCH64_OPND_CLASS_ADDRESS, "SVE_ADDR_RX_LSL3", (3 << OPD_F_OD_LSB) | OPD_F_NO_ZR | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (5, 5), AARCH64_FIELD (16, 5)}, "an address with a scalar register offset"},
- {AARCH64_OPND_CLASS_ADDRESS, "SVE_ADDR_RX_LSL4", (4 << OPD_F_OD_LSB) | OPD_F_NO_ZR | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (5, 5), AARCH64_FIELD (16, 5)}, "an address with a scalar register offset"},
- {AARCH64_OPND_CLASS_ADDRESS, "SVE_ADDR_ZX", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (5, 5), AARCH64_FIELD (16, 5)}, "vector of address with a scalar register offset"},
- {AARCH64_OPND_CLASS_ADDRESS, "SVE_ADDR_RZ", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (5, 5), AARCH64_FIELD (16, 5)}, "an address with a vector register offset"},
- {AARCH64_OPND_CLASS_ADDRESS, "SVE_ADDR_RZ_LSL1", 1 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (5, 5), AARCH64_FIELD (16, 5)}, "an address with a vector register offset"},
- {AARCH64_OPND_CLASS_ADDRESS, "SVE_ADDR_RZ_LSL2", 2 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (5, 5), AARCH64_FIELD (16, 5)}, "an address with a vector register offset"},
- {AARCH64_OPND_CLASS_ADDRESS, "SVE_ADDR_RZ_LSL3", 3 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (5, 5), AARCH64_FIELD (16, 5)}, "an address with a vector register offset"},
- {AARCH64_OPND_CLASS_ADDRESS, "SVE_ADDR_RZ_XTW_14", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (5, 5), AARCH64_FIELD (16, 5), AARCH64_FIELD (14, 1)}, "an address with a vector register offset"},
- {AARCH64_OPND_CLASS_ADDRESS, "SVE_ADDR_RZ_XTW_22", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (5, 5), AARCH64_FIELD (16, 5), AARCH64_FIELD (22, 1)}, "an address with a vector register offset"},
- {AARCH64_OPND_CLASS_ADDRESS, "SVE_ADDR_RZ_XTW1_14", 1 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (5, 5), AARCH64_FIELD (16, 5), AARCH64_FIELD (14, 1)}, "an address with a vector register offset"},
- {AARCH64_OPND_CLASS_ADDRESS, "SVE_ADDR_RZ_XTW1_22", 1 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (5, 5), AARCH64_FIELD (16, 5), AARCH64_FIELD (22, 1)}, "an address with a vector register offset"},
- {AARCH64_OPND_CLASS_ADDRESS, "SVE_ADDR_RZ_XTW2_14", 2 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (5, 5), AARCH64_FIELD (16, 5), AARCH64_FIELD (14, 1)}, "an address with a vector register offset"},
- {AARCH64_OPND_CLASS_ADDRESS, "SVE_ADDR_RZ_XTW2_22", 2 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (5, 5), AARCH64_FIELD (16, 5), AARCH64_FIELD (22, 1)}, "an address with a vector register offset"},
- {AARCH64_OPND_CLASS_ADDRESS, "SVE_ADDR_RZ_XTW3_14", 3 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (5, 5), AARCH64_FIELD (16, 5), AARCH64_FIELD (14, 1)}, "an address with a vector register offset"},
- {AARCH64_OPND_CLASS_ADDRESS, "SVE_ADDR_RZ_XTW3_22", 3 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (5, 5), AARCH64_FIELD (16, 5), AARCH64_FIELD (22, 1)}, "an address with a vector register offset"},
- {AARCH64_OPND_CLASS_ADDRESS, "SVE_ADDR_ZI_U5", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (5, 5)}, "an address with a 5-bit unsigned offset"},
- {AARCH64_OPND_CLASS_ADDRESS, "SVE_ADDR_ZI_U5x2", 1 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (5, 5)}, "an address with a 5-bit unsigned offset, multiplied by 2"},
- {AARCH64_OPND_CLASS_ADDRESS, "SVE_ADDR_ZI_U5x4", 2 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (5, 5)}, "an address with a 5-bit unsigned offset, multiplied by 4"},
- {AARCH64_OPND_CLASS_ADDRESS, "SVE_ADDR_ZI_U5x8", 3 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (5, 5)}, "an address with a 5-bit unsigned offset, multiplied by 8"},
- {AARCH64_OPND_CLASS_ADDRESS, "SVE_ADDR_ZZ_LSL", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (5, 5), AARCH64_FIELD (16, 5)}, "an address with a vector register offset"},
- {AARCH64_OPND_CLASS_ADDRESS, "SVE_ADDR_ZZ_SXTW", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (5, 5), AARCH64_FIELD (16, 5)}, "an address with a vector register offset"},
- {AARCH64_OPND_CLASS_ADDRESS, "SVE_ADDR_ZZ_UXTW", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (5, 5), AARCH64_FIELD (16, 5)}, "an address with a vector register offset"},
- {AARCH64_OPND_CLASS_IMMEDIATE, "SVE_AIMM", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (5, 9)}, "a 9-bit unsigned arithmetic operand"},
- {AARCH64_OPND_CLASS_IMMEDIATE, "SVE_ASIMM", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (5, 9)}, "a 9-bit signed arithmetic operand"},
- {AARCH64_OPND_CLASS_IMMEDIATE, "SVE_FPIMM8", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (5, 8)}, "an 8-bit floating-point immediate"},
- {AARCH64_OPND_CLASS_IMMEDIATE, "SVE_I1_HALF_ONE", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (5, 1)}, "either 0.5 or 1.0"},
- {AARCH64_OPND_CLASS_IMMEDIATE, "SVE_I1_HALF_TWO", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (5, 1)}, "either 0.5 or 2.0"},
- {AARCH64_OPND_CLASS_IMMEDIATE, "SVE_I1_ZERO_ONE", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (5, 1)}, "either 0.0 or 1.0"},
- {AARCH64_OPND_CLASS_IMMEDIATE, "SVE_IMM_ROT1", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (16, 1)}, "a 1-bit rotation specifier for complex arithmetic operations"},
- {AARCH64_OPND_CLASS_IMMEDIATE, "SVE_IMM_ROT2", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (10, 2)}, "a 2-bit rotation specifier for complex arithmetic operations"},
- {AARCH64_OPND_CLASS_IMMEDIATE, "SVE_IMM_ROT3", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (10, 1)}, "a 1-bit rotation specifier for complex arithmetic operations"},
- {AARCH64_OPND_CLASS_IMMEDIATE, "SVE_INV_LIMM", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (17, 1), AARCH64_FIELD (11, 6), AARCH64_FIELD (5, 6)}, "an inverted 13-bit logical immediate"},
- {AARCH64_OPND_CLASS_IMMEDIATE, "SVE_LIMM", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (17, 1), AARCH64_FIELD (11, 6), AARCH64_FIELD (5, 6)}, "a 13-bit logical immediate"},
- {AARCH64_OPND_CLASS_IMMEDIATE, "SVE_LIMM_MOV", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (17, 1), AARCH64_FIELD (11, 6), AARCH64_FIELD (5, 6)}, "a 13-bit logical move immediate"},
- {AARCH64_OPND_CLASS_IMMEDIATE, "SVE_PATTERN", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (5, 5)}, "an enumeration value such as POW2"},
- {AARCH64_OPND_CLASS_IMMEDIATE, "SVE_PATTERN_SCALED", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (5, 5)}, "an enumeration value such as POW2"},
- {AARCH64_OPND_CLASS_IMMEDIATE, "SVE_PRFOP", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (0, 4)}, "an enumeration value such as PLDL1KEEP"},
- {AARCH64_OPND_CLASS_PRED_REG, "SVE_Pd", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (0, 4)}, "an SVE predicate register"},
- {AARCH64_OPND_CLASS_PRED_REG, "SVE_PNd", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (0, 4)}, "an SVE predicate-as-counter register"},
- {AARCH64_OPND_CLASS_PRED_REG, "SVE_Pg3", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (10, 3)}, "an SVE predicate register"},
- {AARCH64_OPND_CLASS_PRED_REG, "SVE_Pg4_5", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (5, 4)}, "an SVE predicate register"},
- {AARCH64_OPND_CLASS_PRED_REG, "SVE_Pg4_10", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (10, 4)}, "an SVE predicate register"},
- {AARCH64_OPND_CLASS_PRED_REG, "SVE_PNg4_10", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (10, 4)}, "an SVE predicate-as-counter register"},
- {AARCH64_OPND_CLASS_PRED_REG, "SVE_Pg4_16", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (16, 4)}, "an SVE predicate register"},
- {AARCH64_OPND_CLASS_PRED_REG, "SVE_Pm", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (16, 4)}, "an SVE predicate register"},
- {AARCH64_OPND_CLASS_PRED_REG, "SVE_Pn", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (5, 4)}, "an SVE predicate register"},
- {AARCH64_OPND_CLASS_PRED_REG, "SVE_PNn", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (5, 4)}, "an SVE predicate register"},
- {AARCH64_OPND_CLASS_PRED_REG, "SVE_Pt", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (0, 4)}, "an SVE predicate register"},
- {AARCH64_OPND_CLASS_PRED_REG, "SVE_PNt", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (0, 4)}, "an SVE predicate register"},
- {AARCH64_OPND_CLASS_INT_REG, "SVE_Rm", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (5, 5)}, "an integer register or zero"},
- {AARCH64_OPND_CLASS_INT_REG, "SVE_Rn_SP", OPD_F_MAYBE_SP | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (16, 5)}, "an integer register or SP"},
- {AARCH64_OPND_CLASS_IMMEDIATE, "SVE_SHLIMM_PRED", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (22, 2), AARCH64_FIELD (5, 5)}, "a shift-left immediate operand"},
- {AARCH64_OPND_CLASS_IMMEDIATE, "SVE_SHLIMM_UNPRED", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (22, 2), AARCH64_FIELD (16, 5)}, "a shift-left immediate operand"},
- {AARCH64_OPND_CLASS_IMMEDIATE, "SVE_SHLIMM_UNPRED_22", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (22, 1), AARCH64_FIELD (19, 2), AARCH64_FIELD (16, 3)}, "a shift-left immediate operand"},
- {AARCH64_OPND_CLASS_IMMEDIATE, "SVE_SHRIMM_PRED", 1 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (22, 2), AARCH64_FIELD (5, 5)}, "a shift-right immediate operand"},
- {AARCH64_OPND_CLASS_IMMEDIATE, "SVE_SHRIMM_UNPRED", 1 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (22, 2), AARCH64_FIELD (16, 5)}, "a shift-right immediate operand"},
- {AARCH64_OPND_CLASS_IMMEDIATE, "SVE_SHRIMM_UNPRED_22", 2 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (22, 1), AARCH64_FIELD (19, 2), AARCH64_FIELD (16, 3)}, "a shift-right immediate operand"},
- {AARCH64_OPND_CLASS_IMMEDIATE, "SVE_SIMM5", OPD_F_SEXT | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (5, 5)}, "a 5-bit signed immediate"},
- {AARCH64_OPND_CLASS_IMMEDIATE, "SVE_SIMM5B", OPD_F_SEXT | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (16, 5)}, "a 5-bit signed immediate"},
- {AARCH64_OPND_CLASS_IMMEDIATE, "SVE_SIMM6", OPD_F_SEXT | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (5, 6)}, "a 6-bit signed immediate"},
- {AARCH64_OPND_CLASS_IMMEDIATE, "SVE_SIMM8", OPD_F_SEXT | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (5, 8)}, "an 8-bit signed immediate"},
- {AARCH64_OPND_CLASS_IMMEDIATE, "SVE_UIMM3", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (16, 3)}, "a 3-bit unsigned immediate"},
- {AARCH64_OPND_CLASS_IMMEDIATE, "SVE_UIMM7", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (14, 7)}, "a 7-bit unsigned immediate"},
- {AARCH64_OPND_CLASS_IMMEDIATE, "SVE_UIMM8", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (5, 8)}, "an 8-bit unsigned immediate"},
- {AARCH64_OPND_CLASS_IMMEDIATE, "SVE_UIMM8_53", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (16, 5), AARCH64_FIELD (10, 3)}, "an 8-bit unsigned immediate"},
- {AARCH64_OPND_CLASS_IMMEDIATE, "SVE_UIMM4", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (16, 4)}, "a 4-bit unsigned immediate"},
- {AARCH64_OPND_CLASS_SIMD_REG, "SVE_VZn", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (5, 5)}, "a SIMD register"},
- {AARCH64_OPND_CLASS_SIMD_REG, "SVE_Vd", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (0, 5)}, "a SIMD register"},
- {AARCH64_OPND_CLASS_SIMD_REG, "SVE_Vm", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (5, 5)}, "a SIMD register"},
- {AARCH64_OPND_CLASS_SIMD_REG, "SVE_Vn", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (5, 5)}, "a SIMD register"},
- {AARCH64_OPND_CLASS_ZA_ACCESS, "SME_ZA_array_vrsb_1", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (15, 1), AARCH64_FIELD (13, 2), AARCH64_FIELD (5, 3)}, "ZA0 tile"},
- {AARCH64_OPND_CLASS_ZA_ACCESS, "SME_ZA_array_vrsh_1", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (15, 1), AARCH64_FIELD (13, 2), AARCH64_FIELD (7, 1), AARCH64_FIELD (5, 2)}, "1 bit ZA tile"},
- {AARCH64_OPND_CLASS_ZA_ACCESS, "SME_ZA_array_vrss_1", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (15, 1), AARCH64_FIELD (13, 2), AARCH64_FIELD (6, 2), AARCH64_FIELD (5, 1)}, "2 ZA tile"},
- {AARCH64_OPND_CLASS_ZA_ACCESS, "SME_ZA_array_vrsd_1", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (15, 1), AARCH64_FIELD (13, 2), AARCH64_FIELD (5, 3)}, "3 ZA tile"},
- {AARCH64_OPND_CLASS_ZA_ACCESS, "SME_ZA_array_vrsb_2", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (15, 1), AARCH64_FIELD (13, 2), AARCH64_FIELD (5, 2)}, "ZA0 tile"},
- {AARCH64_OPND_CLASS_ZA_ACCESS, "SME_ZA_array_vrsh_2", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (15, 1), AARCH64_FIELD (13, 2), AARCH64_FIELD (6, 1), AARCH64_FIELD (5, 1)}, "1 bit ZA tile"},
- {AARCH64_OPND_CLASS_ZA_ACCESS, "SME_ZA_array_vrss_2", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (15, 1), AARCH64_FIELD (13, 2), AARCH64_FIELD (5, 2)}, "2 bit ZA tile"},
- {AARCH64_OPND_CLASS_ZA_ACCESS, "SME_ZA_array_vrsd_2", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (15, 1), AARCH64_FIELD (13, 2), AARCH64_FIELD (5, 3)}, "3 bit ZA tile"},
- {AARCH64_OPND_CLASS_ZA_ACCESS, "SME_ZA_ARRAY4", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (15, 1), AARCH64_FIELD (13, 2)}, "ZA tile to vector register"},
- {AARCH64_OPND_CLASS_SVE_REG, "SVE_Za_5", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (5, 5)}, "an SVE vector register"},
- {AARCH64_OPND_CLASS_SVE_REG, "SVE_Za_16", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (16, 5)}, "an SVE vector register"},
- {AARCH64_OPND_CLASS_SVE_REG, "SVE_Zd", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (0, 5)}, "an SVE vector register"},
- {AARCH64_OPND_CLASS_SVE_REG, "SVE_Zm_5", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (5, 5)}, "an SVE vector register"},
- {AARCH64_OPND_CLASS_SVE_REG, "SVE_Zm_16", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (16, 5)}, "an SVE vector register"},
- {AARCH64_OPND_CLASS_SVE_REG, "SVE_Zm1_23_INDEX", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (23, 1), AARCH64_FIELD (16, 5)}, "an indexed SVE vector register"},
- {AARCH64_OPND_CLASS_SVE_REG, "SVE_Zm2_22_INDEX", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (22, 2), AARCH64_FIELD (16, 5)}, "an indexed SVE vector register"},
- {AARCH64_OPND_CLASS_SVE_REG, "SVE_Zm3_INDEX", 3 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (16, 5)}, "an indexed SVE vector register"},
- {AARCH64_OPND_CLASS_SVE_REG, "SVE_Zm3_11_INDEX", 3 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (19, 2), AARCH64_FIELD (11, 1), AARCH64_FIELD (16, 3)}, "an indexed SVE vector register"},
- {AARCH64_OPND_CLASS_SVE_REG, "SVE_Zm3_12_INDEX", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (22, 2), AARCH64_FIELD (12, 1), AARCH64_FIELD (16, 5)}, "an indexed SVE vector register"},
- {AARCH64_OPND_CLASS_SVE_REG, "SVE_Zm3_19_INDEX", 3 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (19, 2), AARCH64_FIELD (16, 3)}, "an indexed SVE vector register"},
- {AARCH64_OPND_CLASS_SVE_REG, "SVE_Zm3_22_INDEX", 3 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (22, 1), AARCH64_FIELD (16, 5)}, "an indexed SVE vector register"},
- {AARCH64_OPND_CLASS_SVE_REG, "SVE_Zm3_10_INDEX", 3 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (19, 2), AARCH64_FIELD (10, 2), AARCH64_FIELD (16, 3)}, "an indexed SVE vector register"},
- {AARCH64_OPND_CLASS_SVE_REG, "SVE_Zm4_11_INDEX", 4 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (20, 1), AARCH64_FIELD (11, 1), AARCH64_FIELD (16, 4)}, "an indexed SVE vector register"},
- {AARCH64_OPND_CLASS_SVE_REG, "SVE_Zm4_INDEX", 4 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (16, 5)}, "an indexed SVE vector register"},
- {AARCH64_OPND_CLASS_SVE_REG, "SVE_Zn", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (5, 5)}, "an SVE vector register"},
- {AARCH64_OPND_CLASS_SVE_REG, "SVE_Zn_INDEX", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (5, 5), AARCH64_FIELD (22, 2), AARCH64_FIELD (16, 5)}, "an indexed SVE vector register"},
- {AARCH64_OPND_CLASS_SVE_REG, "SVE_Zn_5_INDEX", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (5, 5), AARCH64_FIELD (16, 5)}, "a 5 bit indexed SVE vector register"},
- {AARCH64_OPND_CLASS_SVE_REGLIST, "SVE_ZnxN", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (5, 5)}, "a list of SVE vector registers"},
- {AARCH64_OPND_CLASS_SVE_REG, "SVE_Zt", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (0, 5)}, "an SVE vector register"},
- {AARCH64_OPND_CLASS_SVE_REGLIST, "SVE_ZtxN", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (0, 5)}, "a list of SVE vector registers"},
- {AARCH64_OPND_CLASS_SVE_REGLIST, "SME_Zdnx2", 2 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (1, 4), AARCH64_FIELD_CONST (0, 1)}, "a list of SVE vector registers"},
- {AARCH64_OPND_CLASS_SVE_REGLIST, "SME_Zdnx4", 4 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (2, 3), AARCH64_FIELD_CONST (0, 2)}, "a list of SVE vector registers"},
- {AARCH64_OPND_CLASS_SVE_REG, "SME_Zm", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (16, 4)}, "an SVE vector register"},
- {AARCH64_OPND_CLASS_SVE_REG, "SME_Zm_17", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (17, 4)}, "an SVE vector register"},
- {AARCH64_OPND_CLASS_SVE_REG, "SME_Zn_6_3", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD_CONST (0, 1), AARCH64_FIELD (6, 3), AARCH64_FIELD_CONST (0, 1)}, "an SVE vector register"},
- {AARCH64_OPND_CLASS_SVE_REG, "SME_Zm_17_3", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD_CONST (1, 1), AARCH64_FIELD (17, 3), AARCH64_FIELD_CONST (0, 1)}, "an SVE vector register"},
- {AARCH64_OPND_CLASS_SVE_REGLIST, "SME_Znx2_6_3", 2 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD_CONST (0, 1), AARCH64_FIELD (6, 3), AARCH64_FIELD_CONST (0, 1)}, "a list of SVE vector registers"},
- {AARCH64_OPND_CLASS_SVE_REGLIST, "SME_Zmx2_17_3", 2 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD_CONST (1, 1), AARCH64_FIELD (17, 3), AARCH64_FIELD_CONST (0, 1)}, "a list of SVE vector registers"},
- {AARCH64_OPND_CLASS_SVE_REGLIST, "SME_Zmx2_INDEX_22", 2 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (16, 5), AARCH64_FIELD (22, 1)}, "a list of SVE vector registers with index"},
- {AARCH64_OPND_CLASS_SVE_REGLIST, "SME_Zmx2", 2 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (17, 4), AARCH64_FIELD_CONST (0, 1)}, "a list of SVE vector registers"},
- {AARCH64_OPND_CLASS_SVE_REGLIST, "SME_Zmx4", 4 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (18, 3), AARCH64_FIELD_CONST (0, 2)}, "a list of SVE vector registers"},
- {AARCH64_OPND_CLASS_SVE_REGLIST, "SME_Znx2", 2 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (6, 4), AARCH64_FIELD_CONST (0, 1)}, "a list of SVE vector registers"},
- {AARCH64_OPND_CLASS_SVE_REGLIST, "SME_Znx2_BIT_INDEX", 2 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (6, 4), AARCH64_FIELD_CONST (0, 1)}, "a list of SVE vector registers"},
- {AARCH64_OPND_CLASS_SVE_REGLIST, "SME_Znx4", 4 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (7, 3), AARCH64_FIELD_CONST (0, 2)}, "a list of SVE vector registers"},
- {AARCH64_OPND_CLASS_SVE_REGLIST, "SME_Zn7xN_UNTYPED", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (7, 3)}, "a list of untyped SVE vector registers"},
- {AARCH64_OPND_CLASS_SVE_REGLIST, "SME_Ztx2_STRIDED", 2 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (4, 1), AARCH64_FIELD (0, 3)}, "a list of SVE vector registers"},
- {AARCH64_OPND_CLASS_SVE_REGLIST, "SME_Ztx4_STRIDED", 4 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (4, 1), AARCH64_FIELD (0, 2)}, "a list of SVE vector registers"},
- {AARCH64_OPND_CLASS_SVE_REG, "SME_ZAda_1b", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (0, 1)}, "an SME ZA tile ZA0-ZA1"},
- {AARCH64_OPND_CLASS_SVE_REG, "SME_ZAda_2b", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (0, 2)}, "an SME ZA tile ZA0-ZA3"},
- {AARCH64_OPND_CLASS_SVE_REG, "SME_ZAda_3b", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (0, 3)}, "an SME ZA tile ZA0-ZA7"},
- {AARCH64_OPND_CLASS_ZA_ACCESS, "SME_ZA_HV_idx_src", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (22, 2), AARCH64_FIELD (16, 1), AARCH64_FIELD (15, 1), AARCH64_FIELD (13, 2), AARCH64_FIELD (5, 4)}, "an SME horizontal or vertical vector access register"},
- {AARCH64_OPND_CLASS_ZA_ACCESS, "SME_ZA_HV_idx_srcxN", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (15, 1), AARCH64_FIELD (13, 2), AARCH64_FIELD (5, 3)}, "an SME horizontal or vertical vector access register"},
- {AARCH64_OPND_CLASS_ZA_ACCESS, "SME_ZA_HV_idx_dest", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (22, 2), AARCH64_FIELD (16, 1), AARCH64_FIELD (15, 1), AARCH64_FIELD (13, 2), AARCH64_FIELD (0, 4)}, "an SME horizontal or vertical vector access register"},
- {AARCH64_OPND_CLASS_ZA_ACCESS, "SME_ZA_HV_idx_destxN", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (15, 1), AARCH64_FIELD (13, 2), AARCH64_FIELD (0, 3)}, "an SME horizontal or vertical vector access register"},
- {AARCH64_OPND_CLASS_SVE_REGLIST, "SME_Pdx2", 2 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (1, 3), AARCH64_FIELD_CONST (0, 1)}, "a list of SVE predicate registers"},
- {AARCH64_OPND_CLASS_SVE_REGLIST, "SME_PdxN", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (0, 4)}, "a list of SVE predicate registers"},
- {AARCH64_OPND_CLASS_PRED_REG, "SME_Pm", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (13, 3)}, "an SVE predicate register"},
- {AARCH64_OPND_CLASS_PRED_REG, "SME_PNd3", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD_CONST (1, 1), AARCH64_FIELD (0, 3)}, "an SVE predicate-as-counter register"},
- {AARCH64_OPND_CLASS_PRED_REG, "SME_PNg3", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD_CONST (1, 1), AARCH64_FIELD (10, 3)}, "an SVE predicate-as-counter register"},
- {AARCH64_OPND_CLASS_PRED_REG, "SME_PNn", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (5, 4)}, "an SVE predicate-as-counter register"},
- {AARCH64_OPND_CLASS_SVE_REG, "SME_PNn3_INDEX1", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (8, 1), AARCH64_FIELD_CONST (1, 2), AARCH64_FIELD (5, 3)}, "an indexed SVE predicate-as-counter register"},
- {AARCH64_OPND_CLASS_SVE_REG, "SME_PNn3_INDEX2", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (8, 2), AARCH64_FIELD_CONST (1, 2), AARCH64_FIELD (5, 3)}, "an indexed SVE predicate-as-counter register"},
- {AARCH64_OPND_CLASS_SVE_REG, "SME_list_of_64bit_tiles", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (0, 8)}, "a list of 64-bit ZA element tiles"},
- {AARCH64_OPND_CLASS_ZA_ACCESS, "SME_ZA_HV_idx_ldstr", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (22, 2), AARCH64_FIELD (24, 1), AARCH64_FIELD (15, 1), AARCH64_FIELD (13, 2), AARCH64_FIELD (0, 4)}, "an SME horizontal or vertical vector access register"},
- {AARCH64_OPND_CLASS_ZA_ACCESS, "SME_ZA_array_off1x4", 4 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (13, 2), AARCH64_FIELD (0, 1)}, "ZA array"},
- {AARCH64_OPND_CLASS_ZA_ACCESS, "SME_ZA_array_off2x2", 2 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (13, 2), AARCH64_FIELD (0, 2)}, "ZA array"},
- {AARCH64_OPND_CLASS_ZA_ACCESS, "SME_ZA_array_off2x4", 4 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (13, 2), AARCH64_FIELD (0, 2)}, "ZA array"},
- {AARCH64_OPND_CLASS_ZA_ACCESS, "SME_ZA_array_off3_0", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (13, 2), AARCH64_FIELD (0, 3)}, "ZA array"},
- {AARCH64_OPND_CLASS_ZA_ACCESS, "SME_ZA_array_off3_5", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (13, 2), AARCH64_FIELD (5, 3)}, "ZA array"},
- {AARCH64_OPND_CLASS_ZA_ACCESS, "SME_ZA_array_off3x2", 2 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (13, 2), AARCH64_FIELD (0, 3)}, "ZA array"},
- {AARCH64_OPND_CLASS_ZA_ACCESS, "SME_ZA_array_off4", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (13, 2), AARCH64_FIELD (0, 4)}, "ZA array"},
- {AARCH64_OPND_CLASS_ADDRESS, "SME_ADDR_RI_U4xVL", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (5, 5), AARCH64_FIELD (0, 4)}, "memory offset"},
- {AARCH64_OPND_CLASS_ADDRESS, "SME_SM_ZA", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (8, 4)}, "streaming mode"},
- {AARCH64_OPND_CLASS_SVE_REG, "SME_PnT_Wm_imm", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (16, 2), AARCH64_FIELD (5, 4), AARCH64_FIELD (23, 1), AARCH64_FIELD (22, 1), AARCH64_FIELD (18, 3)}, "Source scalable predicate register with index "},
- {AARCH64_OPND_CLASS_IMMEDIATE, "SME_SHRIMM3", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (16, 3)}, "a shift-right immediate operand"},
- {AARCH64_OPND_CLASS_IMMEDIATE, "SME_SHRIMM4", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (16, 4)}, "a shift-right immediate operand"},
- {AARCH64_OPND_CLASS_IMMEDIATE, "SME_SHRIMM5", 1 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (22, 2), AARCH64_FIELD (16, 5)}, "a shift-right immediate operand"},
- {AARCH64_OPND_CLASS_SVE_REG, "SME_Zk_INDEX", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (4, 2), AARCH64_FIELD_CONST (1, 1), AARCH64_FIELD (12, 1), AARCH64_FIELD_CONST (1, 1), AARCH64_FIELD (10, 2)}, "an indexed SVE vector register"},
- {AARCH64_OPND_CLASS_SVE_REG, "SME_Zm_INDEX1", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (10, 1), AARCH64_FIELD_CONST (0, 1), AARCH64_FIELD (16, 4)}, "an indexed SVE vector register"},
- {AARCH64_OPND_CLASS_SVE_REG, "SME_Zm_INDEX2", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (10, 2), AARCH64_FIELD_CONST (0, 1), AARCH64_FIELD (16, 4)}, "an indexed SVE vector register"},
- {AARCH64_OPND_CLASS_SVE_REG, "SME_Zm_INDEX2_3", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (10, 1), AARCH64_FIELD (3, 1), AARCH64_FIELD_CONST (0, 1), AARCH64_FIELD (16, 4)}, "an indexed SVE vector register"},
- {AARCH64_OPND_CLASS_SVE_REG, "SME_Zm_INDEX3_1", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (10, 1), AARCH64_FIELD (1, 2), AARCH64_FIELD_CONST (0, 1), AARCH64_FIELD (16, 4)}, "an indexed SVE vector register"},
- {AARCH64_OPND_CLASS_SVE_REG, "SME_Zm_INDEX3_2", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (10, 2), AARCH64_FIELD (2, 1), AARCH64_FIELD_CONST (0, 1), AARCH64_FIELD (16, 4)}, "an indexed SVE vector register"},
- {AARCH64_OPND_CLASS_SVE_REG, "SME_Zm_INDEX3_3", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (10, 2), AARCH64_FIELD (3, 1), AARCH64_FIELD_CONST (0, 1), AARCH64_FIELD (16, 4)}, "an indexed SVE vector register"},
- {AARCH64_OPND_CLASS_SVE_REG, "SME_Zm_INDEX3_10", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (15, 1), AARCH64_FIELD (10, 2), AARCH64_FIELD_CONST (0, 1), AARCH64_FIELD (16, 4)}, "an indexed SVE vector register"},
- {AARCH64_OPND_CLASS_SVE_REG, "SME_Zm_INDEX4_1", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (10, 2), AARCH64_FIELD (1, 2), AARCH64_FIELD_CONST (0, 1), AARCH64_FIELD (16, 4)}, "an indexed SVE vector register"},
- {AARCH64_OPND_CLASS_SVE_REG, "SME_Zm_INDEX4_2", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (10, 2), AARCH64_FIELD (2, 2), AARCH64_FIELD_CONST (0, 1), AARCH64_FIELD (16, 4)}, "an indexed SVE vector register"},
- {AARCH64_OPND_CLASS_SVE_REG, "SME_Zm_INDEX4_3", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (15, 1), AARCH64_FIELD (10, 2), AARCH64_FIELD (3, 1), AARCH64_FIELD_CONST (0, 1), AARCH64_FIELD (16, 4)}, "an indexed SVE vector register"},
- {AARCH64_OPND_CLASS_SVE_REG, "SME_Zm_INDEX4_10", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (15, 1), AARCH64_FIELD (10, 3), AARCH64_FIELD_CONST (0, 1), AARCH64_FIELD (16, 4)}, "an indexed SVE vector register"},
- {AARCH64_OPND_CLASS_SVE_REG, "SME_Zn_INDEX1_16", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (16, 1), AARCH64_FIELD (5, 5)}, "an indexed SVE vector register"},
- {AARCH64_OPND_CLASS_SVE_REG, "SME_Zn_INDEX2_15", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (15, 2), AARCH64_FIELD (5, 5)}, "an indexed SVE vector register"},
- {AARCH64_OPND_CLASS_SVE_REG, "SME_Zn_INDEX2_16", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (16, 2), AARCH64_FIELD (5, 5)}, "an indexed SVE vector register"},
- {AARCH64_OPND_CLASS_SVE_REG, "SME_Zn_INDEX2_19", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (19, 2), AARCH64_FIELD (5, 5)}, "an indexed SVE vector register"},
- {AARCH64_OPND_CLASS_SVE_REG, "SME_Zn_INDEX3_14", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (14, 3), AARCH64_FIELD (5, 5)}, "an indexed SVE vector register"},
- {AARCH64_OPND_CLASS_SVE_REG, "SME_Zn_INDEX3_15", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (15, 3), AARCH64_FIELD (5, 5)}, "an indexed SVE vector register"},
- {AARCH64_OPND_CLASS_SVE_REG, "SME_Zn_INDEX4_14", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (14, 4), AARCH64_FIELD (5, 5)}, "an indexed SVE vector register"},
- {AARCH64_OPND_CLASS_SVE_REG, "SVE_Zn0_INDEX", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (5, 5)}, "an SVE vector register with option zero index"},
- {AARCH64_OPND_CLASS_SVE_REG, "SVE_Zn1_17_INDEX", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (17, 1), AARCH64_FIELD (5, 5)}, "an SVE vector register with optional one bit index"},
- {AARCH64_OPND_CLASS_SVE_REG, "SVE_Zn2_18_INDEX", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (17, 2), AARCH64_FIELD (5, 5)}, "an SVE vector register with optional two bit index"},
- {AARCH64_OPND_CLASS_SVE_REG, "SVE_Zn3_22_INDEX", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (22, 1), AARCH64_FIELD (17, 2), AARCH64_FIELD (5, 5)}, "an SVE vector register with optional three bit index"},
- {AARCH64_OPND_CLASS_SVE_REG, "SVE_Zd0_INDEX", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (0, 5)}, "an SVE vector register with option zero index"},
- {AARCH64_OPND_CLASS_SVE_REG, "SVE_Zd1_17_INDEX", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (17, 1), AARCH64_FIELD (0, 5)}, "an SVE vector register with optional one bit index"},
- {AARCH64_OPND_CLASS_SVE_REG, "SVE_Zd2_18_INDEX", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (17, 2), AARCH64_FIELD (0, 5)}, "an SVE vector register with optional two bit index"},
- {AARCH64_OPND_CLASS_SVE_REG, "SVE_Zd3_22_INDEX", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (22, 1), AARCH64_FIELD (17, 2), AARCH64_FIELD (0, 5)}, "an SVE vector register with optional three bit index"},
- {AARCH64_OPND_CLASS_IMMEDIATE, "SME_VLxN_10", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (10, 1)}, "VLx2 or VLx4"},
- {AARCH64_OPND_CLASS_IMMEDIATE, "SME_VLxN_13", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (13, 1)}, "VLx2 or VLx4"},
+ {AARCH64_OPND_CLASS_SYSTEM, "BRBOP", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {{1, 5, false}}, "Branch Record Buffer operation operand"},
+ {AARCH64_OPND_CLASS_INT_REG, "Rt_IN_SYS_ALIASES", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {{5, 0, false}}, "Rt register with defaults for SYS aliases"},
+ {AARCH64_OPND_CLASS_INT_REG, "LSE128_Rt", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {{5, 0, false}}, "an integer register"},
+ {AARCH64_OPND_CLASS_INT_REG, "LSE128_Rt2", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {{5, 16, false}}, "an integer register"},
+ {AARCH64_OPND_CLASS_ADDRESS, "SVE_ADDR_RI_S4x16", 4 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {{5, 5, false}}, "an address with a 4-bit signed offset, multiplied by 16"},
+ {AARCH64_OPND_CLASS_ADDRESS, "SVE_ADDR_RI_S4x32", 5 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {{5, 5, false}}, "an address with a 4-bit signed offset, multiplied by 32"},
+ {AARCH64_OPND_CLASS_ADDRESS, "SVE_ADDR_RI_S4xVL", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {{5, 5, false}}, "an address with a 4-bit signed offset, multiplied by VL"},
+ {AARCH64_OPND_CLASS_ADDRESS, "SVE_ADDR_RI_S4x2xVL", 1 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {{5, 5, false}}, "an address with a 4-bit signed offset, multiplied by 2*VL"},
+ {AARCH64_OPND_CLASS_ADDRESS, "SVE_ADDR_RI_S4x3xVL", 2 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {{5, 5, false}}, "an address with a 4-bit signed offset, multiplied by 3*VL"},
+ {AARCH64_OPND_CLASS_ADDRESS, "SVE_ADDR_RI_S4x4xVL", 3 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {{5, 5, false}}, "an address with a 4-bit signed offset, multiplied by 4*VL"},
+ {AARCH64_OPND_CLASS_ADDRESS, "SVE_ADDR_RI_S6xVL", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {{5, 5, false}}, "an address with a 6-bit signed offset, multiplied by VL"},
+ {AARCH64_OPND_CLASS_ADDRESS, "SVE_ADDR_RI_S9xVL", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {{5, 5, false}}, "an address with a 9-bit signed offset, multiplied by VL"},
+ {AARCH64_OPND_CLASS_ADDRESS, "SVE_ADDR_RI_U6", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {{5, 5, false}}, "an address with a 6-bit unsigned offset"},
+ {AARCH64_OPND_CLASS_ADDRESS, "SVE_ADDR_RI_U6x2", 1 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {{5, 5, false}}, "an address with a 6-bit unsigned offset, multiplied by 2"},
+ {AARCH64_OPND_CLASS_ADDRESS, "SVE_ADDR_RI_U6x4", 2 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {{5, 5, false}}, "an address with a 6-bit unsigned offset, multiplied by 4"},
+ {AARCH64_OPND_CLASS_ADDRESS, "SVE_ADDR_RI_U6x8", 3 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {{5, 5, false}}, "an address with a 6-bit unsigned offset, multiplied by 8"},
+ {AARCH64_OPND_CLASS_ADDRESS, "SVE_ADDR_RR", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {{5, 5, false}, {5, 16, false}}, "an address with a scalar register offset"},
+ {AARCH64_OPND_CLASS_ADDRESS, "SVE_ADDR_RR_LSL1", 1 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {{5, 5, false}, {5, 16, false}}, "an address with a scalar register offset"},
+ {AARCH64_OPND_CLASS_ADDRESS, "SVE_ADDR_RR_LSL2", 2 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {{5, 5, false}, {5, 16, false}}, "an address with a scalar register offset"},
+ {AARCH64_OPND_CLASS_ADDRESS, "SVE_ADDR_RR_LSL3", 3 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {{5, 5, false}, {5, 16, false}}, "an address with a scalar register offset"},
+ {AARCH64_OPND_CLASS_ADDRESS, "SVE_ADDR_RR_LSL4", 4 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {{5, 5, false}, {5, 16, false}}, "an address with a scalar register offset"},
+ {AARCH64_OPND_CLASS_ADDRESS, "SVE_ADDR_RM", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {{5, 5, false}, {5, 16, false}}, "an address with a scalar register offset"},
+ {AARCH64_OPND_CLASS_ADDRESS, "SVE_ADDR_RM_LSL1", 1 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {{5, 5, false}, {5, 16, false}}, "an address with a scalar register offset"},
+ {AARCH64_OPND_CLASS_ADDRESS, "SVE_ADDR_RM_LSL2", 2 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {{5, 5, false}, {5, 16, false}}, "an address with a scalar register offset"},
+ {AARCH64_OPND_CLASS_ADDRESS, "SVE_ADDR_RM_LSL3", 3 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {{5, 5, false}, {5, 16, false}}, "an address with a scalar register offset"},
+ {AARCH64_OPND_CLASS_ADDRESS, "SVE_ADDR_RM_LSL4", 4 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {{5, 5, false}, {5, 16, false}}, "an address with a scalar register offset"},
+ {AARCH64_OPND_CLASS_ADDRESS, "SVE_ADDR_RX", (0 << OPD_F_OD_LSB) | OPD_F_NO_ZR | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {{5, 5, false}, {5, 16, false}}, "an address with a scalar register offset"},
+ {AARCH64_OPND_CLASS_ADDRESS, "SVE_ADDR_RX_LSL1", (1 << OPD_F_OD_LSB) | OPD_F_NO_ZR | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {{5, 5, false}, {5, 16, false}}, "an address with a scalar register offset"},
+ {AARCH64_OPND_CLASS_ADDRESS, "SVE_ADDR_RX_LSL2", (2 << OPD_F_OD_LSB) | OPD_F_NO_ZR | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {{5, 5, false}, {5, 16, false}}, "an address with a scalar register offset"},
+ {AARCH64_OPND_CLASS_ADDRESS, "SVE_ADDR_RX_LSL3", (3 << OPD_F_OD_LSB) | OPD_F_NO_ZR | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {{5, 5, false}, {5, 16, false}}, "an address with a scalar register offset"},
+ {AARCH64_OPND_CLASS_ADDRESS, "SVE_ADDR_RX_LSL4", (4 << OPD_F_OD_LSB) | OPD_F_NO_ZR | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {{5, 5, false}, {5, 16, false}}, "an address with a scalar register offset"},
+ {AARCH64_OPND_CLASS_ADDRESS, "SVE_ADDR_ZX", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {{5, 5, false}, {5, 16, false}}, "vector of address with a scalar register offset"},
+ {AARCH64_OPND_CLASS_ADDRESS, "SVE_ADDR_RZ", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {{5, 5, false}, {5, 16, false}}, "an address with a vector register offset"},
+ {AARCH64_OPND_CLASS_ADDRESS, "SVE_ADDR_RZ_LSL1", 1 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {{5, 5, false}, {5, 16, false}}, "an address with a vector register offset"},
+ {AARCH64_OPND_CLASS_ADDRESS, "SVE_ADDR_RZ_LSL2", 2 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {{5, 5, false}, {5, 16, false}}, "an address with a vector register offset"},
+ {AARCH64_OPND_CLASS_ADDRESS, "SVE_ADDR_RZ_LSL3", 3 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {{5, 5, false}, {5, 16, false}}, "an address with a vector register offset"},
+ {AARCH64_OPND_CLASS_ADDRESS, "SVE_ADDR_RZ_XTW_14", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {{5, 5, false}, {5, 16, false}, {1, 14, false}}, "an address with a vector register offset"},
+ {AARCH64_OPND_CLASS_ADDRESS, "SVE_ADDR_RZ_XTW_22", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {{5, 5, false}, {5, 16, false}, {1, 22, false}}, "an address with a vector register offset"},
+ {AARCH64_OPND_CLASS_ADDRESS, "SVE_ADDR_RZ_XTW1_14", 1 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {{5, 5, false}, {5, 16, false}, {1, 14, false}}, "an address with a vector register offset"},
+ {AARCH64_OPND_CLASS_ADDRESS, "SVE_ADDR_RZ_XTW1_22", 1 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {{5, 5, false}, {5, 16, false}, {1, 22, false}}, "an address with a vector register offset"},
+ {AARCH64_OPND_CLASS_ADDRESS, "SVE_ADDR_RZ_XTW2_14", 2 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {{5, 5, false}, {5, 16, false}, {1, 14, false}}, "an address with a vector register offset"},
+ {AARCH64_OPND_CLASS_ADDRESS, "SVE_ADDR_RZ_XTW2_22", 2 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {{5, 5, false}, {5, 16, false}, {1, 22, false}}, "an address with a vector register offset"},
+ {AARCH64_OPND_CLASS_ADDRESS, "SVE_ADDR_RZ_XTW3_14", 3 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {{5, 5, false}, {5, 16, false}, {1, 14, false}}, "an address with a vector register offset"},
+ {AARCH64_OPND_CLASS_ADDRESS, "SVE_ADDR_RZ_XTW3_22", 3 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {{5, 5, false}, {5, 16, false}, {1, 22, false}}, "an address with a vector register offset"},
+ {AARCH64_OPND_CLASS_ADDRESS, "SVE_ADDR_ZI_U5", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {{5, 5, false}}, "an address with a 5-bit unsigned offset"},
+ {AARCH64_OPND_CLASS_ADDRESS, "SVE_ADDR_ZI_U5x2", 1 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {{5, 5, false}}, "an address with a 5-bit unsigned offset, multiplied by 2"},
+ {AARCH64_OPND_CLASS_ADDRESS, "SVE_ADDR_ZI_U5x4", 2 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {{5, 5, false}}, "an address with a 5-bit unsigned offset, multiplied by 4"},
+ {AARCH64_OPND_CLASS_ADDRESS, "SVE_ADDR_ZI_U5x8", 3 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {{5, 5, false}}, "an address with a 5-bit unsigned offset, multiplied by 8"},
+ {AARCH64_OPND_CLASS_ADDRESS, "SVE_ADDR_ZZ_LSL", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {{5, 5, false}, {5, 16, false}}, "an address with a vector register offset"},
+ {AARCH64_OPND_CLASS_ADDRESS, "SVE_ADDR_ZZ_SXTW", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {{5, 5, false}, {5, 16, false}}, "an address with a vector register offset"},
+ {AARCH64_OPND_CLASS_ADDRESS, "SVE_ADDR_ZZ_UXTW", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {{5, 5, false}, {5, 16, false}}, "an address with a vector register offset"},
+ {AARCH64_OPND_CLASS_IMMEDIATE, "SVE_AIMM", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {{9, 5, false}}, "a 9-bit unsigned arithmetic operand"},
+ {AARCH64_OPND_CLASS_IMMEDIATE, "SVE_ASIMM", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {{9, 5, false}}, "a 9-bit signed arithmetic operand"},
+ {AARCH64_OPND_CLASS_IMMEDIATE, "SVE_FPIMM8", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {{8, 5, false}}, "an 8-bit floating-point immediate"},
+ {AARCH64_OPND_CLASS_IMMEDIATE, "SVE_I1_HALF_ONE", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {{1, 5, false}}, "either 0.5 or 1.0"},
+ {AARCH64_OPND_CLASS_IMMEDIATE, "SVE_I1_HALF_TWO", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {{1, 5, false}}, "either 0.5 or 2.0"},
+ {AARCH64_OPND_CLASS_IMMEDIATE, "SVE_I1_ZERO_ONE", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {{1, 5, false}}, "either 0.0 or 1.0"},
+ {AARCH64_OPND_CLASS_IMMEDIATE, "SVE_IMM_ROT1", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {{1, 16, false}}, "a 1-bit rotation specifier for complex arithmetic operations"},
+ {AARCH64_OPND_CLASS_IMMEDIATE, "SVE_IMM_ROT2", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {{2, 10, false}}, "a 2-bit rotation specifier for complex arithmetic operations"},
+ {AARCH64_OPND_CLASS_IMMEDIATE, "SVE_IMM_ROT3", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {{1, 10, false}}, "a 1-bit rotation specifier for complex arithmetic operations"},
+ {AARCH64_OPND_CLASS_IMMEDIATE, "SVE_INV_LIMM", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {{1, 17, false}, {6, 11, false}, {6, 5, false}}, "an inverted 13-bit logical immediate"},
+ {AARCH64_OPND_CLASS_IMMEDIATE, "SVE_LIMM", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {{1, 17, false}, {6, 11, false}, {6, 5, false}}, "a 13-bit logical immediate"},
+ {AARCH64_OPND_CLASS_IMMEDIATE, "SVE_LIMM_MOV", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {{1, 17, false}, {6, 11, false}, {6, 5, false}}, "a 13-bit logical move immediate"},
+ {AARCH64_OPND_CLASS_IMMEDIATE, "SVE_PATTERN", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {{5, 5, false}}, "an enumeration value such as POW2"},
+ {AARCH64_OPND_CLASS_IMMEDIATE, "SVE_PATTERN_SCALED", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {{5, 5, false}}, "an enumeration value such as POW2"},
+ {AARCH64_OPND_CLASS_IMMEDIATE, "SVE_PRFOP", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {{4, 0, false}}, "an enumeration value such as PLDL1KEEP"},
+ {AARCH64_OPND_CLASS_PRED_REG, "SVE_Pd", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {{4, 0, false}}, "an SVE predicate register"},
+ {AARCH64_OPND_CLASS_PRED_REG, "SVE_PNd", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {{4, 0, false}}, "an SVE predicate-as-counter register"},
+ {AARCH64_OPND_CLASS_PRED_REG, "SVE_Pg3", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {{3, 10, false}}, "an SVE predicate register"},
+ {AARCH64_OPND_CLASS_PRED_REG, "SVE_Pg4_5", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {{4, 5, false}}, "an SVE predicate register"},
+ {AARCH64_OPND_CLASS_PRED_REG, "SVE_Pg4_10", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {{4, 10, false}}, "an SVE predicate register"},
+ {AARCH64_OPND_CLASS_PRED_REG, "SVE_PNg4_10", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {{4, 10, false}}, "an SVE predicate-as-counter register"},
+ {AARCH64_OPND_CLASS_PRED_REG, "SVE_Pg4_16", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {{4, 16, false}}, "an SVE predicate register"},
+ {AARCH64_OPND_CLASS_PRED_REG, "SVE_Pm", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {{4, 16, false}}, "an SVE predicate register"},
+ {AARCH64_OPND_CLASS_PRED_REG, "SVE_Pn", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {{4, 5, false}}, "an SVE predicate register"},
+ {AARCH64_OPND_CLASS_PRED_REG, "SVE_PNn", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {{4, 5, false}}, "an SVE predicate register"},
+ {AARCH64_OPND_CLASS_PRED_REG, "SVE_Pt", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {{4, 0, false}}, "an SVE predicate register"},
+ {AARCH64_OPND_CLASS_PRED_REG, "SVE_PNt", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {{4, 0, false}}, "an SVE predicate register"},
+ {AARCH64_OPND_CLASS_INT_REG, "SVE_Rm", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {{5, 5, false}}, "an integer register or zero"},
+ {AARCH64_OPND_CLASS_INT_REG, "SVE_Rn_SP", OPD_F_MAYBE_SP | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {{5, 16, false}}, "an integer register or SP"},
+ {AARCH64_OPND_CLASS_IMMEDIATE, "SVE_SHLIMM_PRED", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {{2, 22, false}, {5, 5, false}}, "a shift-left immediate operand"},
+ {AARCH64_OPND_CLASS_IMMEDIATE, "SVE_SHLIMM_UNPRED", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {{2, 22, false}, {5, 16, false}}, "a shift-left immediate operand"},
+ {AARCH64_OPND_CLASS_IMMEDIATE, "SVE_SHLIMM_UNPRED_22", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {{1, 22, false}, {2, 19, false}, {3, 16, false}}, "a shift-left immediate operand"},
+ {AARCH64_OPND_CLASS_IMMEDIATE, "SVE_SHRIMM_PRED", 1 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {{2, 22, false}, {5, 5, false}}, "a shift-right immediate operand"},
+ {AARCH64_OPND_CLASS_IMMEDIATE, "SVE_SHRIMM_UNPRED", 1 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {{2, 22, false}, {5, 16, false}}, "a shift-right immediate operand"},
+ {AARCH64_OPND_CLASS_IMMEDIATE, "SVE_SHRIMM_UNPRED_22", 2 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {{1, 22, false}, {2, 19, false}, {3, 16, false}}, "a shift-right immediate operand"},
+ {AARCH64_OPND_CLASS_IMMEDIATE, "SVE_SIMM5", OPD_F_SEXT | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {{5, 5, false}}, "a 5-bit signed immediate"},
+ {AARCH64_OPND_CLASS_IMMEDIATE, "SVE_SIMM5B", OPD_F_SEXT | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {{5, 16, false}}, "a 5-bit signed immediate"},
+ {AARCH64_OPND_CLASS_IMMEDIATE, "SVE_SIMM6", OPD_F_SEXT | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {{6, 5, false}}, "a 6-bit signed immediate"},
+ {AARCH64_OPND_CLASS_IMMEDIATE, "SVE_SIMM8", OPD_F_SEXT | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {{8, 5, false}}, "an 8-bit signed immediate"},
+ {AARCH64_OPND_CLASS_IMMEDIATE, "SVE_UIMM3", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {{3, 16, false}}, "a 3-bit unsigned immediate"},
+ {AARCH64_OPND_CLASS_IMMEDIATE, "SVE_UIMM7", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {{7, 14, false}}, "a 7-bit unsigned immediate"},
+ {AARCH64_OPND_CLASS_IMMEDIATE, "SVE_UIMM8", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {{8, 5, false}}, "an 8-bit unsigned immediate"},
+ {AARCH64_OPND_CLASS_IMMEDIATE, "SVE_UIMM8_53", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {{5, 16, false}, {3, 10, false}}, "an 8-bit unsigned immediate"},
+ {AARCH64_OPND_CLASS_IMMEDIATE, "SVE_UIMM4", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {{4, 16, false}}, "a 4-bit unsigned immediate"},
+ {AARCH64_OPND_CLASS_SIMD_REG, "SVE_VZn", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {{5, 5, false}}, "a SIMD register"},
+ {AARCH64_OPND_CLASS_SIMD_REG, "SVE_Vd", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {{5, 0, false}}, "a SIMD register"},
+ {AARCH64_OPND_CLASS_SIMD_REG, "SVE_Vm", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {{5, 5, false}}, "a SIMD register"},
+ {AARCH64_OPND_CLASS_SIMD_REG, "SVE_Vn", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {{5, 5, false}}, "a SIMD register"},
+ {AARCH64_OPND_CLASS_ZA_ACCESS, "SME_ZA_array_vrsb_1", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {{1, 15, false}, {2, 13, false}, {3, 5, false}}, "ZA0 tile"},
+ {AARCH64_OPND_CLASS_ZA_ACCESS, "SME_ZA_array_vrsh_1", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {{1, 15, false}, {2, 13, false}, {1, 7, false}, {2, 5, false}}, "1 bit ZA tile"},
+ {AARCH64_OPND_CLASS_ZA_ACCESS, "SME_ZA_array_vrss_1", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {{1, 15, false}, {2, 13, false}, {2, 6, false}, {1, 5, false}}, "2 ZA tile"},
+ {AARCH64_OPND_CLASS_ZA_ACCESS, "SME_ZA_array_vrsd_1", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {{1, 15, false}, {2, 13, false}, {3, 5, false}}, "3 ZA tile"},
+ {AARCH64_OPND_CLASS_ZA_ACCESS, "SME_ZA_array_vrsb_2", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {{1, 15, false}, {2, 13, false}, {2, 5, false}}, "ZA0 tile"},
+ {AARCH64_OPND_CLASS_ZA_ACCESS, "SME_ZA_array_vrsh_2", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {{1, 15, false}, {2, 13, false}, {1, 6, false}, {1, 5, false}}, "1 bit ZA tile"},
+ {AARCH64_OPND_CLASS_ZA_ACCESS, "SME_ZA_array_vrss_2", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {{1, 15, false}, {2, 13, false}, {2, 5, false}}, "2 bit ZA tile"},
+ {AARCH64_OPND_CLASS_ZA_ACCESS, "SME_ZA_array_vrsd_2", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {{1, 15, false}, {2, 13, false}, {3, 5, false}}, "3 bit ZA tile"},
+ {AARCH64_OPND_CLASS_ZA_ACCESS, "SME_ZA_ARRAY4", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {{1, 15, false}, {2, 13, false}}, "ZA tile to vector register"},
+ {AARCH64_OPND_CLASS_SVE_REG, "SVE_Za_5", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {{5, 5, false}}, "an SVE vector register"},
+ {AARCH64_OPND_CLASS_SVE_REG, "SVE_Za_16", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {{5, 16, false}}, "an SVE vector register"},
+ {AARCH64_OPND_CLASS_SVE_REG, "SVE_Zd", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {{5, 0, false}}, "an SVE vector register"},
+ {AARCH64_OPND_CLASS_SVE_REG, "SVE_Zm_5", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {{5, 5, false}}, "an SVE vector register"},
+ {AARCH64_OPND_CLASS_SVE_REG, "SVE_Zm_16", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {{5, 16, false}}, "an SVE vector register"},
+ {AARCH64_OPND_CLASS_SVE_REG, "SVE_Zm1_23_INDEX", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {{1, 23, false}, {5, 16, false}}, "an indexed SVE vector register"},
+ {AARCH64_OPND_CLASS_SVE_REG, "SVE_Zm2_22_INDEX", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {{2, 22, false}, {5, 16, false}}, "an indexed SVE vector register"},
+ {AARCH64_OPND_CLASS_SVE_REG, "SVE_Zm3_INDEX", 3 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {{5, 16, false}}, "an indexed SVE vector register"},
+ {AARCH64_OPND_CLASS_SVE_REG, "SVE_Zm3_11_INDEX", 3 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {{2, 19, false}, {1, 11, false}, {3, 16, false}}, "an indexed SVE vector register"},
+ {AARCH64_OPND_CLASS_SVE_REG, "SVE_Zm3_12_INDEX", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {{2, 22, false}, {1, 12, false}, {5, 16, false}}, "an indexed SVE vector register"},
+ {AARCH64_OPND_CLASS_SVE_REG, "SVE_Zm3_19_INDEX", 3 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {{2, 19, false}, {3, 16, false}}, "an indexed SVE vector register"},
+ {AARCH64_OPND_CLASS_SVE_REG, "SVE_Zm3_22_INDEX", 3 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {{1, 22, false}, {5, 16, false}}, "an indexed SVE vector register"},
+ {AARCH64_OPND_CLASS_SVE_REG, "SVE_Zm3_10_INDEX", 3 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {{2, 19, false}, {2, 10, false}, {3, 16, false}}, "an indexed SVE vector register"},
+ {AARCH64_OPND_CLASS_SVE_REG, "SVE_Zm4_11_INDEX", 4 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {{1, 20, false}, {1, 11, false}, {4, 16, false}}, "an indexed SVE vector register"},
+ {AARCH64_OPND_CLASS_SVE_REG, "SVE_Zm4_INDEX", 4 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {{5, 16, false}}, "an indexed SVE vector register"},
+ {AARCH64_OPND_CLASS_SVE_REG, "SVE_Zn", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {{5, 5, false}}, "an SVE vector register"},
+ {AARCH64_OPND_CLASS_SVE_REG, "SVE_Zn_INDEX", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {{5, 5, false}, {2, 22, false}, {5, 16, false}}, "an indexed SVE vector register"},
+ {AARCH64_OPND_CLASS_SVE_REG, "SVE_Zn_5_INDEX", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {{5, 5, false}, {5, 16, false}}, "a 5 bit indexed SVE vector register"},
+ {AARCH64_OPND_CLASS_SVE_REGLIST, "SVE_ZnxN", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {{5, 5, false}}, "a list of SVE vector registers"},
+ {AARCH64_OPND_CLASS_SVE_REG, "SVE_Zt", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {{5, 0, false}}, "an SVE vector register"},
+ {AARCH64_OPND_CLASS_SVE_REGLIST, "SVE_ZtxN", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {{5, 0, false}}, "a list of SVE vector registers"},
+ {AARCH64_OPND_CLASS_SVE_REGLIST, "SME_Zdnx2", 2 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {{4, 1, false}, {1, 0, true}}, "a list of SVE vector registers"},
+ {AARCH64_OPND_CLASS_SVE_REGLIST, "SME_Zdnx4", 4 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {{3, 2, false}, {2, 0, true}}, "a list of SVE vector registers"},
+ {AARCH64_OPND_CLASS_SVE_REG, "SME_Zm", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {{4, 16, false}}, "an SVE vector register"},
+ {AARCH64_OPND_CLASS_SVE_REG, "SME_Zm_17", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {{4, 17, false}}, "an SVE vector register"},
+ {AARCH64_OPND_CLASS_SVE_REG, "SME_Zn_6_3", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {{1, 0, true}, {3, 6, false}, {1, 0, true}}, "an SVE vector register"},
+ {AARCH64_OPND_CLASS_SVE_REG, "SME_Zm_17_3", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {{1, 1, true}, {3, 17, false}, {1, 0, true}}, "an SVE vector register"},
+ {AARCH64_OPND_CLASS_SVE_REGLIST, "SME_Znx2_6_3", 2 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {{1, 0, true}, {3, 6, false}, {1, 0, true}}, "a list of SVE vector registers"},
+ {AARCH64_OPND_CLASS_SVE_REGLIST, "SME_Zmx2_17_3", 2 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {{1, 1, true}, {3, 17, false}, {1, 0, true}}, "a list of SVE vector registers"},
+ {AARCH64_OPND_CLASS_SVE_REGLIST, "SME_Zmx2_INDEX_22", 2 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {{5, 16, false}, {1, 22, false}}, "a list of SVE vector registers with index"},
+ {AARCH64_OPND_CLASS_SVE_REGLIST, "SME_Zmx2", 2 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {{4, 17, false}, {1, 0, true}}, "a list of SVE vector registers"},
+ {AARCH64_OPND_CLASS_SVE_REGLIST, "SME_Zmx4", 4 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {{3, 18, false}, {2, 0, true}}, "a list of SVE vector registers"},
+ {AARCH64_OPND_CLASS_SVE_REGLIST, "SME_Znx2", 2 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {{4, 6, false}, {1, 0, true}}, "a list of SVE vector registers"},
+ {AARCH64_OPND_CLASS_SVE_REGLIST, "SME_Znx2_BIT_INDEX", 2 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {{4, 6, false}, {1, 0, true}}, "a list of SVE vector registers"},
+ {AARCH64_OPND_CLASS_SVE_REGLIST, "SME_Znx4", 4 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {{3, 7, false}, {2, 0, true}}, "a list of SVE vector registers"},
+ {AARCH64_OPND_CLASS_SVE_REGLIST, "SME_Zn7xN_UNTYPED", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {{3, 7, false}}, "a list of untyped SVE vector registers"},
+ {AARCH64_OPND_CLASS_SVE_REGLIST, "SME_Ztx2_STRIDED", 2 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {{1, 4, false}, {3, 0, false}}, "a list of SVE vector registers"},
+ {AARCH64_OPND_CLASS_SVE_REGLIST, "SME_Ztx4_STRIDED", 4 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {{1, 4, false}, {2, 0, false}}, "a list of SVE vector registers"},
+ {AARCH64_OPND_CLASS_SVE_REG, "SME_ZAda_1b", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {{1, 0, false}}, "an SME ZA tile ZA0-ZA1"},
+ {AARCH64_OPND_CLASS_SVE_REG, "SME_ZAda_2b", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {{2, 0, false}}, "an SME ZA tile ZA0-ZA3"},
+ {AARCH64_OPND_CLASS_SVE_REG, "SME_ZAda_3b", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {{3, 0, false}}, "an SME ZA tile ZA0-ZA7"},
+ {AARCH64_OPND_CLASS_ZA_ACCESS, "SME_ZA_HV_idx_src", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {{2, 22, false}, {1, 16, false}, {1, 15, false}, {2, 13, false}, {4, 5, false}}, "an SME horizontal or vertical vector access register"},
+ {AARCH64_OPND_CLASS_ZA_ACCESS, "SME_ZA_HV_idx_srcxN", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {{1, 15, false}, {2, 13, false}, {3, 5, false}}, "an SME horizontal or vertical vector access register"},
+ {AARCH64_OPND_CLASS_ZA_ACCESS, "SME_ZA_HV_idx_dest", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {{2, 22, false}, {1, 16, false}, {1, 15, false}, {2, 13, false}, {4, 0, false}}, "an SME horizontal or vertical vector access register"},
+ {AARCH64_OPND_CLASS_ZA_ACCESS, "SME_ZA_HV_idx_destxN", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {{1, 15, false}, {2, 13, false}, {3, 0, false}}, "an SME horizontal or vertical vector access register"},
+ {AARCH64_OPND_CLASS_SVE_REGLIST, "SME_Pdx2", 2 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {{3, 1, false}, {1, 0, true}}, "a list of SVE predicate registers"},
+ {AARCH64_OPND_CLASS_SVE_REGLIST, "SME_PdxN", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {{4, 0, false}}, "a list of SVE predicate registers"},
+ {AARCH64_OPND_CLASS_PRED_REG, "SME_Pm", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {{3, 13, false}}, "an SVE predicate register"},
+ {AARCH64_OPND_CLASS_PRED_REG, "SME_PNd3", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {{1, 1, true}, {3, 0, false}}, "an SVE predicate-as-counter register"},
+ {AARCH64_OPND_CLASS_PRED_REG, "SME_PNg3", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {{1, 1, true}, {3, 10, false}}, "an SVE predicate-as-counter register"},
+ {AARCH64_OPND_CLASS_PRED_REG, "SME_PNn", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {{4, 5, false}}, "an SVE predicate-as-counter register"},
+ {AARCH64_OPND_CLASS_SVE_REG, "SME_PNn3_INDEX1", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {{1, 8, false}, {2, 1, true}, {3, 5, false}}, "an indexed SVE predicate-as-counter register"},
+ {AARCH64_OPND_CLASS_SVE_REG, "SME_PNn3_INDEX2", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {{2, 8, false}, {2, 1, true}, {3, 5, false}}, "an indexed SVE predicate-as-counter register"},
+ {AARCH64_OPND_CLASS_SVE_REG, "SME_list_of_64bit_tiles", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {{8, 0, false}}, "a list of 64-bit ZA element tiles"},
+ {AARCH64_OPND_CLASS_ZA_ACCESS, "SME_ZA_HV_idx_ldstr", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {{2, 22, false}, {1, 24, false}, {1, 15, false}, {2, 13, false}, {4, 0, false}}, "an SME horizontal or vertical vector access register"},
+ {AARCH64_OPND_CLASS_ZA_ACCESS, "SME_ZA_array_off1x4", 4 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {{2, 13, false}, {1, 0, false}}, "ZA array"},
+ {AARCH64_OPND_CLASS_ZA_ACCESS, "SME_ZA_array_off2x2", 2 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {{2, 13, false}, {2, 0, false}}, "ZA array"},
+ {AARCH64_OPND_CLASS_ZA_ACCESS, "SME_ZA_array_off2x4", 4 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {{2, 13, false}, {2, 0, false}}, "ZA array"},
+ {AARCH64_OPND_CLASS_ZA_ACCESS, "SME_ZA_array_off3_0", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {{2, 13, false}, {3, 0, false}}, "ZA array"},
+ {AARCH64_OPND_CLASS_ZA_ACCESS, "SME_ZA_array_off3_5", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {{2, 13, false}, {3, 5, false}}, "ZA array"},
+ {AARCH64_OPND_CLASS_ZA_ACCESS, "SME_ZA_array_off3x2", 2 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {{2, 13, false}, {3, 0, false}}, "ZA array"},
+ {AARCH64_OPND_CLASS_ZA_ACCESS, "SME_ZA_array_off4", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {{2, 13, false}, {4, 0, false}}, "ZA array"},
+ {AARCH64_OPND_CLASS_ADDRESS, "SME_ADDR_RI_U4xVL", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {{5, 5, false}, {4, 0, false}}, "memory offset"},
+ {AARCH64_OPND_CLASS_ADDRESS, "SME_SM_ZA", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {{4, 8, false}}, "streaming mode"},
+ {AARCH64_OPND_CLASS_SVE_REG, "SME_PnT_Wm_imm", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {{2, 16, false}, {4, 5, false}, {1, 23, false}, {1, 22, false}, {3, 18, false}}, "Source scalable predicate register with index "},
+ {AARCH64_OPND_CLASS_IMMEDIATE, "SME_SHRIMM3", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {{3, 16, false}}, "a shift-right immediate operand"},
+ {AARCH64_OPND_CLASS_IMMEDIATE, "SME_SHRIMM4", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {{4, 16, false}}, "a shift-right immediate operand"},
+ {AARCH64_OPND_CLASS_IMMEDIATE, "SME_SHRIMM5", 1 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {{2, 22, false}, {5, 16, false}}, "a shift-right immediate operand"},
+ {AARCH64_OPND_CLASS_SVE_REG, "SME_Zk_INDEX", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {{2, 4, false}, {1, 1, true}, {1, 12, false}, {1, 1, true}, {2, 10, false}}, "an indexed SVE vector register"},
+ {AARCH64_OPND_CLASS_SVE_REG, "SME_Zm_INDEX1", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {{1, 10, false}, {1, 0, true}, {4, 16, false}}, "an indexed SVE vector register"},
+ {AARCH64_OPND_CLASS_SVE_REG, "SME_Zm_INDEX2", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {{2, 10, false}, {1, 0, true}, {4, 16, false}}, "an indexed SVE vector register"},
+ {AARCH64_OPND_CLASS_SVE_REG, "SME_Zm_INDEX2_3", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {{1, 10, false}, {1, 3, false}, {1, 0, true}, {4, 16, false}}, "an indexed SVE vector register"},
+ {AARCH64_OPND_CLASS_SVE_REG, "SME_Zm_INDEX3_1", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {{1, 10, false}, {2, 1, false}, {1, 0, true}, {4, 16, false}}, "an indexed SVE vector register"},
+ {AARCH64_OPND_CLASS_SVE_REG, "SME_Zm_INDEX3_2", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {{2, 10, false}, {1, 2, false}, {1, 0, true}, {4, 16, false}}, "an indexed SVE vector register"},
+ {AARCH64_OPND_CLASS_SVE_REG, "SME_Zm_INDEX3_3", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {{2, 10, false}, {1, 3, false}, {1, 0, true}, {4, 16, false}}, "an indexed SVE vector register"},
+ {AARCH64_OPND_CLASS_SVE_REG, "SME_Zm_INDEX3_10", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {{1, 15, false}, {2, 10, false}, {1, 0, true}, {4, 16, false}}, "an indexed SVE vector register"},
+ {AARCH64_OPND_CLASS_SVE_REG, "SME_Zm_INDEX4_1", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {{2, 10, false}, {2, 1, false}, {1, 0, true}, {4, 16, false}}, "an indexed SVE vector register"},
+ {AARCH64_OPND_CLASS_SVE_REG, "SME_Zm_INDEX4_2", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {{2, 10, false}, {2, 2, false}, {1, 0, true}, {4, 16, false}}, "an indexed SVE vector register"},
+ {AARCH64_OPND_CLASS_SVE_REG, "SME_Zm_INDEX4_3", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {{1, 15, false}, {2, 10, false}, {1, 3, false}, {1, 0, true}, {4, 16, false}}, "an indexed SVE vector register"},
+ {AARCH64_OPND_CLASS_SVE_REG, "SME_Zm_INDEX4_10", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {{1, 15, false}, {3, 10, false}, {1, 0, true}, {4, 16, false}}, "an indexed SVE vector register"},
+ {AARCH64_OPND_CLASS_SVE_REG, "SME_Zn_INDEX1_16", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {{1, 16, false}, {5, 5, false}}, "an indexed SVE vector register"},
+ {AARCH64_OPND_CLASS_SVE_REG, "SME_Zn_INDEX2_15", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {{2, 15, false}, {5, 5, false}}, "an indexed SVE vector register"},
+ {AARCH64_OPND_CLASS_SVE_REG, "SME_Zn_INDEX2_16", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {{2, 16, false}, {5, 5, false}}, "an indexed SVE vector register"},
+ {AARCH64_OPND_CLASS_SVE_REG, "SME_Zn_INDEX2_19", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {{2, 19, false}, {5, 5, false}}, "an indexed SVE vector register"},
+ {AARCH64_OPND_CLASS_SVE_REG, "SME_Zn_INDEX3_14", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {{3, 14, false}, {5, 5, false}}, "an indexed SVE vector register"},
+ {AARCH64_OPND_CLASS_SVE_REG, "SME_Zn_INDEX3_15", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {{3, 15, false}, {5, 5, false}}, "an indexed SVE vector register"},
+ {AARCH64_OPND_CLASS_SVE_REG, "SME_Zn_INDEX4_14", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {{4, 14, false}, {5, 5, false}}, "an indexed SVE vector register"},
+ {AARCH64_OPND_CLASS_SVE_REG, "SVE_Zn0_INDEX", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {{5, 5, false}}, "an SVE vector register with option zero index"},
+ {AARCH64_OPND_CLASS_SVE_REG, "SVE_Zn1_17_INDEX", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {{1, 17, false}, {5, 5, false}}, "an SVE vector register with optional one bit index"},
+ {AARCH64_OPND_CLASS_SVE_REG, "SVE_Zn2_18_INDEX", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {{2, 17, false}, {5, 5, false}}, "an SVE vector register with optional two bit index"},
+ {AARCH64_OPND_CLASS_SVE_REG, "SVE_Zn3_22_INDEX", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {{1, 22, false}, {2, 17, false}, {5, 5, false}}, "an SVE vector register with optional three bit index"},
+ {AARCH64_OPND_CLASS_SVE_REG, "SVE_Zd0_INDEX", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {{5, 0, false}}, "an SVE vector register with option zero index"},
+ {AARCH64_OPND_CLASS_SVE_REG, "SVE_Zd1_17_INDEX", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {{1, 17, false}, {5, 0, false}}, "an SVE vector register with optional one bit index"},
+ {AARCH64_OPND_CLASS_SVE_REG, "SVE_Zd2_18_INDEX", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {{2, 17, false}, {5, 0, false}}, "an SVE vector register with optional two bit index"},
+ {AARCH64_OPND_CLASS_SVE_REG, "SVE_Zd3_22_INDEX", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {{1, 22, false}, {2, 17, false}, {5, 0, false}}, "an SVE vector register with optional three bit index"},
+ {AARCH64_OPND_CLASS_IMMEDIATE, "SME_VLxN_10", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {{1, 10, false}}, "VLx2 or VLx4"},
+ {AARCH64_OPND_CLASS_IMMEDIATE, "SME_VLxN_13", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {{1, 13, false}}, "VLx2 or VLx4"},
{AARCH64_OPND_CLASS_SYSTEM, "SME_ZT0", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {}, "ZT0"},
- {AARCH64_OPND_CLASS_IMMEDIATE, "SME_ZT0_INDEX", OPD_F_SHIFT_BY_3 | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (12, 3)}, "a ZT0 index"},
- {AARCH64_OPND_CLASS_IMMEDIATE, "SME_ZT0_INDEX_MUL_VL", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (12, 3)}, "a ZT0 index"},
+ {AARCH64_OPND_CLASS_IMMEDIATE, "SME_ZT0_INDEX", OPD_F_SHIFT_BY_3 | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {{3, 12, false}}, "a ZT0 index"},
+ {AARCH64_OPND_CLASS_IMMEDIATE, "SME_ZT0_INDEX_MUL_VL", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {{3, 12, false}}, "a ZT0 index"},
{AARCH64_OPND_CLASS_SYSTEM, "SME_ZT0_LIST", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {}, "{ ZT0 }"},
- {AARCH64_OPND_CLASS_IMMEDIATE, "TME_UIMM16", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (5, 16)}, "a 16-bit unsigned immediate for TME tcancel"},
- {AARCH64_OPND_CLASS_INT_REG, "MOPS_ADDR_Rd", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (0, 5)}, "a register destination address with writeback"},
- {AARCH64_OPND_CLASS_INT_REG, "MOPS_ADDR_Rs", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (16, 5)}, "a register source address with writeback"},
- {AARCH64_OPND_CLASS_INT_REG, "MOPS_WB_Rn", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (5, 5)}, "an integer register with writeback"},
- {AARCH64_OPND_CLASS_IMMEDIATE, "CSSC_SIMM8", OPD_F_SEXT | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (10, 8)}, "an 8-bit signed immediate"},
- {AARCH64_OPND_CLASS_IMMEDIATE, "CSSC_UIMM8", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (10, 8)}, "an 8-bit unsigned immediate"},
- {AARCH64_OPND_CLASS_ADDRESS, "RCPC3_ADDR_OPT_POSTIND", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (12, 4)}, "an address with post-incrementing by ammount of loaded bytes"},
- {AARCH64_OPND_CLASS_ADDRESS, "RCPC3_ADDR_OPT_PREIND_WB", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (12, 4)}, "an address with pre-incrementing with write-back by ammount of stored bytes"},
+ {AARCH64_OPND_CLASS_IMMEDIATE, "TME_UIMM16", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {{16, 5, false}}, "a 16-bit unsigned immediate for TME tcancel"},
+ {AARCH64_OPND_CLASS_INT_REG, "MOPS_ADDR_Rd", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {{5, 0, false}}, "a register destination address with writeback"},
+ {AARCH64_OPND_CLASS_INT_REG, "MOPS_ADDR_Rs", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {{5, 16, false}}, "a register source address with writeback"},
+ {AARCH64_OPND_CLASS_INT_REG, "MOPS_WB_Rn", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {{5, 5, false}}, "an integer register with writeback"},
+ {AARCH64_OPND_CLASS_IMMEDIATE, "CSSC_SIMM8", OPD_F_SEXT | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {{8, 10, false}}, "an 8-bit signed immediate"},
+ {AARCH64_OPND_CLASS_IMMEDIATE, "CSSC_UIMM8", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {{8, 10, false}}, "an 8-bit unsigned immediate"},
+ {AARCH64_OPND_CLASS_ADDRESS, "RCPC3_ADDR_OPT_POSTIND", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {{4, 12, false}}, "an address with post-incrementing by ammount of loaded bytes"},
+ {AARCH64_OPND_CLASS_ADDRESS, "RCPC3_ADDR_OPT_PREIND_WB", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {{4, 12, false}}, "an address with pre-incrementing with write-back by ammount of stored bytes"},
{AARCH64_OPND_CLASS_ADDRESS, "RCPC3_ADDR_POSTIND", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {}, "an address with post-incrementing by ammount of loaded bytes"},
{AARCH64_OPND_CLASS_ADDRESS, "RCPC3_ADDR_PREIND_WB", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {}, "an address with pre-incrementing with write-back by ammount of stored bytes"},
- {AARCH64_OPND_CLASS_ADDRESS, "RCPC3_ADDR_OFFSET", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (5, 5), AARCH64_FIELD (12, 9)}, "an address with an optional 8-bit signed immediate offset"},
+ {AARCH64_OPND_CLASS_ADDRESS, "RCPC3_ADDR_OFFSET", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {{5, 5, false}, {9, 12, false}}, "an address with an optional 8-bit signed immediate offset"},
{AARCH64_OPND_CLASS_SYSTEM, "GIC", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {}, "Generic Interrupt Controller"},
{AARCH64_OPND_CLASS_SYSTEM, "GICR", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {}, "Generic Interrupt Controller"},
{AARCH64_OPND_CLASS_SYSTEM, "GSB", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {}, "Generic Interrupt Controller Synchronization Barrier"},