[PATCH v4 00/12] RISC-V: assorted fixes and (hopefully) improvements

There may not be many dependencies among the patches, but the issues
were all noticed more or less together (i.e. while addressing one,
the next one popped up). I've not made an attempt at sorting the V vs
Z?inx issue, as per Andrew's request.

Quite a few further points are made in remarks in individual patches.
Input there is very welcome.

Jiawei kindly reviewed v1 ... v3, and I meanwhile committed a few more
patches from there (after getting feedback from Nelson). For the others
I'd prefer RISC-V maintainer approval, yet I'm not going to wait
indefinitely.

There are in particular a few new patches in v4. See individual changes
for what changed, if anything.

01: RISC-V: Zv{b,k}* imply Zve32x
02: RISC-V: Zve{32,64}f don't need to explicitly imply Zvl{32,64}b
03: RISC-V: replace INSN_V_EEW64
04: RISC-V: drop FCVT.Q.L{,U} forms with rounding mode operand
05: RISC-V: make FP rounding mode an optional argument
06: RISC-V: check operands for Zdinx in RV32
07: RISC-V: check operands for Zqinx
08: RISC-V/gas: .attribute vs .insn
09: RISC-V/gas: warn about non-boolean unaligned-access attribute
10: RISC-V/gas: warn about non-power-of-2 stack-align attribute
11: RISC-V/bfd: warn about non-boolean unaligned-access attribute
12: RISC-V/bfd: warn about non-power-of-2 stack-align attribute

I'd also like to point out that [1] continues to be pending. I'm far
from insisting that that patch be taken, but something needs doing
about the issue.

Jan

[1] https://sourceware.org/pipermail/binutils/2023-March/126601.html