Re: [PATCH v4 03/12] RISC-V: replace INSN_V_EEW64
Nelson Chu <[email protected]> Mon, 27 Jul 2026 09:40:49 +0800
| Newsgroups | gmane.comp.gnu.binutils |
|---|---|
| Message-ID | <CAHT-pJymxrJcQNtjTu5mfUN27+x3qdTONgV6Hm2qaaQQ63KCiw@mail.gmail.com> |
Cool, thanks for this. Nelson On Fri, Jul 24, 2026 at 6:02 PM Jan Beulich <[email protected]> wrote: > > Introduce INSN_CLASS_ZVE64X instead, making the respective insns (and > diagnostics on their inappropriate use) less special. > --- > v4: New. > > --- a/bfd/elfxx-riscv.c > +++ b/bfd/elfxx-riscv.c > @@ -3001,6 +3001,9 @@ riscv_multi_subset_supports (riscv_parse > return (riscv_subset_supports (rps, "v") > || riscv_subset_supports (rps, "zve64x") > || riscv_subset_supports (rps, "zve32x")); > + case INSN_CLASS_ZVE64X: > + return (riscv_subset_supports (rps, "v") > + || riscv_subset_supports (rps, "zve64x")); > case INSN_CLASS_ZVEF: > return (riscv_subset_supports (rps, "v") > || riscv_subset_supports (rps, "zve64d") > @@ -3355,6 +3358,8 @@ riscv_multi_subset_supports_ext (riscv_p > return "zksh"; > case INSN_CLASS_V: > return _("v' or `zve64x' or `zve32x"); > + case INSN_CLASS_ZVE64X: > + return _("v' or `zve64x"); > case INSN_CLASS_ZVEF: > return _("v' or `zve64d' or `zve64f' or `zve32f"); > case INSN_CLASS_ZVABD: > --- a/gas/config/tc-riscv.c > +++ b/gas/config/tc-riscv.c > @@ -3039,15 +3039,6 @@ riscv_ip (char *str, struct riscv_cl_ins > as_warn (_("read-only CSR is written `%s'"), str); > insn_with_csr = false; > } > - > - /* The (segment) load and store with EEW 64 cannot be used > - when zve32x is enabled. */ > - if ((ip->insn_mo->pinfo & INSN_V_EEW64) > - && !riscv_subset_supports (&riscv_rps_as, "zve64x")) > - { > - error.msg = _("illegal opcode for zve32x"); > - break; > - } > } > if (*asarg != '\0') > break; > --- a/gas/testsuite/gas/riscv/vector-insns-fail-zve32xf.l > +++ b/gas/testsuite/gas/riscv/vector-insns-fail-zve32xf.l > @@ -1,225 +1,225 @@ > .*Assembler messages: > -.*Error: illegal opcode for zve32x `vle64.v v4,\(a0\)' > -.*Error: illegal opcode for zve32x `vle64.v v4,0\(a0\)' > -.*Error: illegal opcode for zve32x `vle64.v v4,\(a0\),v0.t' > -.*Error: illegal opcode for zve32x `vse64.v v4,\(a0\)' > -.*Error: illegal opcode for zve32x `vse64.v v4,0\(a0\)' > -.*Error: illegal opcode for zve32x `vse64.v v4,\(a0\),v0.t' > -.*Error: illegal opcode for zve32x `vlse64.v v4,\(a0\),a1' > -.*Error: illegal opcode for zve32x `vlse64.v v4,0\(a0\),a1' > -.*Error: illegal opcode for zve32x `vlse64.v v4,\(a0\),a1,v0.t' > -.*Error: illegal opcode for zve32x `vsse64.v v4,\(a0\),a1' > -.*Error: illegal opcode for zve32x `vsse64.v v4,0\(a0\),a1' > -.*Error: illegal opcode for zve32x `vsse64.v v4,\(a0\),a1,v0.t' > -.*Error: illegal opcode for zve32x `vloxei64.v v4,\(a0\),v12' > -.*Error: illegal opcode for zve32x `vloxei64.v v4,0\(a0\),v12' > -.*Error: illegal opcode for zve32x `vloxei64.v v4,\(a0\),v12,v0.t' > -.*Error: illegal opcode for zve32x `vsoxei64.v v4,\(a0\),v12' > -.*Error: illegal opcode for zve32x `vsoxei64.v v4,0\(a0\),v12' > -.*Error: illegal opcode for zve32x `vsoxei64.v v4,\(a0\),v12,v0.t' > -.*Error: illegal opcode for zve32x `vluxei64.v v4,\(a0\),v12' > -.*Error: illegal opcode for zve32x `vluxei64.v v4,0\(a0\),v12' > -.*Error: illegal opcode for zve32x `vluxei64.v v4,\(a0\),v12,v0.t' > -.*Error: illegal opcode for zve32x `vsuxei64.v v4,\(a0\),v12' > -.*Error: illegal opcode for zve32x `vsuxei64.v v4,0\(a0\),v12' > -.*Error: illegal opcode for zve32x `vsuxei64.v v4,\(a0\),v12,v0.t' > -.*Error: illegal opcode for zve32x `vle64ff.v v4,\(a0\)' > -.*Error: illegal opcode for zve32x `vle64ff.v v4,0\(a0\)' > -.*Error: illegal opcode for zve32x `vle64ff.v v4,\(a0\),v0.t' > -.*Error: illegal opcode for zve32x `vlseg2e64.v v4,\(a0\)' > -.*Error: illegal opcode for zve32x `vlseg2e64.v v4,0\(a0\)' > -.*Error: illegal opcode for zve32x `vlseg2e64.v v4,\(a0\),v0.t' > -.*Error: illegal opcode for zve32x `vsseg2e64.v v4,\(a0\)' > -.*Error: illegal opcode for zve32x `vsseg2e64.v v4,0\(a0\)' > -.*Error: illegal opcode for zve32x `vsseg2e64.v v4,\(a0\),v0.t' > -.*Error: illegal opcode for zve32x `vlseg3e64.v v4,\(a0\)' > -.*Error: illegal opcode for zve32x `vlseg3e64.v v4,0\(a0\)' > -.*Error: illegal opcode for zve32x `vlseg3e64.v v4,\(a0\),v0.t' > -.*Error: illegal opcode for zve32x `vsseg3e64.v v4,\(a0\)' > -.*Error: illegal opcode for zve32x `vsseg3e64.v v4,0\(a0\)' > -.*Error: illegal opcode for zve32x `vsseg3e64.v v4,\(a0\),v0.t' > -.*Error: illegal opcode for zve32x `vlseg4e64.v v4,\(a0\)' > -.*Error: illegal opcode for zve32x `vlseg4e64.v v4,0\(a0\)' > -.*Error: illegal opcode for zve32x `vlseg4e64.v v4,\(a0\),v0.t' > -.*Error: illegal opcode for zve32x `vsseg4e64.v v4,\(a0\)' > -.*Error: illegal opcode for zve32x `vsseg4e64.v v4,0\(a0\)' > -.*Error: illegal opcode for zve32x `vsseg4e64.v v4,\(a0\),v0.t' > -.*Error: illegal opcode for zve32x `vlseg5e64.v v4,\(a0\)' > -.*Error: illegal opcode for zve32x `vlseg5e64.v v4,0\(a0\)' > -.*Error: illegal opcode for zve32x `vlseg5e64.v v4,\(a0\),v0.t' > -.*Error: illegal opcode for zve32x `vsseg5e64.v v4,\(a0\)' > -.*Error: illegal opcode for zve32x `vsseg5e64.v v4,0\(a0\)' > -.*Error: illegal opcode for zve32x `vsseg5e64.v v4,\(a0\),v0.t' > -.*Error: illegal opcode for zve32x `vlseg6e64.v v4,\(a0\)' > -.*Error: illegal opcode for zve32x `vlseg6e64.v v4,0\(a0\)' > -.*Error: illegal opcode for zve32x `vlseg6e64.v v4,\(a0\),v0.t' > -.*Error: illegal opcode for zve32x `vsseg6e64.v v4,\(a0\)' > -.*Error: illegal opcode for zve32x `vsseg6e64.v v4,0\(a0\)' > -.*Error: illegal opcode for zve32x `vsseg6e64.v v4,\(a0\),v0.t' > -.*Error: illegal opcode for zve32x `vlseg7e64.v v4,\(a0\)' > -.*Error: illegal opcode for zve32x `vlseg7e64.v v4,0\(a0\)' > -.*Error: illegal opcode for zve32x `vlseg7e64.v v4,\(a0\),v0.t' > -.*Error: illegal opcode for zve32x `vsseg7e64.v v4,\(a0\)' > -.*Error: illegal opcode for zve32x `vsseg7e64.v v4,0\(a0\)' > -.*Error: illegal opcode for zve32x `vsseg7e64.v v4,\(a0\),v0.t' > -.*Error: illegal opcode for zve32x `vlseg8e64.v v4,\(a0\)' > -.*Error: illegal opcode for zve32x `vlseg8e64.v v4,0\(a0\)' > -.*Error: illegal opcode for zve32x `vlseg8e64.v v4,\(a0\),v0.t' > -.*Error: illegal opcode for zve32x `vsseg8e64.v v4,\(a0\)' > -.*Error: illegal opcode for zve32x `vsseg8e64.v v4,0\(a0\)' > -.*Error: illegal opcode for zve32x `vsseg8e64.v v4,\(a0\),v0.t' > -.*Error: illegal opcode for zve32x `vlsseg2e64.v v4,\(a0\),a1' > -.*Error: illegal opcode for zve32x `vlsseg2e64.v v4,0\(a0\),a1' > -.*Error: illegal opcode for zve32x `vlsseg2e64.v v4,\(a0\),a1,v0.t' > -.*Error: illegal opcode for zve32x `vssseg2e64.v v4,\(a0\),a1' > -.*Error: illegal opcode for zve32x `vssseg2e64.v v4,0\(a0\),a1' > -.*Error: illegal opcode for zve32x `vssseg2e64.v v4,\(a0\),a1,v0.t' > -.*Error: illegal opcode for zve32x `vlsseg3e64.v v4,\(a0\),a1' > -.*Error: illegal opcode for zve32x `vlsseg3e64.v v4,0\(a0\),a1' > -.*Error: illegal opcode for zve32x `vlsseg3e64.v v4,\(a0\),a1,v0.t' > -.*Error: illegal opcode for zve32x `vssseg3e64.v v4,\(a0\),a1' > -.*Error: illegal opcode for zve32x `vssseg3e64.v v4,0\(a0\),a1' > -.*Error: illegal opcode for zve32x `vssseg3e64.v v4,\(a0\),a1,v0.t' > -.*Error: illegal opcode for zve32x `vlsseg4e64.v v4,\(a0\),a1' > -.*Error: illegal opcode for zve32x `vlsseg4e64.v v4,0\(a0\),a1' > -.*Error: illegal opcode for zve32x `vlsseg4e64.v v4,\(a0\),a1,v0.t' > -.*Error: illegal opcode for zve32x `vssseg4e64.v v4,\(a0\),a1' > -.*Error: illegal opcode for zve32x `vssseg4e64.v v4,0\(a0\),a1' > -.*Error: illegal opcode for zve32x `vssseg4e64.v v4,\(a0\),a1,v0.t' > -.*Error: illegal opcode for zve32x `vlsseg5e64.v v4,\(a0\),a1' > -.*Error: illegal opcode for zve32x `vlsseg5e64.v v4,0\(a0\),a1' > -.*Error: illegal opcode for zve32x `vlsseg5e64.v v4,\(a0\),a1,v0.t' > -.*Error: illegal opcode for zve32x `vssseg5e64.v v4,\(a0\),a1' > -.*Error: illegal opcode for zve32x `vssseg5e64.v v4,0\(a0\),a1' > -.*Error: illegal opcode for zve32x `vssseg5e64.v v4,\(a0\),a1,v0.t' > -.*Error: illegal opcode for zve32x `vlsseg6e64.v v4,\(a0\),a1' > -.*Error: illegal opcode for zve32x `vlsseg6e64.v v4,0\(a0\),a1' > -.*Error: illegal opcode for zve32x `vlsseg6e64.v v4,\(a0\),a1,v0.t' > -.*Error: illegal opcode for zve32x `vssseg6e64.v v4,\(a0\),a1' > -.*Error: illegal opcode for zve32x `vssseg6e64.v v4,0\(a0\),a1' > -.*Error: illegal opcode for zve32x `vssseg6e64.v v4,\(a0\),a1,v0.t' > -.*Error: illegal opcode for zve32x `vlsseg7e64.v v4,\(a0\),a1' > -.*Error: illegal opcode for zve32x `vlsseg7e64.v v4,0\(a0\),a1' > -.*Error: illegal opcode for zve32x `vlsseg7e64.v v4,\(a0\),a1,v0.t' > -.*Error: illegal opcode for zve32x `vssseg7e64.v v4,\(a0\),a1' > -.*Error: illegal opcode for zve32x `vssseg7e64.v v4,0\(a0\),a1' > -.*Error: illegal opcode for zve32x `vssseg7e64.v v4,\(a0\),a1,v0.t' > -.*Error: illegal opcode for zve32x `vlsseg8e64.v v4,\(a0\),a1' > -.*Error: illegal opcode for zve32x `vlsseg8e64.v v4,0\(a0\),a1' > -.*Error: illegal opcode for zve32x `vlsseg8e64.v v4,\(a0\),a1,v0.t' > -.*Error: illegal opcode for zve32x `vssseg8e64.v v4,\(a0\),a1' > -.*Error: illegal opcode for zve32x `vssseg8e64.v v4,0\(a0\),a1' > -.*Error: illegal opcode for zve32x `vssseg8e64.v v4,\(a0\),a1,v0.t' > -.*Error: illegal opcode for zve32x `vloxseg2ei64.v v4,\(a0\),v12' > -.*Error: illegal opcode for zve32x `vloxseg2ei64.v v4,0\(a0\),v12' > -.*Error: illegal opcode for zve32x `vloxseg2ei64.v v4,\(a0\),v12,v0.t' > -.*Error: illegal opcode for zve32x `vsoxseg2ei64.v v4,\(a0\),v12' > -.*Error: illegal opcode for zve32x `vsoxseg2ei64.v v4,0\(a0\),v12' > -.*Error: illegal opcode for zve32x `vsoxseg2ei64.v v4,\(a0\),v12,v0.t' > -.*Error: illegal opcode for zve32x `vloxseg3ei64.v v4,\(a0\),v12' > -.*Error: illegal opcode for zve32x `vloxseg3ei64.v v4,0\(a0\),v12' > -.*Error: illegal opcode for zve32x `vloxseg3ei64.v v4,\(a0\),v12,v0.t' > -.*Error: illegal opcode for zve32x `vsoxseg3ei64.v v4,\(a0\),v12' > -.*Error: illegal opcode for zve32x `vsoxseg3ei64.v v4,0\(a0\),v12' > -.*Error: illegal opcode for zve32x `vsoxseg3ei64.v v4,\(a0\),v12,v0.t' > -.*Error: illegal opcode for zve32x `vloxseg4ei64.v v4,\(a0\),v12' > -.*Error: illegal opcode for zve32x `vloxseg4ei64.v v4,0\(a0\),v12' > -.*Error: illegal opcode for zve32x `vloxseg4ei64.v v4,\(a0\),v12,v0.t' > -.*Error: illegal opcode for zve32x `vsoxseg4ei64.v v4,\(a0\),v12' > -.*Error: illegal opcode for zve32x `vsoxseg4ei64.v v4,0\(a0\),v12' > -.*Error: illegal opcode for zve32x `vsoxseg4ei64.v v4,\(a0\),v12,v0.t' > -.*Error: illegal opcode for zve32x `vloxseg5ei64.v v4,\(a0\),v12' > -.*Error: illegal opcode for zve32x `vloxseg5ei64.v v4,0\(a0\),v12' > -.*Error: illegal opcode for zve32x `vloxseg5ei64.v v4,\(a0\),v12,v0.t' > -.*Error: illegal opcode for zve32x `vsoxseg5ei64.v v4,\(a0\),v12' > -.*Error: illegal opcode for zve32x `vsoxseg5ei64.v v4,0\(a0\),v12' > -.*Error: illegal opcode for zve32x `vsoxseg5ei64.v v4,\(a0\),v12,v0.t' > -.*Error: illegal opcode for zve32x `vloxseg6ei64.v v4,\(a0\),v12' > -.*Error: illegal opcode for zve32x `vloxseg6ei64.v v4,0\(a0\),v12' > -.*Error: illegal opcode for zve32x `vloxseg6ei64.v v4,\(a0\),v12,v0.t' > -.*Error: illegal opcode for zve32x `vsoxseg6ei64.v v4,\(a0\),v12' > -.*Error: illegal opcode for zve32x `vsoxseg6ei64.v v4,0\(a0\),v12' > -.*Error: illegal opcode for zve32x `vsoxseg6ei64.v v4,\(a0\),v12,v0.t' > -.*Error: illegal opcode for zve32x `vloxseg7ei64.v v4,\(a0\),v12' > -.*Error: illegal opcode for zve32x `vloxseg7ei64.v v4,0\(a0\),v12' > -.*Error: illegal opcode for zve32x `vloxseg7ei64.v v4,\(a0\),v12,v0.t' > -.*Error: illegal opcode for zve32x `vsoxseg7ei64.v v4,\(a0\),v12' > -.*Error: illegal opcode for zve32x `vsoxseg7ei64.v v4,0\(a0\),v12' > -.*Error: illegal opcode for zve32x `vsoxseg7ei64.v v4,\(a0\),v12,v0.t' > -.*Error: illegal opcode for zve32x `vloxseg8ei64.v v4,\(a0\),v12' > -.*Error: illegal opcode for zve32x `vloxseg8ei64.v v4,0\(a0\),v12' > -.*Error: illegal opcode for zve32x `vloxseg8ei64.v v4,\(a0\),v12,v0.t' > -.*Error: illegal opcode for zve32x `vsoxseg8ei64.v v4,\(a0\),v12' > -.*Error: illegal opcode for zve32x `vsoxseg8ei64.v v4,0\(a0\),v12' > -.*Error: illegal opcode for zve32x `vsoxseg8ei64.v v4,\(a0\),v12,v0.t' > -.*Error: illegal opcode for zve32x `vluxseg2ei64.v v4,\(a0\),v12' > -.*Error: illegal opcode for zve32x `vluxseg2ei64.v v4,0\(a0\),v12' > -.*Error: illegal opcode for zve32x `vluxseg2ei64.v v4,\(a0\),v12,v0.t' > -.*Error: illegal opcode for zve32x `vsuxseg2ei64.v v4,\(a0\),v12' > -.*Error: illegal opcode for zve32x `vsuxseg2ei64.v v4,0\(a0\),v12' > -.*Error: illegal opcode for zve32x `vsuxseg2ei64.v v4,\(a0\),v12,v0.t' > -.*Error: illegal opcode for zve32x `vluxseg3ei64.v v4,\(a0\),v12' > -.*Error: illegal opcode for zve32x `vluxseg3ei64.v v4,0\(a0\),v12' > -.*Error: illegal opcode for zve32x `vluxseg3ei64.v v4,\(a0\),v12,v0.t' > -.*Error: illegal opcode for zve32x `vsuxseg3ei64.v v4,\(a0\),v12' > -.*Error: illegal opcode for zve32x `vsuxseg3ei64.v v4,0\(a0\),v12' > -.*Error: illegal opcode for zve32x `vsuxseg3ei64.v v4,\(a0\),v12,v0.t' > -.*Error: illegal opcode for zve32x `vluxseg4ei64.v v4,\(a0\),v12' > -.*Error: illegal opcode for zve32x `vluxseg4ei64.v v4,0\(a0\),v12' > -.*Error: illegal opcode for zve32x `vluxseg4ei64.v v4,\(a0\),v12,v0.t' > -.*Error: illegal opcode for zve32x `vsuxseg4ei64.v v4,\(a0\),v12' > -.*Error: illegal opcode for zve32x `vsuxseg4ei64.v v4,0\(a0\),v12' > -.*Error: illegal opcode for zve32x `vsuxseg4ei64.v v4,\(a0\),v12,v0.t' > -.*Error: illegal opcode for zve32x `vluxseg5ei64.v v4,\(a0\),v12' > -.*Error: illegal opcode for zve32x `vluxseg5ei64.v v4,0\(a0\),v12' > -.*Error: illegal opcode for zve32x `vluxseg5ei64.v v4,\(a0\),v12,v0.t' > -.*Error: illegal opcode for zve32x `vsuxseg5ei64.v v4,\(a0\),v12' > -.*Error: illegal opcode for zve32x `vsuxseg5ei64.v v4,0\(a0\),v12' > -.*Error: illegal opcode for zve32x `vsuxseg5ei64.v v4,\(a0\),v12,v0.t' > -.*Error: illegal opcode for zve32x `vluxseg6ei64.v v4,\(a0\),v12' > -.*Error: illegal opcode for zve32x `vluxseg6ei64.v v4,0\(a0\),v12' > -.*Error: illegal opcode for zve32x `vluxseg6ei64.v v4,\(a0\),v12,v0.t' > -.*Error: illegal opcode for zve32x `vsuxseg6ei64.v v4,\(a0\),v12' > -.*Error: illegal opcode for zve32x `vsuxseg6ei64.v v4,0\(a0\),v12' > -.*Error: illegal opcode for zve32x `vsuxseg6ei64.v v4,\(a0\),v12,v0.t' > -.*Error: illegal opcode for zve32x `vluxseg7ei64.v v4,\(a0\),v12' > -.*Error: illegal opcode for zve32x `vluxseg7ei64.v v4,0\(a0\),v12' > -.*Error: illegal opcode for zve32x `vluxseg7ei64.v v4,\(a0\),v12,v0.t' > -.*Error: illegal opcode for zve32x `vsuxseg7ei64.v v4,\(a0\),v12' > -.*Error: illegal opcode for zve32x `vsuxseg7ei64.v v4,0\(a0\),v12' > -.*Error: illegal opcode for zve32x `vsuxseg7ei64.v v4,\(a0\),v12,v0.t' > -.*Error: illegal opcode for zve32x `vluxseg8ei64.v v4,\(a0\),v12' > -.*Error: illegal opcode for zve32x `vluxseg8ei64.v v4,0\(a0\),v12' > -.*Error: illegal opcode for zve32x `vluxseg8ei64.v v4,\(a0\),v12,v0.t' > -.*Error: illegal opcode for zve32x `vsuxseg8ei64.v v4,\(a0\),v12' > -.*Error: illegal opcode for zve32x `vsuxseg8ei64.v v4,0\(a0\),v12' > -.*Error: illegal opcode for zve32x `vsuxseg8ei64.v v4,\(a0\),v12,v0.t' > -.*Error: illegal opcode for zve32x `vlseg2e64ff.v v4,\(a0\)' > -.*Error: illegal opcode for zve32x `vlseg2e64ff.v v4,0\(a0\)' > -.*Error: illegal opcode for zve32x `vlseg2e64ff.v v4,\(a0\),v0.t' > -.*Error: illegal opcode for zve32x `vlseg3e64ff.v v4,\(a0\)' > -.*Error: illegal opcode for zve32x `vlseg3e64ff.v v4,0\(a0\)' > -.*Error: illegal opcode for zve32x `vlseg3e64ff.v v4,\(a0\),v0.t' > -.*Error: illegal opcode for zve32x `vlseg4e64ff.v v4,\(a0\)' > -.*Error: illegal opcode for zve32x `vlseg4e64ff.v v4,0\(a0\)' > -.*Error: illegal opcode for zve32x `vlseg4e64ff.v v4,\(a0\),v0.t' > -.*Error: illegal opcode for zve32x `vlseg5e64ff.v v4,\(a0\)' > -.*Error: illegal opcode for zve32x `vlseg5e64ff.v v4,0\(a0\)' > -.*Error: illegal opcode for zve32x `vlseg5e64ff.v v4,\(a0\),v0.t' > -.*Error: illegal opcode for zve32x `vlseg6e64ff.v v4,\(a0\)' > -.*Error: illegal opcode for zve32x `vlseg6e64ff.v v4,0\(a0\)' > -.*Error: illegal opcode for zve32x `vlseg6e64ff.v v4,\(a0\),v0.t' > -.*Error: illegal opcode for zve32x `vlseg7e64ff.v v4,\(a0\)' > -.*Error: illegal opcode for zve32x `vlseg7e64ff.v v4,0\(a0\)' > -.*Error: illegal opcode for zve32x `vlseg7e64ff.v v4,\(a0\),v0.t' > -.*Error: illegal opcode for zve32x `vlseg8e64ff.v v4,\(a0\)' > -.*Error: illegal opcode for zve32x `vlseg8e64ff.v v4,0\(a0\)' > -.*Error: illegal opcode for zve32x `vlseg8e64ff.v v4,\(a0\),v0.t' > -.*Error: illegal opcode for zve32x `vl1re64.v v3,\(a0\)' > -.*Error: illegal opcode for zve32x `vl1re64.v v3,0\(a0\)' > -.*Error: illegal opcode for zve32x `vl2re64.v v2,\(a0\)' > -.*Error: illegal opcode for zve32x `vl2re64.v v2,0\(a0\)' > -.*Error: illegal opcode for zve32x `vl4re64.v v4,\(a0\)' > -.*Error: illegal opcode for zve32x `vl4re64.v v4,0\(a0\)' > -.*Error: illegal opcode for zve32x `vl8re64.v v8,\(a0\)' > -.*Error: illegal opcode for zve32x `vl8re64.v v8,0\(a0\)' > +.*Error: unrecognized opcode `vle64.v v4,\(a0\)', extension `v' or `zve64x' required > +.*Error: unrecognized opcode `vle64.v v4,0\(a0\)', extension `v' or `zve64x' required > +.*Error: unrecognized opcode `vle64.v v4,\(a0\),v0.t', extension `v' or `zve64x' required > +.*Error: unrecognized opcode `vse64.v v4,\(a0\)', extension `v' or `zve64x' required > +.*Error: unrecognized opcode `vse64.v v4,0\(a0\)', extension `v' or `zve64x' required > +.*Error: unrecognized opcode `vse64.v v4,\(a0\),v0.t', extension `v' or `zve64x' required > +.*Error: unrecognized opcode `vlse64.v v4,\(a0\),a1', extension `v' or `zve64x' required > +.*Error: unrecognized opcode `vlse64.v v4,0\(a0\),a1', extension `v' or `zve64x' required > +.*Error: unrecognized opcode `vlse64.v v4,\(a0\),a1,v0.t', extension `v' or `zve64x' required > +.*Error: unrecognized opcode `vsse64.v v4,\(a0\),a1', extension `v' or `zve64x' required > +.*Error: unrecognized opcode `vsse64.v v4,0\(a0\),a1', extension `v' or `zve64x' required > +.*Error: unrecognized opcode `vsse64.v v4,\(a0\),a1,v0.t', extension `v' or `zve64x' required > +.*Error: unrecognized opcode `vloxei64.v v4,\(a0\),v12', extension `v' or `zve64x' required > +.*Error: unrecognized opcode `vloxei64.v v4,0\(a0\),v12', extension `v' or `zve64x' required > +.*Error: unrecognized opcode `vloxei64.v v4,\(a0\),v12,v0.t', extension `v' or `zve64x' required > +.*Error: unrecognized opcode `vsoxei64.v v4,\(a0\),v12', extension `v' or `zve64x' required > +.*Error: unrecognized opcode `vsoxei64.v v4,0\(a0\),v12', extension `v' or `zve64x' required > +.*Error: unrecognized opcode `vsoxei64.v v4,\(a0\),v12,v0.t', extension `v' or `zve64x' required > +.*Error: unrecognized opcode `vluxei64.v v4,\(a0\),v12', extension `v' or `zve64x' required > +.*Error: unrecognized opcode `vluxei64.v v4,0\(a0\),v12', extension `v' or `zve64x' required > +.*Error: unrecognized opcode `vluxei64.v v4,\(a0\),v12,v0.t', extension `v' or `zve64x' required > +.*Error: unrecognized opcode `vsuxei64.v v4,\(a0\),v12', extension `v' or `zve64x' required > +.*Error: unrecognized opcode `vsuxei64.v v4,0\(a0\),v12', extension `v' or `zve64x' required > +.*Error: unrecognized opcode `vsuxei64.v v4,\(a0\),v12,v0.t', extension `v' or `zve64x' required > +.*Error: unrecognized opcode `vle64ff.v v4,\(a0\)', extension `v' or `zve64x' required > +.*Error: unrecognized opcode `vle64ff.v v4,0\(a0\)', extension `v' or `zve64x' required > +.*Error: unrecognized opcode `vle64ff.v v4,\(a0\),v0.t', extension `v' or `zve64x' required > +.*Error: unrecognized opcode `vlseg2e64.v v4,\(a0\)', extension `v' or `zve64x' required > +.*Error: unrecognized opcode `vlseg2e64.v v4,0\(a0\)', extension `v' or `zve64x' required > +.*Error: unrecognized opcode `vlseg2e64.v v4,\(a0\),v0.t', extension `v' or `zve64x' required > +.*Error: unrecognized opcode `vsseg2e64.v v4,\(a0\)', extension `v' or `zve64x' required > +.*Error: unrecognized opcode `vsseg2e64.v v4,0\(a0\)', extension `v' or `zve64x' required > +.*Error: unrecognized opcode `vsseg2e64.v v4,\(a0\),v0.t', extension `v' or `zve64x' required > +.*Error: unrecognized opcode `vlseg3e64.v v4,\(a0\)', extension `v' or `zve64x' required > +.*Error: unrecognized opcode `vlseg3e64.v v4,0\(a0\)', extension `v' or `zve64x' required > +.*Error: unrecognized opcode `vlseg3e64.v v4,\(a0\),v0.t', extension `v' or `zve64x' required > +.*Error: unrecognized opcode `vsseg3e64.v v4,\(a0\)', extension `v' or `zve64x' required > +.*Error: unrecognized opcode `vsseg3e64.v v4,0\(a0\)', extension `v' or `zve64x' required > +.*Error: unrecognized opcode `vsseg3e64.v v4,\(a0\),v0.t', extension `v' or `zve64x' required > +.*Error: unrecognized opcode `vlseg4e64.v v4,\(a0\)', extension `v' or `zve64x' required > +.*Error: unrecognized opcode `vlseg4e64.v v4,0\(a0\)', extension `v' or `zve64x' required > +.*Error: unrecognized opcode `vlseg4e64.v v4,\(a0\),v0.t', extension `v' or `zve64x' required > +.*Error: unrecognized opcode `vsseg4e64.v v4,\(a0\)', extension `v' or `zve64x' required > +.*Error: unrecognized opcode `vsseg4e64.v v4,0\(a0\)', extension `v' or `zve64x' required > +.*Error: unrecognized opcode `vsseg4e64.v v4,\(a0\),v0.t', extension `v' or `zve64x' required > +.*Error: unrecognized opcode `vlseg5e64.v v4,\(a0\)', extension `v' or `zve64x' required > +.*Error: unrecognized opcode `vlseg5e64.v v4,0\(a0\)', extension `v' or `zve64x' required > +.*Error: unrecognized opcode `vlseg5e64.v v4,\(a0\),v0.t', extension `v' or `zve64x' required > +.*Error: unrecognized opcode `vsseg5e64.v v4,\(a0\)', extension `v' or `zve64x' required > +.*Error: unrecognized opcode `vsseg5e64.v v4,0\(a0\)', extension `v' or `zve64x' required > +.*Error: unrecognized opcode `vsseg5e64.v v4,\(a0\),v0.t', extension `v' or `zve64x' required > +.*Error: unrecognized opcode `vlseg6e64.v v4,\(a0\)', extension `v' or `zve64x' required > +.*Error: unrecognized opcode `vlseg6e64.v v4,0\(a0\)', extension `v' or `zve64x' required > +.*Error: unrecognized opcode `vlseg6e64.v v4,\(a0\),v0.t', extension `v' or `zve64x' required > +.*Error: unrecognized opcode `vsseg6e64.v v4,\(a0\)', extension `v' or `zve64x' required > +.*Error: unrecognized opcode `vsseg6e64.v v4,0\(a0\)', extension `v' or `zve64x' required > +.*Error: unrecognized opcode `vsseg6e64.v v4,\(a0\),v0.t', extension `v' or `zve64x' required > +.*Error: unrecognized opcode `vlseg7e64.v v4,\(a0\)', extension `v' or `zve64x' required > +.*Error: unrecognized opcode `vlseg7e64.v v4,0\(a0\)', extension `v' or `zve64x' required > +.*Error: unrecognized opcode `vlseg7e64.v v4,\(a0\),v0.t', extension `v' or `zve64x' required > +.*Error: unrecognized opcode `vsseg7e64.v v4,\(a0\)', extension `v' or `zve64x' required > +.*Error: unrecognized opcode `vsseg7e64.v v4,0\(a0\)', extension `v' or `zve64x' required > +.*Error: unrecognized opcode `vsseg7e64.v v4,\(a0\),v0.t', extension `v' or `zve64x' required > +.*Error: unrecognized opcode `vlseg8e64.v v4,\(a0\)', extension `v' or `zve64x' required > +.*Error: unrecognized opcode `vlseg8e64.v v4,0\(a0\)', extension `v' or `zve64x' required > +.*Error: unrecognized opcode `vlseg8e64.v v4,\(a0\),v0.t', extension `v' or `zve64x' required > +.*Error: unrecognized opcode `vsseg8e64.v v4,\(a0\)', extension `v' or `zve64x' required > +.*Error: unrecognized opcode `vsseg8e64.v v4,0\(a0\)', extension `v' or `zve64x' required > +.*Error: unrecognized opcode `vsseg8e64.v v4,\(a0\),v0.t', extension `v' or `zve64x' required > +.*Error: unrecognized opcode `vlsseg2e64.v v4,\(a0\),a1', extension `v' or `zve64x' required > +.*Error: unrecognized opcode `vlsseg2e64.v v4,0\(a0\),a1', extension `v' or `zve64x' required > +.*Error: unrecognized opcode `vlsseg2e64.v v4,\(a0\),a1,v0.t', extension `v' or `zve64x' required > +.*Error: unrecognized opcode `vssseg2e64.v v4,\(a0\),a1', extension `v' or `zve64x' required > +.*Error: unrecognized opcode `vssseg2e64.v v4,0\(a0\),a1', extension `v' or `zve64x' required > +.*Error: unrecognized opcode `vssseg2e64.v v4,\(a0\),a1,v0.t', extension `v' or `zve64x' required > +.*Error: unrecognized opcode `vlsseg3e64.v v4,\(a0\),a1', extension `v' or `zve64x' required > +.*Error: unrecognized opcode `vlsseg3e64.v v4,0\(a0\),a1', extension `v' or `zve64x' required > +.*Error: unrecognized opcode `vlsseg3e64.v v4,\(a0\),a1,v0.t', extension `v' or `zve64x' required > +.*Error: unrecognized opcode `vssseg3e64.v v4,\(a0\),a1', extension `v' or `zve64x' required > +.*Error: unrecognized opcode `vssseg3e64.v v4,0\(a0\),a1', extension `v' or `zve64x' required > +.*Error: unrecognized opcode `vssseg3e64.v v4,\(a0\),a1,v0.t', extension `v' or `zve64x' required > +.*Error: unrecognized opcode `vlsseg4e64.v v4,\(a0\),a1', extension `v' or `zve64x' required > +.*Error: unrecognized opcode `vlsseg4e64.v v4,0\(a0\),a1', extension `v' or `zve64x' required > +.*Error: unrecognized opcode `vlsseg4e64.v v4,\(a0\),a1,v0.t', extension `v' or `zve64x' required > +.*Error: unrecognized opcode `vssseg4e64.v v4,\(a0\),a1', extension `v' or `zve64x' required > +.*Error: unrecognized opcode `vssseg4e64.v v4,0\(a0\),a1', extension `v' or `zve64x' required > +.*Error: unrecognized opcode `vssseg4e64.v v4,\(a0\),a1,v0.t', extension `v' or `zve64x' required > +.*Error: unrecognized opcode `vlsseg5e64.v v4,\(a0\),a1', extension `v' or `zve64x' required > +.*Error: unrecognized opcode `vlsseg5e64.v v4,0\(a0\),a1', extension `v' or `zve64x' required > +.*Error: unrecognized opcode `vlsseg5e64.v v4,\(a0\),a1,v0.t', extension `v' or `zve64x' required > +.*Error: unrecognized opcode `vssseg5e64.v v4,\(a0\),a1', extension `v' or `zve64x' required > +.*Error: unrecognized opcode `vssseg5e64.v v4,0\(a0\),a1', extension `v' or `zve64x' required > +.*Error: unrecognized opcode `vssseg5e64.v v4,\(a0\),a1,v0.t', extension `v' or `zve64x' required > +.*Error: unrecognized opcode `vlsseg6e64.v v4,\(a0\),a1', extension `v' or `zve64x' required > +.*Error: unrecognized opcode `vlsseg6e64.v v4,0\(a0\),a1', extension `v' or `zve64x' required > +.*Error: unrecognized opcode `vlsseg6e64.v v4,\(a0\),a1,v0.t', extension `v' or `zve64x' required > +.*Error: unrecognized opcode `vssseg6e64.v v4,\(a0\),a1', extension `v' or `zve64x' required > +.*Error: unrecognized opcode `vssseg6e64.v v4,0\(a0\),a1', extension `v' or `zve64x' required > +.*Error: unrecognized opcode `vssseg6e64.v v4,\(a0\),a1,v0.t', extension `v' or `zve64x' required > +.*Error: unrecognized opcode `vlsseg7e64.v v4,\(a0\),a1', extension `v' or `zve64x' required > +.*Error: unrecognized opcode `vlsseg7e64.v v4,0\(a0\),a1', extension `v' or `zve64x' required > +.*Error: unrecognized opcode `vlsseg7e64.v v4,\(a0\),a1,v0.t', extension `v' or `zve64x' required > +.*Error: unrecognized opcode `vssseg7e64.v v4,\(a0\),a1', extension `v' or `zve64x' required > +.*Error: unrecognized opcode `vssseg7e64.v v4,0\(a0\),a1', extension `v' or `zve64x' required > +.*Error: unrecognized opcode `vssseg7e64.v v4,\(a0\),a1,v0.t', extension `v' or `zve64x' required > +.*Error: unrecognized opcode `vlsseg8e64.v v4,\(a0\),a1', extension `v' or `zve64x' required > +.*Error: unrecognized opcode `vlsseg8e64.v v4,0\(a0\),a1', extension `v' or `zve64x' required > +.*Error: unrecognized opcode `vlsseg8e64.v v4,\(a0\),a1,v0.t', extension `v' or `zve64x' required > +.*Error: unrecognized opcode `vssseg8e64.v v4,\(a0\),a1', extension `v' or `zve64x' required > +.*Error: unrecognized opcode `vssseg8e64.v v4,0\(a0\),a1', extension `v' or `zve64x' required > +.*Error: unrecognized opcode `vssseg8e64.v v4,\(a0\),a1,v0.t', extension `v' or `zve64x' required > +.*Error: unrecognized opcode `vloxseg2ei64.v v4,\(a0\),v12', extension `v' or `zve64x' required > +.*Error: unrecognized opcode `vloxseg2ei64.v v4,0\(a0\),v12', extension `v' or `zve64x' required > +.*Error: unrecognized opcode `vloxseg2ei64.v v4,\(a0\),v12,v0.t', extension `v' or `zve64x' required > +.*Error: unrecognized opcode `vsoxseg2ei64.v v4,\(a0\),v12', extension `v' or `zve64x' required > +.*Error: unrecognized opcode `vsoxseg2ei64.v v4,0\(a0\),v12', extension `v' or `zve64x' required > +.*Error: unrecognized opcode `vsoxseg2ei64.v v4,\(a0\),v12,v0.t', extension `v' or `zve64x' required > +.*Error: unrecognized opcode `vloxseg3ei64.v v4,\(a0\),v12', extension `v' or `zve64x' required > +.*Error: unrecognized opcode `vloxseg3ei64.v v4,0\(a0\),v12', extension `v' or `zve64x' required > +.*Error: unrecognized opcode `vloxseg3ei64.v v4,\(a0\),v12,v0.t', extension `v' or `zve64x' required > +.*Error: unrecognized opcode `vsoxseg3ei64.v v4,\(a0\),v12', extension `v' or `zve64x' required > +.*Error: unrecognized opcode `vsoxseg3ei64.v v4,0\(a0\),v12', extension `v' or `zve64x' required > +.*Error: unrecognized opcode `vsoxseg3ei64.v v4,\(a0\),v12,v0.t', extension `v' or `zve64x' required > +.*Error: unrecognized opcode `vloxseg4ei64.v v4,\(a0\),v12', extension `v' or `zve64x' required > +.*Error: unrecognized opcode `vloxseg4ei64.v v4,0\(a0\),v12', extension `v' or `zve64x' required > +.*Error: unrecognized opcode `vloxseg4ei64.v v4,\(a0\),v12,v0.t', extension `v' or `zve64x' required > +.*Error: unrecognized opcode `vsoxseg4ei64.v v4,\(a0\),v12', extension `v' or `zve64x' required > +.*Error: unrecognized opcode `vsoxseg4ei64.v v4,0\(a0\),v12', extension `v' or `zve64x' required > +.*Error: unrecognized opcode `vsoxseg4ei64.v v4,\(a0\),v12,v0.t', extension `v' or `zve64x' required > +.*Error: unrecognized opcode `vloxseg5ei64.v v4,\(a0\),v12', extension `v' or `zve64x' required > +.*Error: unrecognized opcode `vloxseg5ei64.v v4,0\(a0\),v12', extension `v' or `zve64x' required > +.*Error: unrecognized opcode `vloxseg5ei64.v v4,\(a0\),v12,v0.t', extension `v' or `zve64x' required > +.*Error: unrecognized opcode `vsoxseg5ei64.v v4,\(a0\),v12', extension `v' or `zve64x' required > +.*Error: unrecognized opcode `vsoxseg5ei64.v v4,0\(a0\),v12', extension `v' or `zve64x' required > +.*Error: unrecognized opcode `vsoxseg5ei64.v v4,\(a0\),v12,v0.t', extension `v' or `zve64x' required > +.*Error: unrecognized opcode `vloxseg6ei64.v v4,\(a0\),v12', extension `v' or `zve64x' required > +.*Error: unrecognized opcode `vloxseg6ei64.v v4,0\(a0\),v12', extension `v' or `zve64x' required > +.*Error: unrecognized opcode `vloxseg6ei64.v v4,\(a0\),v12,v0.t', extension `v' or `zve64x' required > +.*Error: unrecognized opcode `vsoxseg6ei64.v v4,\(a0\),v12', extension `v' or `zve64x' required > +.*Error: unrecognized opcode `vsoxseg6ei64.v v4,0\(a0\),v12', extension `v' or `zve64x' required > +.*Error: unrecognized opcode `vsoxseg6ei64.v v4,\(a0\),v12,v0.t', extension `v' or `zve64x' required > +.*Error: unrecognized opcode `vloxseg7ei64.v v4,\(a0\),v12', extension `v' or `zve64x' required > +.*Error: unrecognized opcode `vloxseg7ei64.v v4,0\(a0\),v12', extension `v' or `zve64x' required > +.*Error: unrecognized opcode `vloxseg7ei64.v v4,\(a0\),v12,v0.t', extension `v' or `zve64x' required > +.*Error: unrecognized opcode `vsoxseg7ei64.v v4,\(a0\),v12', extension `v' or `zve64x' required > +.*Error: unrecognized opcode `vsoxseg7ei64.v v4,0\(a0\),v12', extension `v' or `zve64x' required > +.*Error: unrecognized opcode `vsoxseg7ei64.v v4,\(a0\),v12,v0.t', extension `v' or `zve64x' required > +.*Error: unrecognized opcode `vloxseg8ei64.v v4,\(a0\),v12', extension `v' or `zve64x' required > +.*Error: unrecognized opcode `vloxseg8ei64.v v4,0\(a0\),v12', extension `v' or `zve64x' required > +.*Error: unrecognized opcode `vloxseg8ei64.v v4,\(a0\),v12,v0.t', extension `v' or `zve64x' required > +.*Error: unrecognized opcode `vsoxseg8ei64.v v4,\(a0\),v12', extension `v' or `zve64x' required > +.*Error: unrecognized opcode `vsoxseg8ei64.v v4,0\(a0\),v12', extension `v' or `zve64x' required > +.*Error: unrecognized opcode `vsoxseg8ei64.v v4,\(a0\),v12,v0.t', extension `v' or `zve64x' required > +.*Error: unrecognized opcode `vluxseg2ei64.v v4,\(a0\),v12', extension `v' or `zve64x' required > +.*Error: unrecognized opcode `vluxseg2ei64.v v4,0\(a0\),v12', extension `v' or `zve64x' required > +.*Error: unrecognized opcode `vluxseg2ei64.v v4,\(a0\),v12,v0.t', extension `v' or `zve64x' required > +.*Error: unrecognized opcode `vsuxseg2ei64.v v4,\(a0\),v12', extension `v' or `zve64x' required > +.*Error: unrecognized opcode `vsuxseg2ei64.v v4,0\(a0\),v12', extension `v' or `zve64x' required > +.*Error: unrecognized opcode `vsuxseg2ei64.v v4,\(a0\),v12,v0.t', extension `v' or `zve64x' required > +.*Error: unrecognized opcode `vluxseg3ei64.v v4,\(a0\),v12', extension `v' or `zve64x' required > +.*Error: unrecognized opcode `vluxseg3ei64.v v4,0\(a0\),v12', extension `v' or `zve64x' required > +.*Error: unrecognized opcode `vluxseg3ei64.v v4,\(a0\),v12,v0.t', extension `v' or `zve64x' required > +.*Error: unrecognized opcode `vsuxseg3ei64.v v4,\(a0\),v12', extension `v' or `zve64x' required > +.*Error: unrecognized opcode `vsuxseg3ei64.v v4,0\(a0\),v12', extension `v' or `zve64x' required > +.*Error: unrecognized opcode `vsuxseg3ei64.v v4,\(a0\),v12,v0.t', extension `v' or `zve64x' required > +.*Error: unrecognized opcode `vluxseg4ei64.v v4,\(a0\),v12', extension `v' or `zve64x' required > +.*Error: unrecognized opcode `vluxseg4ei64.v v4,0\(a0\),v12', extension `v' or `zve64x' required > +.*Error: unrecognized opcode `vluxseg4ei64.v v4,\(a0\),v12,v0.t', extension `v' or `zve64x' required > +.*Error: unrecognized opcode `vsuxseg4ei64.v v4,\(a0\),v12', extension `v' or `zve64x' required > +.*Error: unrecognized opcode `vsuxseg4ei64.v v4,0\(a0\),v12', extension `v' or `zve64x' required > +.*Error: unrecognized opcode `vsuxseg4ei64.v v4,\(a0\),v12,v0.t', extension `v' or `zve64x' required > +.*Error: unrecognized opcode `vluxseg5ei64.v v4,\(a0\),v12', extension `v' or `zve64x' required > +.*Error: unrecognized opcode `vluxseg5ei64.v v4,0\(a0\),v12', extension `v' or `zve64x' required > +.*Error: unrecognized opcode `vluxseg5ei64.v v4,\(a0\),v12,v0.t', extension `v' or `zve64x' required > +.*Error: unrecognized opcode `vsuxseg5ei64.v v4,\(a0\),v12', extension `v' or `zve64x' required > +.*Error: unrecognized opcode `vsuxseg5ei64.v v4,0\(a0\),v12', extension `v' or `zve64x' required > +.*Error: unrecognized opcode `vsuxseg5ei64.v v4,\(a0\),v12,v0.t', extension `v' or `zve64x' required > +.*Error: unrecognized opcode `vluxseg6ei64.v v4,\(a0\),v12', extension `v' or `zve64x' required > +.*Error: unrecognized opcode `vluxseg6ei64.v v4,0\(a0\),v12', extension `v' or `zve64x' required > +.*Error: unrecognized opcode `vluxseg6ei64.v v4,\(a0\),v12,v0.t', extension `v' or `zve64x' required > +.*Error: unrecognized opcode `vsuxseg6ei64.v v4,\(a0\),v12', extension `v' or `zve64x' required > +.*Error: unrecognized opcode `vsuxseg6ei64.v v4,0\(a0\),v12', extension `v' or `zve64x' required > +.*Error: unrecognized opcode `vsuxseg6ei64.v v4,\(a0\),v12,v0.t', extension `v' or `zve64x' required > +.*Error: unrecognized opcode `vluxseg7ei64.v v4,\(a0\),v12', extension `v' or `zve64x' required > +.*Error: unrecognized opcode `vluxseg7ei64.v v4,0\(a0\),v12', extension `v' or `zve64x' required > +.*Error: unrecognized opcode `vluxseg7ei64.v v4,\(a0\),v12,v0.t', extension `v' or `zve64x' required > +.*Error: unrecognized opcode `vsuxseg7ei64.v v4,\(a0\),v12', extension `v' or `zve64x' required > +.*Error: unrecognized opcode `vsuxseg7ei64.v v4,0\(a0\),v12', extension `v' or `zve64x' required > +.*Error: unrecognized opcode `vsuxseg7ei64.v v4,\(a0\),v12,v0.t', extension `v' or `zve64x' required > +.*Error: unrecognized opcode `vluxseg8ei64.v v4,\(a0\),v12', extension `v' or `zve64x' required > +.*Error: unrecognized opcode `vluxseg8ei64.v v4,0\(a0\),v12', extension `v' or `zve64x' required > +.*Error: unrecognized opcode `vluxseg8ei64.v v4,\(a0\),v12,v0.t', extension `v' or `zve64x' required > +.*Error: unrecognized opcode `vsuxseg8ei64.v v4,\(a0\),v12', extension `v' or `zve64x' required > +.*Error: unrecognized opcode `vsuxseg8ei64.v v4,0\(a0\),v12', extension `v' or `zve64x' required > +.*Error: unrecognized opcode `vsuxseg8ei64.v v4,\(a0\),v12,v0.t', extension `v' or `zve64x' required > +.*Error: unrecognized opcode `vlseg2e64ff.v v4,\(a0\)', extension `v' or `zve64x' required > +.*Error: unrecognized opcode `vlseg2e64ff.v v4,0\(a0\)', extension `v' or `zve64x' required > +.*Error: unrecognized opcode `vlseg2e64ff.v v4,\(a0\),v0.t', extension `v' or `zve64x' required > +.*Error: unrecognized opcode `vlseg3e64ff.v v4,\(a0\)', extension `v' or `zve64x' required > +.*Error: unrecognized opcode `vlseg3e64ff.v v4,0\(a0\)', extension `v' or `zve64x' required > +.*Error: unrecognized opcode `vlseg3e64ff.v v4,\(a0\),v0.t', extension `v' or `zve64x' required > +.*Error: unrecognized opcode `vlseg4e64ff.v v4,\(a0\)', extension `v' or `zve64x' required > +.*Error: unrecognized opcode `vlseg4e64ff.v v4,0\(a0\)', extension `v' or `zve64x' required > +.*Error: unrecognized opcode `vlseg4e64ff.v v4,\(a0\),v0.t', extension `v' or `zve64x' required > +.*Error: unrecognized opcode `vlseg5e64ff.v v4,\(a0\)', extension `v' or `zve64x' required > +.*Error: unrecognized opcode `vlseg5e64ff.v v4,0\(a0\)', extension `v' or `zve64x' required > +.*Error: unrecognized opcode `vlseg5e64ff.v v4,\(a0\),v0.t', extension `v' or `zve64x' required > +.*Error: unrecognized opcode `vlseg6e64ff.v v4,\(a0\)', extension `v' or `zve64x' required > +.*Error: unrecognized opcode `vlseg6e64ff.v v4,0\(a0\)', extension `v' or `zve64x' required > +.*Error: unrecognized opcode `vlseg6e64ff.v v4,\(a0\),v0.t', extension `v' or `zve64x' required > +.*Error: unrecognized opcode `vlseg7e64ff.v v4,\(a0\)', extension `v' or `zve64x' required > +.*Error: unrecognized opcode `vlseg7e64ff.v v4,0\(a0\)', extension `v' or `zve64x' required > +.*Error: unrecognized opcode `vlseg7e64ff.v v4,\(a0\),v0.t', extension `v' or `zve64x' required > +.*Error: unrecognized opcode `vlseg8e64ff.v v4,\(a0\)', extension `v' or `zve64x' required > +.*Error: unrecognized opcode `vlseg8e64ff.v v4,0\(a0\)', extension `v' or `zve64x' required > +.*Error: unrecognized opcode `vlseg8e64ff.v v4,\(a0\),v0.t', extension `v' or `zve64x' required > +.*Error: unrecognized opcode `vl1re64.v v3,\(a0\)', extension `v' or `zve64x' required > +.*Error: unrecognized opcode `vl1re64.v v3,0\(a0\)', extension `v' or `zve64x' required > +.*Error: unrecognized opcode `vl2re64.v v2,\(a0\)', extension `v' or `zve64x' required > +.*Error: unrecognized opcode `vl2re64.v v2,0\(a0\)', extension `v' or `zve64x' required > +.*Error: unrecognized opcode `vl4re64.v v4,\(a0\)', extension `v' or `zve64x' required > +.*Error: unrecognized opcode `vl4re64.v v4,0\(a0\)', extension `v' or `zve64x' required > +.*Error: unrecognized opcode `vl8re64.v v8,\(a0\)', extension `v' or `zve64x' required > +.*Error: unrecognized opcode `vl8re64.v v8,0\(a0\)', extension `v' or `zve64x' required > --- a/include/opcode/riscv.h > +++ b/include/opcode/riscv.h > @@ -560,6 +560,7 @@ enum riscv_insn_class > INSN_CLASS_ZBC_OR_ZBKC, > INSN_CLASS_ZKND_OR_ZKNE, > INSN_CLASS_V, > + INSN_CLASS_ZVE64X, > INSN_CLASS_ZVEF, > INSN_CLASS_ZVBB, > INSN_CLASS_ZVBC, > @@ -698,8 +699,6 @@ struct riscv_opcode > #define INSN_JSR 0x00000006 > /* Instruction is a data reference. */ > #define INSN_DREF 0x00000008 > -/* Instruction is allowed when eew >= 64. */ > -#define INSN_V_EEW64 0x10000000 > > /* We have 5 data reference sizes, which we can encode in 3 bits. */ > #define INSN_DATA_SIZE 0x00000070 > --- a/opcodes/riscv-dis.c > +++ b/opcodes/riscv-dis.c > @@ -1133,10 +1133,6 @@ riscv_disassemble_insn (bfd_vma memaddr, > if (!riscv_multi_subset_supports (&pd->riscv_rps_dis, > op->insn_class)) > continue; > - > - if ((op->pinfo & INSN_V_EEW64) > - && !riscv_subset_supports (&pd->riscv_rps_dis, "zve64x")) > - continue; > } > > /* It's a match. */ > --- a/opcodes/riscv-opc.c > +++ b/opcodes/riscv-opc.c > @@ -1493,47 +1493,47 @@ const struct riscv_opcode riscv_opcodes[ > {"vle8.v", 0, INSN_CLASS_V, "Vd,0(s)Vm", MATCH_VLE8V, MASK_VLE8V, match_opcode, INSN_DREF }, > {"vle16.v", 0, INSN_CLASS_V, "Vd,0(s)Vm", MATCH_VLE16V, MASK_VLE16V, match_opcode, INSN_DREF }, > {"vle32.v", 0, INSN_CLASS_V, "Vd,0(s)Vm", MATCH_VLE32V, MASK_VLE32V, match_opcode, INSN_DREF }, > -{"vle64.v", 0, INSN_CLASS_V, "Vd,0(s)Vm", MATCH_VLE64V, MASK_VLE64V, match_opcode, INSN_DREF|INSN_V_EEW64 }, > +{"vle64.v", 0, INSN_CLASS_ZVE64X, "Vd,0(s)Vm", MATCH_VLE64V, MASK_VLE64V, match_opcode, INSN_DREF }, > > {"vse8.v", 0, INSN_CLASS_V, "Vd,0(s)Vm", MATCH_VSE8V, MASK_VSE8V, match_opcode, INSN_DREF }, > {"vse16.v", 0, INSN_CLASS_V, "Vd,0(s)Vm", MATCH_VSE16V, MASK_VSE16V, match_opcode, INSN_DREF }, > {"vse32.v", 0, INSN_CLASS_V, "Vd,0(s)Vm", MATCH_VSE32V, MASK_VSE32V, match_opcode, INSN_DREF }, > -{"vse64.v", 0, INSN_CLASS_V, "Vd,0(s)Vm", MATCH_VSE64V, MASK_VSE64V, match_opcode, INSN_DREF|INSN_V_EEW64 }, > +{"vse64.v", 0, INSN_CLASS_ZVE64X, "Vd,0(s)Vm", MATCH_VSE64V, MASK_VSE64V, match_opcode, INSN_DREF }, > > {"vlse8.v", 0, INSN_CLASS_V, "Vd,0(s),tVm", MATCH_VLSE8V, MASK_VLSE8V, match_opcode, INSN_DREF }, > {"vlse16.v", 0, INSN_CLASS_V, "Vd,0(s),tVm", MATCH_VLSE16V, MASK_VLSE16V, match_opcode, INSN_DREF }, > {"vlse32.v", 0, INSN_CLASS_V, "Vd,0(s),tVm", MATCH_VLSE32V, MASK_VLSE32V, match_opcode, INSN_DREF }, > -{"vlse64.v", 0, INSN_CLASS_V, "Vd,0(s),tVm", MATCH_VLSE64V, MASK_VLSE64V, match_opcode, INSN_DREF|INSN_V_EEW64 }, > +{"vlse64.v", 0, INSN_CLASS_ZVE64X, "Vd,0(s),tVm", MATCH_VLSE64V, MASK_VLSE64V, match_opcode, INSN_DREF }, > > {"vsse8.v", 0, INSN_CLASS_V, "Vd,0(s),tVm", MATCH_VSSE8V, MASK_VSSE8V, match_opcode, INSN_DREF }, > {"vsse16.v", 0, INSN_CLASS_V, "Vd,0(s),tVm", MATCH_VSSE16V, MASK_VSSE16V, match_opcode, INSN_DREF }, > {"vsse32.v", 0, INSN_CLASS_V, "Vd,0(s),tVm", MATCH_VSSE32V, MASK_VSSE32V, match_opcode, INSN_DREF }, > -{"vsse64.v", 0, INSN_CLASS_V, "Vd,0(s),tVm", MATCH_VSSE64V, MASK_VSSE64V, match_opcode, INSN_DREF|INSN_V_EEW64 }, > +{"vsse64.v", 0, INSN_CLASS_ZVE64X, "Vd,0(s),tVm", MATCH_VSSE64V, MASK_VSSE64V, match_opcode, INSN_DREF }, > > {"vloxei8.v", 0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VLOXEI8V, MASK_VLOXEI8V, match_opcode, INSN_DREF }, > {"vloxei16.v", 0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VLOXEI16V, MASK_VLOXEI16V, match_opcode, INSN_DREF }, > {"vloxei32.v", 0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VLOXEI32V, MASK_VLOXEI32V, match_opcode, INSN_DREF }, > -{"vloxei64.v", 0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VLOXEI64V, MASK_VLOXEI64V, match_opcode, INSN_DREF|INSN_V_EEW64 }, > +{"vloxei64.v", 0, INSN_CLASS_ZVE64X, "Vd,0(s),VtVm", MATCH_VLOXEI64V, MASK_VLOXEI64V, match_opcode, INSN_DREF }, > > {"vsoxei8.v", 0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VSOXEI8V, MASK_VSOXEI8V, match_opcode, INSN_DREF }, > {"vsoxei16.v", 0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VSOXEI16V, MASK_VSOXEI16V, match_opcode, INSN_DREF }, > {"vsoxei32.v", 0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VSOXEI32V, MASK_VSOXEI32V, match_opcode, INSN_DREF }, > -{"vsoxei64.v", 0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VSOXEI64V, MASK_VSOXEI64V, match_opcode, INSN_DREF|INSN_V_EEW64 }, > +{"vsoxei64.v", 0, INSN_CLASS_ZVE64X, "Vd,0(s),VtVm", MATCH_VSOXEI64V, MASK_VSOXEI64V, match_opcode, INSN_DREF }, > > {"vluxei8.v", 0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VLUXEI8V, MASK_VLUXEI8V, match_opcode, INSN_DREF }, > {"vluxei16.v", 0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VLUXEI16V, MASK_VLUXEI16V, match_opcode, INSN_DREF }, > {"vluxei32.v", 0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VLUXEI32V, MASK_VLUXEI32V, match_opcode, INSN_DREF }, > -{"vluxei64.v", 0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VLUXEI64V, MASK_VLUXEI64V, match_opcode, INSN_DREF|INSN_V_EEW64 }, > +{"vluxei64.v", 0, INSN_CLASS_ZVE64X, "Vd,0(s),VtVm", MATCH_VLUXEI64V, MASK_VLUXEI64V, match_opcode, INSN_DREF }, > > {"vsuxei8.v", 0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VSUXEI8V, MASK_VSUXEI8V, match_opcode, INSN_DREF }, > {"vsuxei16.v", 0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VSUXEI16V, MASK_VSUXEI16V, match_opcode, INSN_DREF }, > {"vsuxei32.v", 0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VSUXEI32V, MASK_VSUXEI32V, match_opcode, INSN_DREF }, > -{"vsuxei64.v", 0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VSUXEI64V, MASK_VSUXEI64V, match_opcode, INSN_DREF|INSN_V_EEW64 }, > +{"vsuxei64.v", 0, INSN_CLASS_ZVE64X, "Vd,0(s),VtVm", MATCH_VSUXEI64V, MASK_VSUXEI64V, match_opcode, INSN_DREF }, > > {"vle8ff.v", 0, INSN_CLASS_V, "Vd,0(s)Vm", MATCH_VLE8FFV, MASK_VLE8FFV, match_opcode, INSN_DREF }, > {"vle16ff.v", 0, INSN_CLASS_V, "Vd,0(s)Vm", MATCH_VLE16FFV, MASK_VLE16FFV, match_opcode, INSN_DREF }, > {"vle32ff.v", 0, INSN_CLASS_V, "Vd,0(s)Vm", MATCH_VLE32FFV, MASK_VLE32FFV, match_opcode, INSN_DREF }, > -{"vle64ff.v", 0, INSN_CLASS_V, "Vd,0(s)Vm", MATCH_VLE64FFV, MASK_VLE64FFV, match_opcode, INSN_DREF|INSN_V_EEW64 }, > +{"vle64ff.v", 0, INSN_CLASS_ZVE64X, "Vd,0(s)Vm", MATCH_VLE64FFV, MASK_VLE64FFV, match_opcode, INSN_DREF }, > > {"vlseg2e8.v", 0, INSN_CLASS_V, "Vd,0(s)Vm", MATCH_VLSEG2E8V, MASK_VLSEG2E8V, match_opcode, INSN_DREF }, > {"vsseg2e8.v", 0, INSN_CLASS_V, "Vd,0(s)Vm", MATCH_VSSEG2E8V, MASK_VSSEG2E8V, match_opcode, INSN_DREF }, > @@ -1580,20 +1580,20 @@ const struct riscv_opcode riscv_opcodes[ > {"vlseg8e32.v", 0, INSN_CLASS_V, "Vd,0(s)Vm", MATCH_VLSEG8E32V, MASK_VLSEG8E32V, match_opcode, INSN_DREF }, > {"vsseg8e32.v", 0, INSN_CLASS_V, "Vd,0(s)Vm", MATCH_VSSEG8E32V, MASK_VSSEG8E32V, match_opcode, INSN_DREF }, > > -{"vlseg2e64.v", 0, INSN_CLASS_V, "Vd,0(s)Vm", MATCH_VLSEG2E64V, MASK_VLSEG2E64V, match_opcode, INSN_DREF|INSN_V_EEW64 }, > -{"vsseg2e64.v", 0, INSN_CLASS_V, "Vd,0(s)Vm", MATCH_VSSEG2E64V, MASK_VSSEG2E64V, match_opcode, INSN_DREF|INSN_V_EEW64 }, > -{"vlseg3e64.v", 0, INSN_CLASS_V, "Vd,0(s)Vm", MATCH_VLSEG3E64V, MASK_VLSEG3E64V, match_opcode, INSN_DREF|INSN_V_EEW64 }, > -{"vsseg3e64.v", 0, INSN_CLASS_V, "Vd,0(s)Vm", MATCH_VSSEG3E64V, MASK_VSSEG3E64V, match_opcode, INSN_DREF|INSN_V_EEW64 }, > -{"vlseg4e64.v", 0, INSN_CLASS_V, "Vd,0(s)Vm", MATCH_VLSEG4E64V, MASK_VLSEG4E64V, match_opcode, INSN_DREF|INSN_V_EEW64 }, > -{"vsseg4e64.v", 0, INSN_CLASS_V, "Vd,0(s)Vm", MATCH_VSSEG4E64V, MASK_VSSEG4E64V, match_opcode, INSN_DREF|INSN_V_EEW64 }, > -{"vlseg5e64.v", 0, INSN_CLASS_V, "Vd,0(s)Vm", MATCH_VLSEG5E64V, MASK_VLSEG5E64V, match_opcode, INSN_DREF|INSN_V_EEW64 }, > -{"vsseg5e64.v", 0, INSN_CLASS_V, "Vd,0(s)Vm", MATCH_VSSEG5E64V, MASK_VSSEG5E64V, match_opcode, INSN_DREF|INSN_V_EEW64 }, > -{"vlseg6e64.v", 0, INSN_CLASS_V, "Vd,0(s)Vm", MATCH_VLSEG6E64V, MASK_VLSEG6E64V, match_opcode, INSN_DREF|INSN_V_EEW64 }, > -{"vsseg6e64.v", 0, INSN_CLASS_V, "Vd,0(s)Vm", MATCH_VSSEG6E64V, MASK_VSSEG6E64V, match_opcode, INSN_DREF|INSN_V_EEW64 }, > -{"vlseg7e64.v", 0, INSN_CLASS_V, "Vd,0(s)Vm", MATCH_VLSEG7E64V, MASK_VLSEG7E64V, match_opcode, INSN_DREF|INSN_V_EEW64 }, > -{"vsseg7e64.v", 0, INSN_CLASS_V, "Vd,0(s)Vm", MATCH_VSSEG7E64V, MASK_VSSEG7E64V, match_opcode, INSN_DREF|INSN_V_EEW64 }, > -{"vlseg8e64.v", 0, INSN_CLASS_V, "Vd,0(s)Vm", MATCH_VLSEG8E64V, MASK_VLSEG8E64V, match_opcode, INSN_DREF|INSN_V_EEW64 }, > -{"vsseg8e64.v", 0, INSN_CLASS_V, "Vd,0(s)Vm", MATCH_VSSEG8E64V, MASK_VSSEG8E64V, match_opcode, INSN_DREF|INSN_V_EEW64 }, > +{"vlseg2e64.v", 0, INSN_CLASS_ZVE64X, "Vd,0(s)Vm", MATCH_VLSEG2E64V, MASK_VLSEG2E64V, match_opcode, INSN_DREF }, > +{"vsseg2e64.v", 0, INSN_CLASS_ZVE64X, "Vd,0(s)Vm", MATCH_VSSEG2E64V, MASK_VSSEG2E64V, match_opcode, INSN_DREF }, > +{"vlseg3e64.v", 0, INSN_CLASS_ZVE64X, "Vd,0(s)Vm", MATCH_VLSEG3E64V, MASK_VLSEG3E64V, match_opcode, INSN_DREF }, > +{"vsseg3e64.v", 0, INSN_CLASS_ZVE64X, "Vd,0(s)Vm", MATCH_VSSEG3E64V, MASK_VSSEG3E64V, match_opcode, INSN_DREF }, > +{"vlseg4e64.v", 0, INSN_CLASS_ZVE64X, "Vd,0(s)Vm", MATCH_VLSEG4E64V, MASK_VLSEG4E64V, match_opcode, INSN_DREF }, > +{"vsseg4e64.v", 0, INSN_CLASS_ZVE64X, "Vd,0(s)Vm", MATCH_VSSEG4E64V, MASK_VSSEG4E64V, match_opcode, INSN_DREF }, > +{"vlseg5e64.v", 0, INSN_CLASS_ZVE64X, "Vd,0(s)Vm", MATCH_VLSEG5E64V, MASK_VLSEG5E64V, match_opcode, INSN_DREF }, > +{"vsseg5e64.v", 0, INSN_CLASS_ZVE64X, "Vd,0(s)Vm", MATCH_VSSEG5E64V, MASK_VSSEG5E64V, match_opcode, INSN_DREF }, > +{"vlseg6e64.v", 0, INSN_CLASS_ZVE64X, "Vd,0(s)Vm", MATCH_VLSEG6E64V, MASK_VLSEG6E64V, match_opcode, INSN_DREF }, > +{"vsseg6e64.v", 0, INSN_CLASS_ZVE64X, "Vd,0(s)Vm", MATCH_VSSEG6E64V, MASK_VSSEG6E64V, match_opcode, INSN_DREF }, > +{"vlseg7e64.v", 0, INSN_CLASS_ZVE64X, "Vd,0(s)Vm", MATCH_VLSEG7E64V, MASK_VLSEG7E64V, match_opcode, INSN_DREF }, > +{"vsseg7e64.v", 0, INSN_CLASS_ZVE64X, "Vd,0(s)Vm", MATCH_VSSEG7E64V, MASK_VSSEG7E64V, match_opcode, INSN_DREF }, > +{"vlseg8e64.v", 0, INSN_CLASS_ZVE64X, "Vd,0(s)Vm", MATCH_VLSEG8E64V, MASK_VLSEG8E64V, match_opcode, INSN_DREF }, > +{"vsseg8e64.v", 0, INSN_CLASS_ZVE64X, "Vd,0(s)Vm", MATCH_VSSEG8E64V, MASK_VSSEG8E64V, match_opcode, INSN_DREF }, > > {"vlsseg2e8.v", 0, INSN_CLASS_V, "Vd,0(s),tVm", MATCH_VLSSEG2E8V, MASK_VLSSEG2E8V, match_opcode, INSN_DREF }, > {"vssseg2e8.v", 0, INSN_CLASS_V, "Vd,0(s),tVm", MATCH_VSSSEG2E8V, MASK_VSSSEG2E8V, match_opcode, INSN_DREF }, > @@ -1640,20 +1640,20 @@ const struct riscv_opcode riscv_opcodes[ > {"vlsseg8e32.v", 0, INSN_CLASS_V, "Vd,0(s),tVm", MATCH_VLSSEG8E32V, MASK_VLSSEG8E32V, match_opcode, INSN_DREF }, > {"vssseg8e32.v", 0, INSN_CLASS_V, "Vd,0(s),tVm", MATCH_VSSSEG8E32V, MASK_VSSSEG8E32V, match_opcode, INSN_DREF }, > > -{"vlsseg2e64.v", 0, INSN_CLASS_V, "Vd,0(s),tVm", MATCH_VLSSEG2E64V, MASK_VLSSEG2E64V, match_opcode, INSN_DREF|INSN_V_EEW64 }, > -{"vssseg2e64.v", 0, INSN_CLASS_V, "Vd,0(s),tVm", MATCH_VSSSEG2E64V, MASK_VSSSEG2E64V, match_opcode, INSN_DREF|INSN_V_EEW64 }, > -{"vlsseg3e64.v", 0, INSN_CLASS_V, "Vd,0(s),tVm", MATCH_VLSSEG3E64V, MASK_VLSSEG3E64V, match_opcode, INSN_DREF|INSN_V_EEW64 }, > -{"vssseg3e64.v", 0, INSN_CLASS_V, "Vd,0(s),tVm", MATCH_VSSSEG3E64V, MASK_VSSSEG3E64V, match_opcode, INSN_DREF|INSN_V_EEW64 }, > -{"vlsseg4e64.v", 0, INSN_CLASS_V, "Vd,0(s),tVm", MATCH_VLSSEG4E64V, MASK_VLSSEG4E64V, match_opcode, INSN_DREF|INSN_V_EEW64 }, > -{"vssseg4e64.v", 0, INSN_CLASS_V, "Vd,0(s),tVm", MATCH_VSSSEG4E64V, MASK_VSSSEG4E64V, match_opcode, INSN_DREF|INSN_V_EEW64 }, > -{"vlsseg5e64.v", 0, INSN_CLASS_V, "Vd,0(s),tVm", MATCH_VLSSEG5E64V, MASK_VLSSEG5E64V, match_opcode, INSN_DREF|INSN_V_EEW64 }, > -{"vssseg5e64.v", 0, INSN_CLASS_V, "Vd,0(s),tVm", MATCH_VSSSEG5E64V, MASK_VSSSEG5E64V, match_opcode, INSN_DREF|INSN_V_EEW64 }, > -{"vlsseg6e64.v", 0, INSN_CLASS_V, "Vd,0(s),tVm", MATCH_VLSSEG6E64V, MASK_VLSSEG6E64V, match_opcode, INSN_DREF|INSN_V_EEW64 }, > -{"vssseg6e64.v", 0, INSN_CLASS_V, "Vd,0(s),tVm", MATCH_VSSSEG6E64V, MASK_VSSSEG6E64V, match_opcode, INSN_DREF|INSN_V_EEW64 }, > -{"vlsseg7e64.v", 0, INSN_CLASS_V, "Vd,0(s),tVm", MATCH_VLSSEG7E64V, MASK_VLSSEG7E64V, match_opcode, INSN_DREF|INSN_V_EEW64 }, > -{"vssseg7e64.v", 0, INSN_CLASS_V, "Vd,0(s),tVm", MATCH_VSSSEG7E64V, MASK_VSSSEG7E64V, match_opcode, INSN_DREF|INSN_V_EEW64 }, > -{"vlsseg8e64.v", 0, INSN_CLASS_V, "Vd,0(s),tVm", MATCH_VLSSEG8E64V, MASK_VLSSEG8E64V, match_opcode, INSN_DREF|INSN_V_EEW64 }, > -{"vssseg8e64.v", 0, INSN_CLASS_V, "Vd,0(s),tVm", MATCH_VSSSEG8E64V, MASK_VSSSEG8E64V, match_opcode, INSN_DREF|INSN_V_EEW64 }, > +{"vlsseg2e64.v", 0, INSN_CLASS_ZVE64X, "Vd,0(s),tVm", MATCH_VLSSEG2E64V, MASK_VLSSEG2E64V, match_opcode, INSN_DREF }, > +{"vssseg2e64.v", 0, INSN_CLASS_ZVE64X, "Vd,0(s),tVm", MATCH_VSSSEG2E64V, MASK_VSSSEG2E64V, match_opcode, INSN_DREF }, > +{"vlsseg3e64.v", 0, INSN_CLASS_ZVE64X, "Vd,0(s),tVm", MATCH_VLSSEG3E64V, MASK_VLSSEG3E64V, match_opcode, INSN_DREF }, > +{"vssseg3e64.v", 0, INSN_CLASS_ZVE64X, "Vd,0(s),tVm", MATCH_VSSSEG3E64V, MASK_VSSSEG3E64V, match_opcode, INSN_DREF }, > +{"vlsseg4e64.v", 0, INSN_CLASS_ZVE64X, "Vd,0(s),tVm", MATCH_VLSSEG4E64V, MASK_VLSSEG4E64V, match_opcode, INSN_DREF }, > +{"vssseg4e64.v", 0, INSN_CLASS_ZVE64X, "Vd,0(s),tVm", MATCH_VSSSEG4E64V, MASK_VSSSEG4E64V, match_opcode, INSN_DREF }, > +{"vlsseg5e64.v", 0, INSN_CLASS_ZVE64X, "Vd,0(s),tVm", MATCH_VLSSEG5E64V, MASK_VLSSEG5E64V, match_opcode, INSN_DREF }, > +{"vssseg5e64.v", 0, INSN_CLASS_ZVE64X, "Vd,0(s),tVm", MATCH_VSSSEG5E64V, MASK_VSSSEG5E64V, match_opcode, INSN_DREF }, > +{"vlsseg6e64.v", 0, INSN_CLASS_ZVE64X, "Vd,0(s),tVm", MATCH_VLSSEG6E64V, MASK_VLSSEG6E64V, match_opcode, INSN_DREF }, > +{"vssseg6e64.v", 0, INSN_CLASS_ZVE64X, "Vd,0(s),tVm", MATCH_VSSSEG6E64V, MASK_VSSSEG6E64V, match_opcode, INSN_DREF }, > +{"vlsseg7e64.v", 0, INSN_CLASS_ZVE64X, "Vd,0(s),tVm", MATCH_VLSSEG7E64V, MASK_VLSSEG7E64V, match_opcode, INSN_DREF }, > +{"vssseg7e64.v", 0, INSN_CLASS_ZVE64X, "Vd,0(s),tVm", MATCH_VSSSEG7E64V, MASK_VSSSEG7E64V, match_opcode, INSN_DREF }, > +{"vlsseg8e64.v", 0, INSN_CLASS_ZVE64X, "Vd,0(s),tVm", MATCH_VLSSEG8E64V, MASK_VLSSEG8E64V, match_opcode, INSN_DREF }, > +{"vssseg8e64.v", 0, INSN_CLASS_ZVE64X, "Vd,0(s),tVm", MATCH_VSSSEG8E64V, MASK_VSSSEG8E64V, match_opcode, INSN_DREF }, > > {"vloxseg2ei8.v", 0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VLOXSEG2EI8V, MASK_VLOXSEG2EI8V, match_opcode, INSN_DREF }, > {"vsoxseg2ei8.v", 0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VSOXSEG2EI8V, MASK_VSOXSEG2EI8V, match_opcode, INSN_DREF }, > @@ -1700,20 +1700,20 @@ const struct riscv_opcode riscv_opcodes[ > {"vloxseg8ei32.v", 0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VLOXSEG8EI32V, MASK_VLOXSEG8EI32V, match_opcode, INSN_DREF }, > {"vsoxseg8ei32.v", 0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VSOXSEG8EI32V, MASK_VSOXSEG8EI32V, match_opcode, INSN_DREF }, > > -{"vloxseg2ei64.v", 0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VLOXSEG2EI64V, MASK_VLOXSEG2EI64V, match_opcode, INSN_DREF|INSN_V_EEW64 }, > -{"vsoxseg2ei64.v", 0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VSOXSEG2EI64V, MASK_VSOXSEG2EI64V, match_opcode, INSN_DREF|INSN_V_EEW64 }, > -{"vloxseg3ei64.v", 0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VLOXSEG3EI64V, MASK_VLOXSEG3EI64V, match_opcode, INSN_DREF|INSN_V_EEW64 }, > -{"vsoxseg3ei64.v", 0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VSOXSEG3EI64V, MASK_VSOXSEG3EI64V, match_opcode, INSN_DREF|INSN_V_EEW64 }, > -{"vloxseg4ei64.v", 0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VLOXSEG4EI64V, MASK_VLOXSEG4EI64V, match_opcode, INSN_DREF|INSN_V_EEW64 }, > -{"vsoxseg4ei64.v", 0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VSOXSEG4EI64V, MASK_VSOXSEG4EI64V, match_opcode, INSN_DREF|INSN_V_EEW64 }, > -{"vloxseg5ei64.v", 0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VLOXSEG5EI64V, MASK_VLOXSEG5EI64V, match_opcode, INSN_DREF|INSN_V_EEW64 }, > -{"vsoxseg5ei64.v", 0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VSOXSEG5EI64V, MASK_VSOXSEG5EI64V, match_opcode, INSN_DREF|INSN_V_EEW64 }, > -{"vloxseg6ei64.v", 0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VLOXSEG6EI64V, MASK_VLOXSEG6EI64V, match_opcode, INSN_DREF|INSN_V_EEW64 }, > -{"vsoxseg6ei64.v", 0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VSOXSEG6EI64V, MASK_VSOXSEG6EI64V, match_opcode, INSN_DREF|INSN_V_EEW64 }, > -{"vloxseg7ei64.v", 0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VLOXSEG7EI64V, MASK_VLOXSEG7EI64V, match_opcode, INSN_DREF|INSN_V_EEW64 }, > -{"vsoxseg7ei64.v", 0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VSOXSEG7EI64V, MASK_VSOXSEG7EI64V, match_opcode, INSN_DREF|INSN_V_EEW64 }, > -{"vloxseg8ei64.v", 0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VLOXSEG8EI64V, MASK_VLOXSEG8EI64V, match_opcode, INSN_DREF|INSN_V_EEW64 }, > -{"vsoxseg8ei64.v", 0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VSOXSEG8EI64V, MASK_VSOXSEG8EI64V, match_opcode, INSN_DREF|INSN_V_EEW64 }, > +{"vloxseg2ei64.v", 0, INSN_CLASS_ZVE64X, "Vd,0(s),VtVm", MATCH_VLOXSEG2EI64V, MASK_VLOXSEG2EI64V, match_opcode, INSN_DREF }, > +{"vsoxseg2ei64.v", 0, INSN_CLASS_ZVE64X, "Vd,0(s),VtVm", MATCH_VSOXSEG2EI64V, MASK_VSOXSEG2EI64V, match_opcode, INSN_DREF }, > +{"vloxseg3ei64.v", 0, INSN_CLASS_ZVE64X, "Vd,0(s),VtVm", MATCH_VLOXSEG3EI64V, MASK_VLOXSEG3EI64V, match_opcode, INSN_DREF }, > +{"vsoxseg3ei64.v", 0, INSN_CLASS_ZVE64X, "Vd,0(s),VtVm", MATCH_VSOXSEG3EI64V, MASK_VSOXSEG3EI64V, match_opcode, INSN_DREF }, > +{"vloxseg4ei64.v", 0, INSN_CLASS_ZVE64X, "Vd,0(s),VtVm", MATCH_VLOXSEG4EI64V, MASK_VLOXSEG4EI64V, match_opcode, INSN_DREF }, > +{"vsoxseg4ei64.v", 0, INSN_CLASS_ZVE64X, "Vd,0(s),VtVm", MATCH_VSOXSEG4EI64V, MASK_VSOXSEG4EI64V, match_opcode, INSN_DREF }, > +{"vloxseg5ei64.v", 0, INSN_CLASS_ZVE64X, "Vd,0(s),VtVm", MATCH_VLOXSEG5EI64V, MASK_VLOXSEG5EI64V, match_opcode, INSN_DREF }, > +{"vsoxseg5ei64.v", 0, INSN_CLASS_ZVE64X, "Vd,0(s),VtVm", MATCH_VSOXSEG5EI64V, MASK_VSOXSEG5EI64V, match_opcode, INSN_DREF }, > +{"vloxseg6ei64.v", 0, INSN_CLASS_ZVE64X, "Vd,0(s),VtVm", MATCH_VLOXSEG6EI64V, MASK_VLOXSEG6EI64V, match_opcode, INSN_DREF }, > +{"vsoxseg6ei64.v", 0, INSN_CLASS_ZVE64X, "Vd,0(s),VtVm", MATCH_VSOXSEG6EI64V, MASK_VSOXSEG6EI64V, match_opcode, INSN_DREF }, > +{"vloxseg7ei64.v", 0, INSN_CLASS_ZVE64X, "Vd,0(s),VtVm", MATCH_VLOXSEG7EI64V, MASK_VLOXSEG7EI64V, match_opcode, INSN_DREF }, > +{"vsoxseg7ei64.v", 0, INSN_CLASS_ZVE64X, "Vd,0(s),VtVm", MATCH_VSOXSEG7EI64V, MASK_VSOXSEG7EI64V, match_opcode, INSN_DREF }, > +{"vloxseg8ei64.v", 0, INSN_CLASS_ZVE64X, "Vd,0(s),VtVm", MATCH_VLOXSEG8EI64V, MASK_VLOXSEG8EI64V, match_opcode, INSN_DREF }, > +{"vsoxseg8ei64.v", 0, INSN_CLASS_ZVE64X, "Vd,0(s),VtVm", MATCH_VSOXSEG8EI64V, MASK_VSOXSEG8EI64V, match_opcode, INSN_DREF }, > > {"vluxseg2ei8.v", 0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VLUXSEG2EI8V, MASK_VLUXSEG2EI8V, match_opcode, INSN_DREF }, > {"vsuxseg2ei8.v", 0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VSUXSEG2EI8V, MASK_VSUXSEG2EI8V, match_opcode, INSN_DREF }, > @@ -1760,20 +1760,20 @@ const struct riscv_opcode riscv_opcodes[ > {"vluxseg8ei32.v", 0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VLUXSEG8EI32V, MASK_VLUXSEG8EI32V, match_opcode, INSN_DREF }, > {"vsuxseg8ei32.v", 0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VSUXSEG8EI32V, MASK_VSUXSEG8EI32V, match_opcode, INSN_DREF }, > > -{"vluxseg2ei64.v", 0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VLUXSEG2EI64V, MASK_VLUXSEG2EI64V, match_opcode, INSN_DREF|INSN_V_EEW64 }, > -{"vsuxseg2ei64.v", 0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VSUXSEG2EI64V, MASK_VSUXSEG2EI64V, match_opcode, INSN_DREF|INSN_V_EEW64 }, > -{"vluxseg3ei64.v", 0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VLUXSEG3EI64V, MASK_VLUXSEG3EI64V, match_opcode, INSN_DREF|INSN_V_EEW64 }, > -{"vsuxseg3ei64.v", 0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VSUXSEG3EI64V, MASK_VSUXSEG3EI64V, match_opcode, INSN_DREF|INSN_V_EEW64 }, > -{"vluxseg4ei64.v", 0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VLUXSEG4EI64V, MASK_VLUXSEG4EI64V, match_opcode, INSN_DREF|INSN_V_EEW64 }, > -{"vsuxseg4ei64.v", 0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VSUXSEG4EI64V, MASK_VSUXSEG4EI64V, match_opcode, INSN_DREF|INSN_V_EEW64 }, > -{"vluxseg5ei64.v", 0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VLUXSEG5EI64V, MASK_VLUXSEG5EI64V, match_opcode, INSN_DREF|INSN_V_EEW64 }, > -{"vsuxseg5ei64.v", 0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VSUXSEG5EI64V, MASK_VSUXSEG5EI64V, match_opcode, INSN_DREF|INSN_V_EEW64 }, > -{"vluxseg6ei64.v", 0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VLUXSEG6EI64V, MASK_VLUXSEG6EI64V, match_opcode, INSN_DREF|INSN_V_EEW64 }, > -{"vsuxseg6ei64.v", 0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VSUXSEG6EI64V, MASK_VSUXSEG6EI64V, match_opcode, INSN_DREF|INSN_V_EEW64 }, > -{"vluxseg7ei64.v", 0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VLUXSEG7EI64V, MASK_VLUXSEG7EI64V, match_opcode, INSN_DREF|INSN_V_EEW64 }, > -{"vsuxseg7ei64.v", 0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VSUXSEG7EI64V, MASK_VSUXSEG7EI64V, match_opcode, INSN_DREF|INSN_V_EEW64 }, > -{"vluxseg8ei64.v", 0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VLUXSEG8EI64V, MASK_VLUXSEG8EI64V, match_opcode, INSN_DREF|INSN_V_EEW64 }, > -{"vsuxseg8ei64.v", 0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VSUXSEG8EI64V, MASK_VSUXSEG8EI64V, match_opcode, INSN_DREF|INSN_V_EEW64 }, > +{"vluxseg2ei64.v", 0, INSN_CLASS_ZVE64X, "Vd,0(s),VtVm", MATCH_VLUXSEG2EI64V, MASK_VLUXSEG2EI64V, match_opcode, INSN_DREF }, > +{"vsuxseg2ei64.v", 0, INSN_CLASS_ZVE64X, "Vd,0(s),VtVm", MATCH_VSUXSEG2EI64V, MASK_VSUXSEG2EI64V, match_opcode, INSN_DREF }, > +{"vluxseg3ei64.v", 0, INSN_CLASS_ZVE64X, "Vd,0(s),VtVm", MATCH_VLUXSEG3EI64V, MASK_VLUXSEG3EI64V, match_opcode, INSN_DREF }, > +{"vsuxseg3ei64.v", 0, INSN_CLASS_ZVE64X, "Vd,0(s),VtVm", MATCH_VSUXSEG3EI64V, MASK_VSUXSEG3EI64V, match_opcode, INSN_DREF }, > +{"vluxseg4ei64.v", 0, INSN_CLASS_ZVE64X, "Vd,0(s),VtVm", MATCH_VLUXSEG4EI64V, MASK_VLUXSEG4EI64V, match_opcode, INSN_DREF }, > +{"vsuxseg4ei64.v", 0, INSN_CLASS_ZVE64X, "Vd,0(s),VtVm", MATCH_VSUXSEG4EI64V, MASK_VSUXSEG4EI64V, match_opcode, INSN_DREF }, > +{"vluxseg5ei64.v", 0, INSN_CLASS_ZVE64X, "Vd,0(s),VtVm", MATCH_VLUXSEG5EI64V, MASK_VLUXSEG5EI64V, match_opcode, INSN_DREF }, > +{"vsuxseg5ei64.v", 0, INSN_CLASS_ZVE64X, "Vd,0(s),VtVm", MATCH_VSUXSEG5EI64V, MASK_VSUXSEG5EI64V, match_opcode, INSN_DREF }, > +{"vluxseg6ei64.v", 0, INSN_CLASS_ZVE64X, "Vd,0(s),VtVm", MATCH_VLUXSEG6EI64V, MASK_VLUXSEG6EI64V, match_opcode, INSN_DREF }, > +{"vsuxseg6ei64.v", 0, INSN_CLASS_ZVE64X, "Vd,0(s),VtVm", MATCH_VSUXSEG6EI64V, MASK_VSUXSEG6EI64V, match_opcode, INSN_DREF }, > +{"vluxseg7ei64.v", 0, INSN_CLASS_ZVE64X, "Vd,0(s),VtVm", MATCH_VLUXSEG7EI64V, MASK_VLUXSEG7EI64V, match_opcode, INSN_DREF }, > +{"vsuxseg7ei64.v", 0, INSN_CLASS_ZVE64X, "Vd,0(s),VtVm", MATCH_VSUXSEG7EI64V, MASK_VSUXSEG7EI64V, match_opcode, INSN_DREF }, > +{"vluxseg8ei64.v", 0, INSN_CLASS_ZVE64X, "Vd,0(s),VtVm", MATCH_VLUXSEG8EI64V, MASK_VLUXSEG8EI64V, match_opcode, INSN_DREF }, > +{"vsuxseg8ei64.v", 0, INSN_CLASS_ZVE64X, "Vd,0(s),VtVm", MATCH_VSUXSEG8EI64V, MASK_VSUXSEG8EI64V, match_opcode, INSN_DREF }, > > {"vlseg2e8ff.v", 0, INSN_CLASS_V, "Vd,0(s)Vm", MATCH_VLSEG2E8FFV, MASK_VLSEG2E8FFV, match_opcode, INSN_DREF }, > {"vlseg3e8ff.v", 0, INSN_CLASS_V, "Vd,0(s)Vm", MATCH_VLSEG3E8FFV, MASK_VLSEG3E8FFV, match_opcode, INSN_DREF }, > @@ -1799,37 +1799,37 @@ const struct riscv_opcode riscv_opcodes[ > {"vlseg7e32ff.v", 0, INSN_CLASS_V, "Vd,0(s)Vm", MATCH_VLSEG7E32FFV, MASK_VLSEG7E32FFV, match_opcode, INSN_DREF }, > {"vlseg8e32ff.v", 0, INSN_CLASS_V, "Vd,0(s)Vm", MATCH_VLSEG8E32FFV, MASK_VLSEG8E32FFV, match_opcode, INSN_DREF }, > > -{"vlseg2e64ff.v", 0, INSN_CLASS_V, "Vd,0(s)Vm", MATCH_VLSEG2E64FFV, MASK_VLSEG2E64FFV, match_opcode, INSN_DREF|INSN_V_EEW64 }, > -{"vlseg3e64ff.v", 0, INSN_CLASS_V, "Vd,0(s)Vm", MATCH_VLSEG3E64FFV, MASK_VLSEG3E64FFV, match_opcode, INSN_DREF|INSN_V_EEW64 }, > -{"vlseg4e64ff.v", 0, INSN_CLASS_V, "Vd,0(s)Vm", MATCH_VLSEG4E64FFV, MASK_VLSEG4E64FFV, match_opcode, INSN_DREF|INSN_V_EEW64 }, > -{"vlseg5e64ff.v", 0, INSN_CLASS_V, "Vd,0(s)Vm", MATCH_VLSEG5E64FFV, MASK_VLSEG5E64FFV, match_opcode, INSN_DREF|INSN_V_EEW64 }, > -{"vlseg6e64ff.v", 0, INSN_CLASS_V, "Vd,0(s)Vm", MATCH_VLSEG6E64FFV, MASK_VLSEG6E64FFV, match_opcode, INSN_DREF|INSN_V_EEW64 }, > -{"vlseg7e64ff.v", 0, INSN_CLASS_V, "Vd,0(s)Vm", MATCH_VLSEG7E64FFV, MASK_VLSEG7E64FFV, match_opcode, INSN_DREF|INSN_V_EEW64 }, > -{"vlseg8e64ff.v", 0, INSN_CLASS_V, "Vd,0(s)Vm", MATCH_VLSEG8E64FFV, MASK_VLSEG8E64FFV, match_opcode, INSN_DREF|INSN_V_EEW64 }, > +{"vlseg2e64ff.v", 0, INSN_CLASS_ZVE64X, "Vd,0(s)Vm", MATCH_VLSEG2E64FFV, MASK_VLSEG2E64FFV, match_opcode, INSN_DREF }, > +{"vlseg3e64ff.v", 0, INSN_CLASS_ZVE64X, "Vd,0(s)Vm", MATCH_VLSEG3E64FFV, MASK_VLSEG3E64FFV, match_opcode, INSN_DREF }, > +{"vlseg4e64ff.v", 0, INSN_CLASS_ZVE64X, "Vd,0(s)Vm", MATCH_VLSEG4E64FFV, MASK_VLSEG4E64FFV, match_opcode, INSN_DREF }, > +{"vlseg5e64ff.v", 0, INSN_CLASS_ZVE64X, "Vd,0(s)Vm", MATCH_VLSEG5E64FFV, MASK_VLSEG5E64FFV, match_opcode, INSN_DREF }, > +{"vlseg6e64ff.v", 0, INSN_CLASS_ZVE64X, "Vd,0(s)Vm", MATCH_VLSEG6E64FFV, MASK_VLSEG6E64FFV, match_opcode, INSN_DREF }, > +{"vlseg7e64ff.v", 0, INSN_CLASS_ZVE64X, "Vd,0(s)Vm", MATCH_VLSEG7E64FFV, MASK_VLSEG7E64FFV, match_opcode, INSN_DREF }, > +{"vlseg8e64ff.v", 0, INSN_CLASS_ZVE64X, "Vd,0(s)Vm", MATCH_VLSEG8E64FFV, MASK_VLSEG8E64FFV, match_opcode, INSN_DREF }, > > {"vl1r.v", 0, INSN_CLASS_V, "Vd,0(s)", MATCH_VL1RE8V, MASK_VL1RE8V, match_opcode, INSN_DREF|INSN_ALIAS }, > {"vl1re8.v", 0, INSN_CLASS_V, "Vd,0(s)", MATCH_VL1RE8V, MASK_VL1RE8V, match_opcode, INSN_DREF }, > {"vl1re16.v", 0, INSN_CLASS_V, "Vd,0(s)", MATCH_VL1RE16V, MASK_VL1RE16V, match_opcode, INSN_DREF }, > {"vl1re32.v", 0, INSN_CLASS_V, "Vd,0(s)", MATCH_VL1RE32V, MASK_VL1RE32V, match_opcode, INSN_DREF }, > -{"vl1re64.v", 0, INSN_CLASS_V, "Vd,0(s)", MATCH_VL1RE64V, MASK_VL1RE64V, match_opcode, INSN_DREF|INSN_V_EEW64 }, > +{"vl1re64.v", 0, INSN_CLASS_ZVE64X, "Vd,0(s)", MATCH_VL1RE64V, MASK_VL1RE64V, match_opcode, INSN_DREF }, > > {"vl2r.v", 0, INSN_CLASS_V, "Vd,0(s)", MATCH_VL2RE8V, MASK_VL2RE8V, match_opcode, INSN_DREF|INSN_ALIAS }, > {"vl2re8.v", 0, INSN_CLASS_V, "Vd,0(s)", MATCH_VL2RE8V, MASK_VL2RE8V, match_opcode, INSN_DREF }, > {"vl2re16.v", 0, INSN_CLASS_V, "Vd,0(s)", MATCH_VL2RE16V, MASK_VL2RE16V, match_opcode, INSN_DREF }, > {"vl2re32.v", 0, INSN_CLASS_V, "Vd,0(s)", MATCH_VL2RE32V, MASK_VL2RE32V, match_opcode, INSN_DREF }, > -{"vl2re64.v", 0, INSN_CLASS_V, "Vd,0(s)", MATCH_VL2RE64V, MASK_VL2RE64V, match_opcode, INSN_DREF|INSN_V_EEW64 }, > +{"vl2re64.v", 0, INSN_CLASS_ZVE64X, "Vd,0(s)", MATCH_VL2RE64V, MASK_VL2RE64V, match_opcode, INSN_DREF }, > > {"vl4r.v", 0, INSN_CLASS_V, "Vd,0(s)", MATCH_VL4RE8V, MASK_VL4RE8V, match_opcode, INSN_DREF|INSN_ALIAS }, > {"vl4re8.v", 0, INSN_CLASS_V, "Vd,0(s)", MATCH_VL4RE8V, MASK_VL4RE8V, match_opcode, INSN_DREF }, > {"vl4re16.v", 0, INSN_CLASS_V, "Vd,0(s)", MATCH_VL4RE16V, MASK_VL4RE16V, match_opcode, INSN_DREF }, > {"vl4re32.v", 0, INSN_CLASS_V, "Vd,0(s)", MATCH_VL4RE32V, MASK_VL4RE32V, match_opcode, INSN_DREF }, > -{"vl4re64.v", 0, INSN_CLASS_V, "Vd,0(s)", MATCH_VL4RE64V, MASK_VL4RE64V, match_opcode, INSN_DREF|INSN_V_EEW64 }, > +{"vl4re64.v", 0, INSN_CLASS_ZVE64X, "Vd,0(s)", MATCH_VL4RE64V, MASK_VL4RE64V, match_opcode, INSN_DREF }, > > {"vl8r.v", 0, INSN_CLASS_V, "Vd,0(s)", MATCH_VL8RE8V, MASK_VL8RE8V, match_opcode, INSN_DREF|INSN_ALIAS }, > {"vl8re8.v", 0, INSN_CLASS_V, "Vd,0(s)", MATCH_VL8RE8V, MASK_VL8RE8V, match_opcode, INSN_DREF }, > {"vl8re16.v", 0, INSN_CLASS_V, "Vd,0(s)", MATCH_VL8RE16V, MASK_VL8RE16V, match_opcode, INSN_DREF }, > {"vl8re32.v", 0, INSN_CLASS_V, "Vd,0(s)", MATCH_VL8RE32V, MASK_VL8RE32V, match_opcode, INSN_DREF }, > -{"vl8re64.v", 0, INSN_CLASS_V, "Vd,0(s)", MATCH_VL8RE64V, MASK_VL8RE64V, match_opcode, INSN_DREF|INSN_V_EEW64 }, > +{"vl8re64.v", 0, INSN_CLASS_ZVE64X, "Vd,0(s)", MATCH_VL8RE64V, MASK_VL8RE64V, match_opcode, INSN_DREF }, > > {"vs1r.v", 0, INSN_CLASS_V, "Vd,0(s)", MATCH_VS1RV, MASK_VS1RV, match_opcode, INSN_DREF }, > {"vs2r.v", 0, INSN_CLASS_V, "Vd,0(s)", MATCH_VS2RV, MASK_VS2RV, match_opcode, INSN_DREF }, >